mir_graph.h revision e8ae81453e1d6c19d7db2001a1e7b1849f74241c
1/* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_MIR_GRAPH_H_ 18#define ART_COMPILER_DEX_MIR_GRAPH_H_ 19 20#include <stdint.h> 21 22#include "dex_file.h" 23#include "dex_instruction.h" 24#include "compiler_ir.h" 25#include "invoke_type.h" 26#include "mir_field_info.h" 27#include "mir_method_info.h" 28#include "utils/arena_bit_vector.h" 29#include "utils/growable_array.h" 30#include "reg_location.h" 31#include "reg_storage.h" 32 33namespace art { 34 35enum InstructionAnalysisAttributePos { 36 kUninterestingOp = 0, 37 kArithmeticOp, 38 kFPOp, 39 kSingleOp, 40 kDoubleOp, 41 kIntOp, 42 kLongOp, 43 kBranchOp, 44 kInvokeOp, 45 kArrayOp, 46 kHeavyweightOp, 47 kSimpleConstOp, 48 kMoveOp, 49 kSwitch 50}; 51 52#define AN_NONE (1 << kUninterestingOp) 53#define AN_MATH (1 << kArithmeticOp) 54#define AN_FP (1 << kFPOp) 55#define AN_LONG (1 << kLongOp) 56#define AN_INT (1 << kIntOp) 57#define AN_SINGLE (1 << kSingleOp) 58#define AN_DOUBLE (1 << kDoubleOp) 59#define AN_FLOATMATH (1 << kFPOp) 60#define AN_BRANCH (1 << kBranchOp) 61#define AN_INVOKE (1 << kInvokeOp) 62#define AN_ARRAYOP (1 << kArrayOp) 63#define AN_HEAVYWEIGHT (1 << kHeavyweightOp) 64#define AN_SIMPLECONST (1 << kSimpleConstOp) 65#define AN_MOVE (1 << kMoveOp) 66#define AN_SWITCH (1 << kSwitch) 67#define AN_COMPUTATIONAL (AN_MATH | AN_ARRAYOP | AN_MOVE | AN_SIMPLECONST) 68 69enum DataFlowAttributePos { 70 kUA = 0, 71 kUB, 72 kUC, 73 kAWide, 74 kBWide, 75 kCWide, 76 kDA, 77 kIsMove, 78 kSetsConst, 79 kFormat35c, 80 kFormat3rc, 81 kNullCheckSrc0, // Null check of uses[0]. 82 kNullCheckSrc1, // Null check of uses[1]. 83 kNullCheckSrc2, // Null check of uses[2]. 84 kNullCheckOut0, // Null check out outgoing arg0. 85 kDstNonNull, // May assume dst is non-null. 86 kRetNonNull, // May assume retval is non-null. 87 kNullTransferSrc0, // Object copy src[0] -> dst. 88 kNullTransferSrcN, // Phi null check state transfer. 89 kRangeCheckSrc1, // Range check of uses[1]. 90 kRangeCheckSrc2, // Range check of uses[2]. 91 kRangeCheckSrc3, // Range check of uses[3]. 92 kFPA, 93 kFPB, 94 kFPC, 95 kCoreA, 96 kCoreB, 97 kCoreC, 98 kRefA, 99 kRefB, 100 kRefC, 101 kUsesMethodStar, // Implicit use of Method*. 102 kUsesIField, // Accesses an instance field (IGET/IPUT). 103 kUsesSField, // Accesses a static field (SGET/SPUT). 104 kDoLVN, // Worth computing local value numbers. 105}; 106 107#define DF_NOP UINT64_C(0) 108#define DF_UA (UINT64_C(1) << kUA) 109#define DF_UB (UINT64_C(1) << kUB) 110#define DF_UC (UINT64_C(1) << kUC) 111#define DF_A_WIDE (UINT64_C(1) << kAWide) 112#define DF_B_WIDE (UINT64_C(1) << kBWide) 113#define DF_C_WIDE (UINT64_C(1) << kCWide) 114#define DF_DA (UINT64_C(1) << kDA) 115#define DF_IS_MOVE (UINT64_C(1) << kIsMove) 116#define DF_SETS_CONST (UINT64_C(1) << kSetsConst) 117#define DF_FORMAT_35C (UINT64_C(1) << kFormat35c) 118#define DF_FORMAT_3RC (UINT64_C(1) << kFormat3rc) 119#define DF_NULL_CHK_0 (UINT64_C(1) << kNullCheckSrc0) 120#define DF_NULL_CHK_1 (UINT64_C(1) << kNullCheckSrc1) 121#define DF_NULL_CHK_2 (UINT64_C(1) << kNullCheckSrc2) 122#define DF_NULL_CHK_OUT0 (UINT64_C(1) << kNullCheckOut0) 123#define DF_NON_NULL_DST (UINT64_C(1) << kDstNonNull) 124#define DF_NON_NULL_RET (UINT64_C(1) << kRetNonNull) 125#define DF_NULL_TRANSFER_0 (UINT64_C(1) << kNullTransferSrc0) 126#define DF_NULL_TRANSFER_N (UINT64_C(1) << kNullTransferSrcN) 127#define DF_RANGE_CHK_1 (UINT64_C(1) << kRangeCheckSrc1) 128#define DF_RANGE_CHK_2 (UINT64_C(1) << kRangeCheckSrc2) 129#define DF_RANGE_CHK_3 (UINT64_C(1) << kRangeCheckSrc3) 130#define DF_FP_A (UINT64_C(1) << kFPA) 131#define DF_FP_B (UINT64_C(1) << kFPB) 132#define DF_FP_C (UINT64_C(1) << kFPC) 133#define DF_CORE_A (UINT64_C(1) << kCoreA) 134#define DF_CORE_B (UINT64_C(1) << kCoreB) 135#define DF_CORE_C (UINT64_C(1) << kCoreC) 136#define DF_REF_A (UINT64_C(1) << kRefA) 137#define DF_REF_B (UINT64_C(1) << kRefB) 138#define DF_REF_C (UINT64_C(1) << kRefC) 139#define DF_UMS (UINT64_C(1) << kUsesMethodStar) 140#define DF_IFIELD (UINT64_C(1) << kUsesIField) 141#define DF_SFIELD (UINT64_C(1) << kUsesSField) 142#define DF_LVN (UINT64_C(1) << kDoLVN) 143 144#define DF_HAS_USES (DF_UA | DF_UB | DF_UC) 145 146#define DF_HAS_DEFS (DF_DA) 147 148#define DF_HAS_NULL_CHKS (DF_NULL_CHK_0 | \ 149 DF_NULL_CHK_1 | \ 150 DF_NULL_CHK_2 | \ 151 DF_NULL_CHK_OUT0) 152 153#define DF_HAS_RANGE_CHKS (DF_RANGE_CHK_1 | \ 154 DF_RANGE_CHK_2 | \ 155 DF_RANGE_CHK_3) 156 157#define DF_HAS_NR_CHKS (DF_HAS_NULL_CHKS | \ 158 DF_HAS_RANGE_CHKS) 159 160#define DF_A_IS_REG (DF_UA | DF_DA) 161#define DF_B_IS_REG (DF_UB) 162#define DF_C_IS_REG (DF_UC) 163#define DF_IS_GETTER_OR_SETTER (DF_IS_GETTER | DF_IS_SETTER) 164#define DF_USES_FP (DF_FP_A | DF_FP_B | DF_FP_C) 165#define DF_NULL_TRANSFER (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N) 166enum OatMethodAttributes { 167 kIsLeaf, // Method is leaf. 168 kHasLoop, // Method contains simple loop. 169}; 170 171#define METHOD_IS_LEAF (1 << kIsLeaf) 172#define METHOD_HAS_LOOP (1 << kHasLoop) 173 174// Minimum field size to contain Dalvik v_reg number. 175#define VREG_NUM_WIDTH 16 176 177#define INVALID_SREG (-1) 178#define INVALID_VREG (0xFFFFU) 179#define INVALID_OFFSET (0xDEADF00FU) 180 181#define MIR_IGNORE_NULL_CHECK (1 << kMIRIgnoreNullCheck) 182#define MIR_NULL_CHECK_ONLY (1 << kMIRNullCheckOnly) 183#define MIR_IGNORE_RANGE_CHECK (1 << kMIRIgnoreRangeCheck) 184#define MIR_RANGE_CHECK_ONLY (1 << kMIRRangeCheckOnly) 185#define MIR_IGNORE_CLINIT_CHECK (1 << kMIRIgnoreClInitCheck) 186#define MIR_INLINED (1 << kMIRInlined) 187#define MIR_INLINED_PRED (1 << kMIRInlinedPred) 188#define MIR_CALLEE (1 << kMIRCallee) 189#define MIR_IGNORE_SUSPEND_CHECK (1 << kMIRIgnoreSuspendCheck) 190#define MIR_DUP (1 << kMIRDup) 191 192#define BLOCK_NAME_LEN 80 193 194typedef uint16_t BasicBlockId; 195static const BasicBlockId NullBasicBlockId = 0; 196static constexpr bool kLeafOptimization = false; 197 198/* 199 * In general, vreg/sreg describe Dalvik registers that originated with dx. However, 200 * it is useful to have compiler-generated temporary registers and have them treated 201 * in the same manner as dx-generated virtual registers. This struct records the SSA 202 * name of compiler-introduced temporaries. 203 */ 204struct CompilerTemp { 205 int32_t v_reg; // Virtual register number for temporary. 206 int32_t s_reg_low; // SSA name for low Dalvik word. 207}; 208 209enum CompilerTempType { 210 kCompilerTempVR, // A virtual register temporary. 211 kCompilerTempSpecialMethodPtr, // Temporary that keeps track of current method pointer. 212}; 213 214// When debug option enabled, records effectiveness of null and range check elimination. 215struct Checkstats { 216 int32_t null_checks; 217 int32_t null_checks_eliminated; 218 int32_t range_checks; 219 int32_t range_checks_eliminated; 220}; 221 222// Dataflow attributes of a basic block. 223struct BasicBlockDataFlow { 224 ArenaBitVector* use_v; 225 ArenaBitVector* def_v; 226 ArenaBitVector* live_in_v; 227 ArenaBitVector* phi_v; 228 int32_t* vreg_to_ssa_map_exit; 229 ArenaBitVector* ending_check_v; // For null check and class init check elimination. 230}; 231 232/* 233 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that 234 * uses/defs retain the Dalvik convention that long operations operate on a pair of 32-bit 235 * vregs. For example, "ADD_LONG v0, v2, v3" would have 2 defs (v0/v1) and 4 uses (v2/v3, v4/v5). 236 * Following SSA renaming, this is the primary struct used by code generators to locate 237 * operand and result registers. This is a somewhat confusing and unhelpful convention that 238 * we may want to revisit in the future. 239 * 240 * TODO: 241 * 1. Add accessors for uses/defs and make data private 242 * 2. Change fp_use/fp_def to a bit array (could help memory usage) 243 * 3. Combine array storage into internal array and handled via accessors from 1. 244 */ 245struct SSARepresentation { 246 int32_t* uses; 247 bool* fp_use; 248 int32_t* defs; 249 bool* fp_def; 250 int16_t num_uses_allocated; 251 int16_t num_defs_allocated; 252 int16_t num_uses; 253 int16_t num_defs; 254 255 static uint32_t GetStartUseIndex(Instruction::Code opcode); 256}; 257 258/* 259 * The Midlevel Intermediate Representation node, which may be largely considered a 260 * wrapper around a Dalvik byte code. 261 */ 262struct MIR { 263 /* 264 * TODO: remove embedded DecodedInstruction to save space, keeping only opcode. Recover 265 * additional fields on as-needed basis. Question: how to support MIR Pseudo-ops; probably 266 * need to carry aux data pointer. 267 */ 268 struct DecodedInstruction { 269 uint32_t vA; 270 uint32_t vB; 271 uint64_t vB_wide; /* for k51l */ 272 uint32_t vC; 273 uint32_t arg[5]; /* vC/D/E/F/G in invoke or filled-new-array */ 274 Instruction::Code opcode; 275 276 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { 277 } 278 279 /* 280 * Given a decoded instruction representing a const bytecode, it updates 281 * the out arguments with proper values as dictated by the constant bytecode. 282 */ 283 bool GetConstant(int64_t* ptr_value, bool* wide) const; 284 285 bool IsStore() const { 286 return ((Instruction::FlagsOf(opcode) & Instruction::kStore) == Instruction::kStore); 287 } 288 289 bool IsLoad() const { 290 return ((Instruction::FlagsOf(opcode) & Instruction::kLoad) == Instruction::kLoad); 291 } 292 293 bool IsConditionalBranch() const { 294 return (Instruction::FlagsOf(opcode) == (Instruction::kContinue | Instruction::kBranch)); 295 } 296 297 /** 298 * @brief Is the register C component of the decoded instruction a constant? 299 */ 300 bool IsCFieldOrConstant() const { 301 return ((Instruction::FlagsOf(opcode) & Instruction::kRegCFieldOrConstant) == Instruction::kRegCFieldOrConstant); 302 } 303 304 /** 305 * @brief Is the register C component of the decoded instruction a constant? 306 */ 307 bool IsBFieldOrConstant() const { 308 return ((Instruction::FlagsOf(opcode) & Instruction::kRegBFieldOrConstant) == Instruction::kRegBFieldOrConstant); 309 } 310 311 bool IsCast() const { 312 return ((Instruction::FlagsOf(opcode) & Instruction::kCast) == Instruction::kCast); 313 } 314 315 /** 316 * @brief Does the instruction clobber memory? 317 * @details Clobber means that the instruction changes the memory not in a punctual way. 318 * Therefore any supposition on memory aliasing or memory contents should be disregarded 319 * when crossing such an instruction. 320 */ 321 bool Clobbers() const { 322 return ((Instruction::FlagsOf(opcode) & Instruction::kClobber) == Instruction::kClobber); 323 } 324 325 bool IsLinear() const { 326 return (Instruction::FlagsOf(opcode) & (Instruction::kAdd | Instruction::kSubtract)) != 0; 327 } 328 } dalvikInsn; 329 330 NarrowDexOffset offset; // Offset of the instruction in code units. 331 uint16_t optimization_flags; 332 int16_t m_unit_index; // From which method was this MIR included 333 BasicBlockId bb; 334 MIR* next; 335 SSARepresentation* ssa_rep; 336 union { 337 // Incoming edges for phi node. 338 BasicBlockId* phi_incoming; 339 // Establish link from check instruction (kMirOpCheck) to the actual throwing instruction. 340 MIR* throw_insn; 341 // Branch condition for fused cmp or select. 342 ConditionCode ccode; 343 // IGET/IPUT lowering info index, points to MIRGraph::ifield_lowering_infos_. Due to limit on 344 // the number of code points (64K) and size of IGET/IPUT insn (2), this will never exceed 32K. 345 uint32_t ifield_lowering_info; 346 // SGET/SPUT lowering info index, points to MIRGraph::sfield_lowering_infos_. Due to limit on 347 // the number of code points (64K) and size of SGET/SPUT insn (2), this will never exceed 32K. 348 uint32_t sfield_lowering_info; 349 // INVOKE data index, points to MIRGraph::method_lowering_infos_. 350 uint32_t method_lowering_info; 351 } meta; 352 353 explicit MIR():offset(0), optimization_flags(0), m_unit_index(0), bb(NullBasicBlockId), 354 next(nullptr), ssa_rep(nullptr) { 355 memset(&meta, 0, sizeof(meta)); 356 } 357 358 uint32_t GetStartUseIndex() const { 359 return SSARepresentation::GetStartUseIndex(dalvikInsn.opcode); 360 } 361 362 MIR* Copy(CompilationUnit *c_unit); 363 MIR* Copy(MIRGraph* mir_Graph); 364 365 static void* operator new(size_t size, ArenaAllocator* arena) { 366 return arena->Alloc(sizeof(MIR), kArenaAllocMIR); 367 } 368 static void operator delete(void* p) {} // Nop. 369}; 370 371struct SuccessorBlockInfo; 372 373struct BasicBlock { 374 BasicBlockId id; 375 BasicBlockId dfs_id; 376 NarrowDexOffset start_offset; // Offset in code units. 377 BasicBlockId fall_through; 378 BasicBlockId taken; 379 BasicBlockId i_dom; // Immediate dominator. 380 uint16_t nesting_depth; 381 BBType block_type:4; 382 BlockListType successor_block_list_type:4; 383 bool visited:1; 384 bool hidden:1; 385 bool catch_entry:1; 386 bool explicit_throw:1; 387 bool conditional_branch:1; 388 bool terminated_by_return:1; // Block ends with a Dalvik return opcode. 389 bool dominates_return:1; // Is a member of return extended basic block. 390 bool use_lvn:1; // Run local value numbering on this block. 391 MIR* first_mir_insn; 392 MIR* last_mir_insn; 393 BasicBlockDataFlow* data_flow_info; 394 ArenaBitVector* dominators; 395 ArenaBitVector* i_dominated; // Set nodes being immediately dominated. 396 ArenaBitVector* dom_frontier; // Dominance frontier. 397 GrowableArray<BasicBlockId>* predecessors; 398 GrowableArray<SuccessorBlockInfo*>* successor_blocks; 399 400 void AppendMIR(MIR* mir); 401 void AppendMIRList(MIR* first_list_mir, MIR* last_list_mir); 402 void AppendMIRList(const std::vector<MIR*>& insns); 403 void PrependMIR(MIR* mir); 404 void PrependMIRList(MIR* first_list_mir, MIR* last_list_mir); 405 void PrependMIRList(const std::vector<MIR*>& to_add); 406 void InsertMIRAfter(MIR* current_mir, MIR* new_mir); 407 void InsertMIRListAfter(MIR* insert_after, MIR* first_list_mir, MIR* last_list_mir); 408 MIR* FindPreviousMIR(MIR* mir); 409 void InsertMIRBefore(MIR* insert_before, MIR* list); 410 void InsertMIRListBefore(MIR* insert_before, MIR* first_list_mir, MIR* last_list_mir); 411 bool RemoveMIR(MIR* mir); 412 bool RemoveMIRList(MIR* first_list_mir, MIR* last_list_mir); 413 414 BasicBlock* Copy(CompilationUnit* c_unit); 415 BasicBlock* Copy(MIRGraph* mir_graph); 416 417 /** 418 * @brief Reset the optimization_flags field of each MIR. 419 */ 420 void ResetOptimizationFlags(uint16_t reset_flags); 421 422 /** 423 * @brief Hide the BasicBlock. 424 * @details Set it to kDalvikByteCode, set hidden to true, remove all MIRs, 425 * remove itself from any predecessor edges, remove itself from any 426 * child's predecessor growable array. 427 */ 428 void Hide(CompilationUnit* c_unit); 429 430 /** 431 * @brief Is ssa_reg the last SSA definition of that VR in the block? 432 */ 433 bool IsSSALiveOut(const CompilationUnit* c_unit, int ssa_reg); 434 435 /** 436 * @brief Replace the edge going to old_bb to now go towards new_bb. 437 */ 438 bool ReplaceChild(BasicBlockId old_bb, BasicBlockId new_bb); 439 440 /** 441 * @brief Update the predecessor growable array from old_pred to new_pred. 442 */ 443 void UpdatePredecessor(BasicBlockId old_pred, BasicBlockId new_pred); 444 445 /** 446 * @brief Used to obtain the next MIR that follows unconditionally. 447 * @details The implementation does not guarantee that a MIR does not 448 * follow even if this method returns nullptr. 449 * @param mir_graph the MIRGraph. 450 * @param current The MIR for which to find an unconditional follower. 451 * @return Returns the following MIR if one can be found. 452 */ 453 MIR* GetNextUnconditionalMir(MIRGraph* mir_graph, MIR* current); 454 bool IsExceptionBlock() const; 455 456 static void* operator new(size_t size, ArenaAllocator* arena) { 457 return arena->Alloc(sizeof(BasicBlock), kArenaAllocBB); 458 } 459 static void operator delete(void* p) {} // Nop. 460}; 461 462/* 463 * The "blocks" field in "successor_block_list" points to an array of elements with the type 464 * "SuccessorBlockInfo". For catch blocks, key is type index for the exception. For switch 465 * blocks, key is the case value. 466 */ 467struct SuccessorBlockInfo { 468 BasicBlockId block; 469 int key; 470}; 471 472/** 473 * @class ChildBlockIterator 474 * @brief Enable an easy iteration of the children. 475 */ 476class ChildBlockIterator { 477 public: 478 /** 479 * @brief Constructs a child iterator. 480 * @param bb The basic whose children we need to iterate through. 481 * @param mir_graph The MIRGraph used to get the basic block during iteration. 482 */ 483 ChildBlockIterator(BasicBlock* bb, MIRGraph* mir_graph); 484 BasicBlock* Next(); 485 486 private: 487 BasicBlock* basic_block_; 488 MIRGraph* mir_graph_; 489 bool visited_fallthrough_; 490 bool visited_taken_; 491 bool have_successors_; 492 GrowableArray<SuccessorBlockInfo*>::Iterator successor_iter_; 493}; 494 495/* 496 * Collection of information describing an invoke, and the destination of 497 * the subsequent MOVE_RESULT (if applicable). Collected as a unit to enable 498 * more efficient invoke code generation. 499 */ 500struct CallInfo { 501 int num_arg_words; // Note: word count, not arg count. 502 RegLocation* args; // One for each word of arguments. 503 RegLocation result; // Eventual target of MOVE_RESULT. 504 int opt_flags; 505 InvokeType type; 506 uint32_t dex_idx; 507 uint32_t index; // Method idx for invokes, type idx for FilledNewArray. 508 uintptr_t direct_code; 509 uintptr_t direct_method; 510 RegLocation target; // Target of following move_result. 511 bool skip_this; 512 bool is_range; 513 DexOffset offset; // Offset in code units. 514 MIR* mir; 515}; 516 517 518const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, RegStorage(), INVALID_SREG, 519 INVALID_SREG}; 520 521class MIRGraph { 522 public: 523 MIRGraph(CompilationUnit* cu, ArenaAllocator* arena); 524 ~MIRGraph(); 525 526 /* 527 * Examine the graph to determine whether it's worthwile to spend the time compiling 528 * this method. 529 */ 530 bool SkipCompilation(std::string* skip_message); 531 532 /* 533 * Should we skip the compilation of this method based on its name? 534 */ 535 bool SkipCompilationByName(const std::string& methodname); 536 537 /* 538 * Parse dex method and add MIR at current insert point. Returns id (which is 539 * actually the index of the method in the m_units_ array). 540 */ 541 void InlineMethod(const DexFile::CodeItem* code_item, uint32_t access_flags, 542 InvokeType invoke_type, uint16_t class_def_idx, 543 uint32_t method_idx, jobject class_loader, const DexFile& dex_file); 544 545 /* Find existing block */ 546 BasicBlock* FindBlock(DexOffset code_offset) { 547 return FindBlock(code_offset, false, false, NULL); 548 } 549 550 const uint16_t* GetCurrentInsns() const { 551 return current_code_item_->insns_; 552 } 553 554 const uint16_t* GetInsns(int m_unit_index) const { 555 return m_units_[m_unit_index]->GetCodeItem()->insns_; 556 } 557 558 unsigned int GetNumBlocks() const { 559 return num_blocks_; 560 } 561 562 size_t GetNumDalvikInsns() const { 563 return cu_->code_item->insns_size_in_code_units_; 564 } 565 566 ArenaBitVector* GetTryBlockAddr() const { 567 return try_block_addr_; 568 } 569 570 BasicBlock* GetEntryBlock() const { 571 return entry_block_; 572 } 573 574 BasicBlock* GetExitBlock() const { 575 return exit_block_; 576 } 577 578 BasicBlock* GetBasicBlock(unsigned int block_id) const { 579 return (block_id == NullBasicBlockId) ? NULL : block_list_.Get(block_id); 580 } 581 582 size_t GetBasicBlockListCount() const { 583 return block_list_.Size(); 584 } 585 586 GrowableArray<BasicBlock*>* GetBlockList() { 587 return &block_list_; 588 } 589 590 GrowableArray<BasicBlockId>* GetDfsOrder() { 591 return dfs_order_; 592 } 593 594 GrowableArray<BasicBlockId>* GetDfsPostOrder() { 595 return dfs_post_order_; 596 } 597 598 GrowableArray<BasicBlockId>* GetDomPostOrder() { 599 return dom_post_order_traversal_; 600 } 601 602 int GetDefCount() const { 603 return def_count_; 604 } 605 606 ArenaAllocator* GetArena() { 607 return arena_; 608 } 609 610 void EnableOpcodeCounting() { 611 opcode_count_ = static_cast<int*>(arena_->Alloc(kNumPackedOpcodes * sizeof(int), 612 kArenaAllocMisc)); 613 } 614 615 void ShowOpcodeStats(); 616 617 DexCompilationUnit* GetCurrentDexCompilationUnit() const { 618 return m_units_[current_method_]; 619 } 620 621 /** 622 * @brief Dump a CFG into a dot file format. 623 * @param dir_prefix the directory the file will be created in. 624 * @param all_blocks does the dumper use all the basic blocks or use the reachable blocks. 625 * @param suffix does the filename require a suffix or not (default = nullptr). 626 */ 627 void DumpCFG(const char* dir_prefix, bool all_blocks, const char* suffix = nullptr); 628 629 bool HasFieldAccess() const { 630 return (merged_df_flags_ & (DF_IFIELD | DF_SFIELD)) != 0u; 631 } 632 633 bool HasStaticFieldAccess() const { 634 return (merged_df_flags_ & DF_SFIELD) != 0u; 635 } 636 637 bool HasInvokes() const { 638 // NOTE: These formats include the rare filled-new-array/range. 639 return (merged_df_flags_ & (DF_FORMAT_35C | DF_FORMAT_3RC)) != 0u; 640 } 641 642 void DoCacheFieldLoweringInfo(); 643 644 const MirIFieldLoweringInfo& GetIFieldLoweringInfo(MIR* mir) const { 645 DCHECK_LT(mir->meta.ifield_lowering_info, ifield_lowering_infos_.Size()); 646 return ifield_lowering_infos_.GetRawStorage()[mir->meta.ifield_lowering_info]; 647 } 648 649 const MirSFieldLoweringInfo& GetSFieldLoweringInfo(MIR* mir) const { 650 DCHECK_LT(mir->meta.sfield_lowering_info, sfield_lowering_infos_.Size()); 651 return sfield_lowering_infos_.GetRawStorage()[mir->meta.sfield_lowering_info]; 652 } 653 654 void DoCacheMethodLoweringInfo(); 655 656 const MirMethodLoweringInfo& GetMethodLoweringInfo(MIR* mir) { 657 DCHECK_LT(mir->meta.method_lowering_info, method_lowering_infos_.Size()); 658 return method_lowering_infos_.GetRawStorage()[mir->meta.method_lowering_info]; 659 } 660 661 void ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput); 662 663 void InitRegLocations(); 664 665 void RemapRegLocations(); 666 667 void DumpRegLocTable(RegLocation* table, int count); 668 669 void BasicBlockOptimization(); 670 671 GrowableArray<BasicBlockId>* GetTopologicalSortOrder() { 672 DCHECK(topological_order_ != nullptr); 673 return topological_order_; 674 } 675 676 bool IsConst(int32_t s_reg) const { 677 return is_constant_v_->IsBitSet(s_reg); 678 } 679 680 bool IsConst(RegLocation loc) const { 681 return loc.orig_sreg < 0 ? false : IsConst(loc.orig_sreg); 682 } 683 684 int32_t ConstantValue(RegLocation loc) const { 685 DCHECK(IsConst(loc)); 686 return constant_values_[loc.orig_sreg]; 687 } 688 689 int32_t ConstantValue(int32_t s_reg) const { 690 DCHECK(IsConst(s_reg)); 691 return constant_values_[s_reg]; 692 } 693 694 int64_t ConstantValueWide(RegLocation loc) const { 695 DCHECK(IsConst(loc)); 696 return (static_cast<int64_t>(constant_values_[loc.orig_sreg + 1]) << 32) | 697 Low32Bits(static_cast<int64_t>(constant_values_[loc.orig_sreg])); 698 } 699 700 bool IsConstantNullRef(RegLocation loc) const { 701 return loc.ref && loc.is_const && (ConstantValue(loc) == 0); 702 } 703 704 int GetNumSSARegs() const { 705 return num_ssa_regs_; 706 } 707 708 void SetNumSSARegs(int new_num) { 709 /* 710 * TODO: It's theoretically possible to exceed 32767, though any cases which did 711 * would be filtered out with current settings. When orig_sreg field is removed 712 * from RegLocation, expand s_reg_low to handle all possible cases and remove DCHECK(). 713 */ 714 DCHECK_EQ(new_num, static_cast<int16_t>(new_num)); 715 num_ssa_regs_ = new_num; 716 } 717 718 unsigned int GetNumReachableBlocks() const { 719 return num_reachable_blocks_; 720 } 721 722 int GetUseCount(int vreg) const { 723 return use_counts_.Get(vreg); 724 } 725 726 int GetRawUseCount(int vreg) const { 727 return raw_use_counts_.Get(vreg); 728 } 729 730 int GetSSASubscript(int ssa_reg) const { 731 return ssa_subscripts_->Get(ssa_reg); 732 } 733 734 RegLocation GetRawSrc(MIR* mir, int num) { 735 DCHECK(num < mir->ssa_rep->num_uses); 736 RegLocation res = reg_location_[mir->ssa_rep->uses[num]]; 737 return res; 738 } 739 740 RegLocation GetRawDest(MIR* mir) { 741 DCHECK_GT(mir->ssa_rep->num_defs, 0); 742 RegLocation res = reg_location_[mir->ssa_rep->defs[0]]; 743 return res; 744 } 745 746 RegLocation GetDest(MIR* mir) { 747 RegLocation res = GetRawDest(mir); 748 DCHECK(!res.wide); 749 return res; 750 } 751 752 RegLocation GetSrc(MIR* mir, int num) { 753 RegLocation res = GetRawSrc(mir, num); 754 DCHECK(!res.wide); 755 return res; 756 } 757 758 RegLocation GetDestWide(MIR* mir) { 759 RegLocation res = GetRawDest(mir); 760 DCHECK(res.wide); 761 return res; 762 } 763 764 RegLocation GetSrcWide(MIR* mir, int low) { 765 RegLocation res = GetRawSrc(mir, low); 766 DCHECK(res.wide); 767 return res; 768 } 769 770 RegLocation GetBadLoc() { 771 return bad_loc; 772 } 773 774 int GetMethodSReg() const { 775 return method_sreg_; 776 } 777 778 /** 779 * @brief Used to obtain the number of compiler temporaries being used. 780 * @return Returns the number of compiler temporaries. 781 */ 782 size_t GetNumUsedCompilerTemps() const { 783 size_t total_num_temps = compiler_temps_.Size(); 784 DCHECK_LE(num_non_special_compiler_temps_, total_num_temps); 785 return total_num_temps; 786 } 787 788 /** 789 * @brief Used to obtain the number of non-special compiler temporaries being used. 790 * @return Returns the number of non-special compiler temporaries. 791 */ 792 size_t GetNumNonSpecialCompilerTemps() const { 793 return num_non_special_compiler_temps_; 794 } 795 796 /** 797 * @brief Used to set the total number of available non-special compiler temporaries. 798 * @details Can fail setting the new max if there are more temps being used than the new_max. 799 * @param new_max The new maximum number of non-special compiler temporaries. 800 * @return Returns true if the max was set and false if failed to set. 801 */ 802 bool SetMaxAvailableNonSpecialCompilerTemps(size_t new_max) { 803 if (new_max < GetNumNonSpecialCompilerTemps()) { 804 return false; 805 } else { 806 max_available_non_special_compiler_temps_ = new_max; 807 return true; 808 } 809 } 810 811 /** 812 * @brief Provides the number of non-special compiler temps available. 813 * @details Even if this returns zero, special compiler temps are guaranteed to be available. 814 * @return Returns the number of available temps. 815 */ 816 size_t GetNumAvailableNonSpecialCompilerTemps(); 817 818 /** 819 * @brief Used to obtain an existing compiler temporary. 820 * @param index The index of the temporary which must be strictly less than the 821 * number of temporaries. 822 * @return Returns the temporary that was asked for. 823 */ 824 CompilerTemp* GetCompilerTemp(size_t index) const { 825 return compiler_temps_.Get(index); 826 } 827 828 /** 829 * @brief Used to obtain the maximum number of compiler temporaries that can be requested. 830 * @return Returns the maximum number of compiler temporaries, whether used or not. 831 */ 832 size_t GetMaxPossibleCompilerTemps() const { 833 return max_available_special_compiler_temps_ + max_available_non_special_compiler_temps_; 834 } 835 836 /** 837 * @brief Used to obtain a new unique compiler temporary. 838 * @param ct_type Type of compiler temporary requested. 839 * @param wide Whether we should allocate a wide temporary. 840 * @return Returns the newly created compiler temporary. 841 */ 842 CompilerTemp* GetNewCompilerTemp(CompilerTempType ct_type, bool wide); 843 844 bool MethodIsLeaf() { 845 return attributes_ & METHOD_IS_LEAF; 846 } 847 848 RegLocation GetRegLocation(int index) { 849 DCHECK((index >= 0) && (index < num_ssa_regs_)); 850 return reg_location_[index]; 851 } 852 853 RegLocation GetMethodLoc() { 854 return reg_location_[method_sreg_]; 855 } 856 857 bool IsBackedge(BasicBlock* branch_bb, BasicBlockId target_bb_id) { 858 return ((target_bb_id != NullBasicBlockId) && 859 (GetBasicBlock(target_bb_id)->start_offset <= branch_bb->start_offset)); 860 } 861 862 bool IsBackwardsBranch(BasicBlock* branch_bb) { 863 return IsBackedge(branch_bb, branch_bb->taken) || IsBackedge(branch_bb, branch_bb->fall_through); 864 } 865 866 void CountBranch(DexOffset target_offset) { 867 if (target_offset <= current_offset_) { 868 backward_branches_++; 869 } else { 870 forward_branches_++; 871 } 872 } 873 874 int GetBranchCount() { 875 return backward_branches_ + forward_branches_; 876 } 877 878 static bool IsPseudoMirOp(Instruction::Code opcode) { 879 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); 880 } 881 882 static bool IsPseudoMirOp(int opcode) { 883 return opcode >= static_cast<int>(kMirOpFirst); 884 } 885 886 // Is this vreg in the in set? 887 bool IsInVReg(int vreg) { 888 return (vreg >= cu_->num_regs); 889 } 890 891 void DumpCheckStats(); 892 MIR* FindMoveResult(BasicBlock* bb, MIR* mir); 893 int SRegToVReg(int ssa_reg) const; 894 void VerifyDataflow(); 895 void CheckForDominanceFrontier(BasicBlock* dom_bb, const BasicBlock* succ_bb); 896 void EliminateNullChecksAndInferTypesStart(); 897 bool EliminateNullChecksAndInferTypes(BasicBlock* bb); 898 void EliminateNullChecksAndInferTypesEnd(); 899 bool EliminateClassInitChecksGate(); 900 bool EliminateClassInitChecks(BasicBlock* bb); 901 void EliminateClassInitChecksEnd(); 902 /* 903 * Type inference handling helpers. Because Dalvik's bytecode is not fully typed, 904 * we have to do some work to figure out the sreg type. For some operations it is 905 * clear based on the opcode (i.e. ADD_FLOAT v0, v1, v2), but for others (MOVE), we 906 * may never know the "real" type. 907 * 908 * We perform the type inference operation by using an iterative walk over 909 * the graph, propagating types "defined" by typed opcodes to uses and defs in 910 * non-typed opcodes (such as MOVE). The Setxx(index) helpers are used to set defined 911 * types on typed opcodes (such as ADD_INT). The Setxx(index, is_xx) form is used to 912 * propagate types through non-typed opcodes such as PHI and MOVE. The is_xx flag 913 * tells whether our guess of the type is based on a previously typed definition. 914 * If so, the defined type takes precedence. Note that it's possible to have the same sreg 915 * show multiple defined types because dx treats constants as untyped bit patterns. 916 * The return value of the Setxx() helpers says whether or not the Setxx() action changed 917 * the current guess, and is used to know when to terminate the iterative walk. 918 */ 919 bool SetFp(int index, bool is_fp); 920 bool SetFp(int index); 921 bool SetCore(int index, bool is_core); 922 bool SetCore(int index); 923 bool SetRef(int index, bool is_ref); 924 bool SetRef(int index); 925 bool SetWide(int index, bool is_wide); 926 bool SetWide(int index); 927 bool SetHigh(int index, bool is_high); 928 bool SetHigh(int index); 929 930 bool PuntToInterpreter() { 931 return punt_to_interpreter_; 932 } 933 934 void SetPuntToInterpreter(bool val) { 935 punt_to_interpreter_ = val; 936 } 937 938 char* GetDalvikDisassembly(const MIR* mir); 939 void ReplaceSpecialChars(std::string& str); 940 std::string GetSSAName(int ssa_reg); 941 std::string GetSSANameWithConst(int ssa_reg, bool singles_only); 942 void GetBlockName(BasicBlock* bb, char* name); 943 const char* GetShortyFromTargetIdx(int); 944 void DumpMIRGraph(); 945 CallInfo* NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range); 946 BasicBlock* NewMemBB(BBType block_type, int block_id); 947 MIR* NewMIR(); 948 MIR* AdvanceMIR(BasicBlock** p_bb, MIR* mir); 949 BasicBlock* NextDominatedBlock(BasicBlock* bb); 950 bool LayoutBlocks(BasicBlock* bb); 951 void ComputeTopologicalSortOrder(); 952 BasicBlock* CreateNewBB(BBType block_type); 953 954 bool InlineCallsGate(); 955 void InlineCallsStart(); 956 void InlineCalls(BasicBlock* bb); 957 void InlineCallsEnd(); 958 959 /** 960 * @brief Perform the initial preparation for the Method Uses. 961 */ 962 void InitializeMethodUses(); 963 964 /** 965 * @brief Perform the initial preparation for the Constant Propagation. 966 */ 967 void InitializeConstantPropagation(); 968 969 /** 970 * @brief Perform the initial preparation for the SSA Transformation. 971 */ 972 void SSATransformationStart(); 973 974 /** 975 * @brief Insert a the operands for the Phi nodes. 976 * @param bb the considered BasicBlock. 977 * @return true 978 */ 979 bool InsertPhiNodeOperands(BasicBlock* bb); 980 981 /** 982 * @brief Perform the cleanup after the SSA Transformation. 983 */ 984 void SSATransformationEnd(); 985 986 /** 987 * @brief Perform constant propagation on a BasicBlock. 988 * @param bb the considered BasicBlock. 989 */ 990 void DoConstantPropagation(BasicBlock* bb); 991 992 /** 993 * @brief Count the uses in the BasicBlock 994 * @param bb the BasicBlock 995 */ 996 void CountUses(struct BasicBlock* bb); 997 998 static uint64_t GetDataFlowAttributes(Instruction::Code opcode); 999 static uint64_t GetDataFlowAttributes(MIR* mir); 1000 1001 /** 1002 * @brief Combine BasicBlocks 1003 * @param the BasicBlock we are considering 1004 */ 1005 void CombineBlocks(BasicBlock* bb); 1006 1007 void ClearAllVisitedFlags(); 1008 1009 void AllocateSSAUseData(MIR *mir, int num_uses); 1010 void AllocateSSADefData(MIR *mir, int num_defs); 1011 void CalculateBasicBlockInformation(); 1012 void InitializeBasicBlockData(); 1013 void ComputeDFSOrders(); 1014 void ComputeDefBlockMatrix(); 1015 void ComputeDominators(); 1016 void CompilerInitializeSSAConversion(); 1017 void InsertPhiNodes(); 1018 void DoDFSPreOrderSSARename(BasicBlock* block); 1019 1020 /* 1021 * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on 1022 * we can verify that all catch entries have native PC entries. 1023 */ 1024 std::set<uint32_t> catches_; 1025 1026 // TODO: make these private. 1027 RegLocation* reg_location_; // Map SSA names to location. 1028 SafeMap<unsigned int, unsigned int> block_id_map_; // Block collapse lookup cache. 1029 1030 static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst]; 1031 static const uint32_t analysis_attributes_[kMirOpLast]; 1032 1033 void HandleSSADef(int* defs, int dalvik_reg, int reg_index); 1034 bool InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed); 1035 1036 // Used for removing redudant suspend tests 1037 void AppendGenSuspendTestList(BasicBlock* bb) { 1038 if (gen_suspend_test_list_.Size() == 0 || 1039 gen_suspend_test_list_.Get(gen_suspend_test_list_.Size() - 1) != bb) { 1040 gen_suspend_test_list_.Insert(bb); 1041 } 1042 } 1043 1044 /* This is used to check if there is already a method call dominating the 1045 * source basic block of a backedge and being dominated by the target basic 1046 * block of the backedge. 1047 */ 1048 bool HasSuspendTestBetween(BasicBlock* source, BasicBlockId target_id); 1049 1050 protected: 1051 int FindCommonParent(int block1, int block2); 1052 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, 1053 const ArenaBitVector* src2); 1054 void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v, 1055 ArenaBitVector* live_in_v, int dalvik_reg_id); 1056 void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id); 1057 bool DoSSAConversion(BasicBlock* bb); 1058 bool InvokeUsesMethodStar(MIR* mir); 1059 int ParseInsn(const uint16_t* code_ptr, MIR::DecodedInstruction* decoded_instruction); 1060 bool ContentIsInsn(const uint16_t* code_ptr); 1061 BasicBlock* SplitBlock(DexOffset code_offset, BasicBlock* orig_block, 1062 BasicBlock** immed_pred_block_p); 1063 BasicBlock* FindBlock(DexOffset code_offset, bool split, bool create, 1064 BasicBlock** immed_pred_block_p); 1065 void ProcessTryCatchBlocks(); 1066 bool IsBadMonitorExitCatch(NarrowDexOffset monitor_exit_offset, NarrowDexOffset catch_offset); 1067 BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1068 int flags, const uint16_t* code_ptr, const uint16_t* code_end); 1069 BasicBlock* ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1070 int flags); 1071 BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, DexOffset cur_offset, int width, 1072 int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr, 1073 const uint16_t* code_end); 1074 int AddNewSReg(int v_reg); 1075 void HandleSSAUse(int* uses, int dalvik_reg, int reg_index); 1076 void DataFlowSSAFormat35C(MIR* mir); 1077 void DataFlowSSAFormat3RC(MIR* mir); 1078 bool FindLocalLiveIn(BasicBlock* bb); 1079 bool VerifyPredInfo(BasicBlock* bb); 1080 BasicBlock* NeedsVisit(BasicBlock* bb); 1081 BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb); 1082 void MarkPreOrder(BasicBlock* bb); 1083 void RecordDFSOrders(BasicBlock* bb); 1084 void ComputeDomPostOrderTraversal(BasicBlock* bb); 1085 void SetConstant(int32_t ssa_reg, int value); 1086 void SetConstantWide(int ssa_reg, int64_t value); 1087 int GetSSAUseCount(int s_reg); 1088 bool BasicBlockOpt(BasicBlock* bb); 1089 bool BuildExtendedBBList(struct BasicBlock* bb); 1090 bool FillDefBlockMatrix(BasicBlock* bb); 1091 void InitializeDominationInfo(BasicBlock* bb); 1092 bool ComputeblockIDom(BasicBlock* bb); 1093 bool ComputeBlockDominators(BasicBlock* bb); 1094 bool SetDominators(BasicBlock* bb); 1095 bool ComputeBlockLiveIns(BasicBlock* bb); 1096 bool ComputeDominanceFrontier(BasicBlock* bb); 1097 1098 void CountChecks(BasicBlock* bb); 1099 void AnalyzeBlock(BasicBlock* bb, struct MethodStats* stats); 1100 bool ComputeSkipCompilation(struct MethodStats* stats, bool skip_default, 1101 std::string* skip_message); 1102 1103 CompilationUnit* const cu_; 1104 GrowableArray<int>* ssa_base_vregs_; 1105 GrowableArray<int>* ssa_subscripts_; 1106 // Map original Dalvik virtual reg i to the current SSA name. 1107 int* vreg_to_ssa_map_; // length == method->registers_size 1108 int* ssa_last_defs_; // length == method->registers_size 1109 ArenaBitVector* is_constant_v_; // length == num_ssa_reg 1110 int* constant_values_; // length == num_ssa_reg 1111 // Use counts of ssa names. 1112 GrowableArray<uint32_t> use_counts_; // Weighted by nesting depth 1113 GrowableArray<uint32_t> raw_use_counts_; // Not weighted 1114 unsigned int num_reachable_blocks_; 1115 unsigned int max_num_reachable_blocks_; 1116 GrowableArray<BasicBlockId>* dfs_order_; 1117 GrowableArray<BasicBlockId>* dfs_post_order_; 1118 GrowableArray<BasicBlockId>* dom_post_order_traversal_; 1119 GrowableArray<BasicBlockId>* topological_order_; 1120 int* i_dom_list_; 1121 ArenaBitVector** def_block_matrix_; // num_dalvik_register x num_blocks. 1122 std::unique_ptr<ScopedArenaAllocator> temp_scoped_alloc_; 1123 uint16_t* temp_insn_data_; 1124 uint32_t temp_bit_vector_size_; 1125 ArenaBitVector* temp_bit_vector_; 1126 static const int kInvalidEntry = -1; 1127 GrowableArray<BasicBlock*> block_list_; 1128 ArenaBitVector* try_block_addr_; 1129 BasicBlock* entry_block_; 1130 BasicBlock* exit_block_; 1131 unsigned int num_blocks_; 1132 const DexFile::CodeItem* current_code_item_; 1133 GrowableArray<uint16_t> dex_pc_to_block_map_; // FindBlock lookup cache. 1134 std::vector<DexCompilationUnit*> m_units_; // List of methods included in this graph 1135 typedef std::pair<int, int> MIRLocation; // Insert point, (m_unit_ index, offset) 1136 std::vector<MIRLocation> method_stack_; // Include stack 1137 int current_method_; 1138 DexOffset current_offset_; // Offset in code units 1139 int def_count_; // Used to estimate size of ssa name storage. 1140 int* opcode_count_; // Dex opcode coverage stats. 1141 int num_ssa_regs_; // Number of names following SSA transformation. 1142 std::vector<BasicBlockId> extended_basic_blocks_; // Heads of block "traces". 1143 int method_sreg_; 1144 unsigned int attributes_; 1145 Checkstats* checkstats_; 1146 ArenaAllocator* arena_; 1147 int backward_branches_; 1148 int forward_branches_; 1149 GrowableArray<CompilerTemp*> compiler_temps_; 1150 size_t num_non_special_compiler_temps_; 1151 size_t max_available_non_special_compiler_temps_; 1152 size_t max_available_special_compiler_temps_; 1153 bool punt_to_interpreter_; // Difficult or not worthwhile - just interpret. 1154 uint64_t merged_df_flags_; 1155 GrowableArray<MirIFieldLoweringInfo> ifield_lowering_infos_; 1156 GrowableArray<MirSFieldLoweringInfo> sfield_lowering_infos_; 1157 GrowableArray<MirMethodLoweringInfo> method_lowering_infos_; 1158 static const uint64_t oat_data_flow_attributes_[kMirOpLast]; 1159 GrowableArray<BasicBlock*> gen_suspend_test_list_; // List of blocks containing suspend tests 1160 1161 friend class ClassInitCheckEliminationTest; 1162 friend class LocalValueNumberingTest; 1163}; 1164 1165} // namespace art 1166 1167#endif // ART_COMPILER_DEX_MIR_GRAPH_H_ 1168