mir_optimization.cc revision 69f08baaa4b70ce32a258f3da43cf12f2a034696
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "compiler_internals.h" 18#include "local_value_numbering.h" 19#include "dataflow_iterator-inl.h" 20#include "dex/quick/dex_file_method_inliner.h" 21#include "dex/quick/dex_file_to_method_inliner_map.h" 22#include "utils/scoped_arena_containers.h" 23 24namespace art { 25 26static unsigned int Predecessors(BasicBlock* bb) { 27 return bb->predecessors->Size(); 28} 29 30/* Setup a constant value for opcodes thare have the DF_SETS_CONST attribute */ 31void MIRGraph::SetConstant(int32_t ssa_reg, int value) { 32 is_constant_v_->SetBit(ssa_reg); 33 constant_values_[ssa_reg] = value; 34} 35 36void MIRGraph::SetConstantWide(int ssa_reg, int64_t value) { 37 is_constant_v_->SetBit(ssa_reg); 38 constant_values_[ssa_reg] = Low32Bits(value); 39 constant_values_[ssa_reg + 1] = High32Bits(value); 40} 41 42void MIRGraph::DoConstantPropagation(BasicBlock* bb) { 43 MIR* mir; 44 45 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 46 // Skip pass if BB has MIR without SSA representation. 47 if (mir->ssa_rep == nullptr) { 48 return; 49 } 50 51 uint64_t df_attributes = GetDataFlowAttributes(mir); 52 53 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn; 54 55 if (!(df_attributes & DF_HAS_DEFS)) continue; 56 57 /* Handle instructions that set up constants directly */ 58 if (df_attributes & DF_SETS_CONST) { 59 if (df_attributes & DF_DA) { 60 int32_t vB = static_cast<int32_t>(d_insn->vB); 61 switch (d_insn->opcode) { 62 case Instruction::CONST_4: 63 case Instruction::CONST_16: 64 case Instruction::CONST: 65 SetConstant(mir->ssa_rep->defs[0], vB); 66 break; 67 case Instruction::CONST_HIGH16: 68 SetConstant(mir->ssa_rep->defs[0], vB << 16); 69 break; 70 case Instruction::CONST_WIDE_16: 71 case Instruction::CONST_WIDE_32: 72 SetConstantWide(mir->ssa_rep->defs[0], static_cast<int64_t>(vB)); 73 break; 74 case Instruction::CONST_WIDE: 75 SetConstantWide(mir->ssa_rep->defs[0], d_insn->vB_wide); 76 break; 77 case Instruction::CONST_WIDE_HIGH16: 78 SetConstantWide(mir->ssa_rep->defs[0], static_cast<int64_t>(vB) << 48); 79 break; 80 default: 81 break; 82 } 83 } 84 /* Handle instructions that set up constants directly */ 85 } else if (df_attributes & DF_IS_MOVE) { 86 int i; 87 88 for (i = 0; i < mir->ssa_rep->num_uses; i++) { 89 if (!is_constant_v_->IsBitSet(mir->ssa_rep->uses[i])) break; 90 } 91 /* Move a register holding a constant to another register */ 92 if (i == mir->ssa_rep->num_uses) { 93 SetConstant(mir->ssa_rep->defs[0], constant_values_[mir->ssa_rep->uses[0]]); 94 if (df_attributes & DF_A_WIDE) { 95 SetConstant(mir->ssa_rep->defs[1], constant_values_[mir->ssa_rep->uses[1]]); 96 } 97 } 98 } 99 } 100 /* TODO: implement code to handle arithmetic operations */ 101} 102 103/* Advance to next strictly dominated MIR node in an extended basic block */ 104MIR* MIRGraph::AdvanceMIR(BasicBlock** p_bb, MIR* mir) { 105 BasicBlock* bb = *p_bb; 106 if (mir != NULL) { 107 mir = mir->next; 108 if (mir == NULL) { 109 bb = GetBasicBlock(bb->fall_through); 110 if ((bb == NULL) || Predecessors(bb) != 1) { 111 mir = NULL; 112 } else { 113 *p_bb = bb; 114 mir = bb->first_mir_insn; 115 } 116 } 117 } 118 return mir; 119} 120 121/* 122 * To be used at an invoke mir. If the logically next mir node represents 123 * a move-result, return it. Else, return NULL. If a move-result exists, 124 * it is required to immediately follow the invoke with no intervening 125 * opcodes or incoming arcs. However, if the result of the invoke is not 126 * used, a move-result may not be present. 127 */ 128MIR* MIRGraph::FindMoveResult(BasicBlock* bb, MIR* mir) { 129 BasicBlock* tbb = bb; 130 mir = AdvanceMIR(&tbb, mir); 131 while (mir != NULL) { 132 int opcode = mir->dalvikInsn.opcode; 133 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || 134 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || 135 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { 136 break; 137 } 138 // Keep going if pseudo op, otherwise terminate 139 if (opcode < kNumPackedOpcodes) { 140 mir = NULL; 141 } else { 142 mir = AdvanceMIR(&tbb, mir); 143 } 144 } 145 return mir; 146} 147 148BasicBlock* MIRGraph::NextDominatedBlock(BasicBlock* bb) { 149 if (bb->block_type == kDead) { 150 return NULL; 151 } 152 DCHECK((bb->block_type == kEntryBlock) || (bb->block_type == kDalvikByteCode) 153 || (bb->block_type == kExitBlock)); 154 BasicBlock* bb_taken = GetBasicBlock(bb->taken); 155 BasicBlock* bb_fall_through = GetBasicBlock(bb->fall_through); 156 if (((bb_fall_through == NULL) && (bb_taken != NULL)) && 157 ((bb_taken->block_type == kDalvikByteCode) || (bb_taken->block_type == kExitBlock))) { 158 // Follow simple unconditional branches. 159 bb = bb_taken; 160 } else { 161 // Follow simple fallthrough 162 bb = (bb_taken != NULL) ? NULL : bb_fall_through; 163 } 164 if (bb == NULL || (Predecessors(bb) != 1)) { 165 return NULL; 166 } 167 DCHECK((bb->block_type == kDalvikByteCode) || (bb->block_type == kExitBlock)); 168 return bb; 169} 170 171static MIR* FindPhi(BasicBlock* bb, int ssa_name) { 172 for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 173 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { 174 for (int i = 0; i < mir->ssa_rep->num_uses; i++) { 175 if (mir->ssa_rep->uses[i] == ssa_name) { 176 return mir; 177 } 178 } 179 } 180 } 181 return NULL; 182} 183 184static SelectInstructionKind SelectKind(MIR* mir) { 185 switch (mir->dalvikInsn.opcode) { 186 case Instruction::MOVE: 187 case Instruction::MOVE_OBJECT: 188 case Instruction::MOVE_16: 189 case Instruction::MOVE_OBJECT_16: 190 case Instruction::MOVE_FROM16: 191 case Instruction::MOVE_OBJECT_FROM16: 192 return kSelectMove; 193 case Instruction::CONST: 194 case Instruction::CONST_4: 195 case Instruction::CONST_16: 196 return kSelectConst; 197 case Instruction::GOTO: 198 case Instruction::GOTO_16: 199 case Instruction::GOTO_32: 200 return kSelectGoto; 201 default: 202 return kSelectNone; 203 } 204} 205 206static constexpr ConditionCode kIfCcZConditionCodes[] = { 207 kCondEq, kCondNe, kCondLt, kCondGe, kCondGt, kCondLe 208}; 209 210COMPILE_ASSERT(arraysize(kIfCcZConditionCodes) == Instruction::IF_LEZ - Instruction::IF_EQZ + 1, 211 if_ccz_ccodes_size1); 212 213static constexpr bool IsInstructionIfCcZ(Instruction::Code opcode) { 214 return Instruction::IF_EQZ <= opcode && opcode <= Instruction::IF_LEZ; 215} 216 217static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { 218 return kIfCcZConditionCodes[opcode - Instruction::IF_EQZ]; 219} 220 221COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_EQZ) == kCondEq, check_if_eqz_ccode); 222COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_NEZ) == kCondNe, check_if_nez_ccode); 223COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_LTZ) == kCondLt, check_if_ltz_ccode); 224COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_GEZ) == kCondGe, check_if_gez_ccode); 225COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_GTZ) == kCondGt, check_if_gtz_ccode); 226COMPILE_ASSERT(ConditionCodeForIfCcZ(Instruction::IF_LEZ) == kCondLe, check_if_lez_ccode); 227 228int MIRGraph::GetSSAUseCount(int s_reg) { 229 return raw_use_counts_.Get(s_reg); 230} 231 232size_t MIRGraph::GetNumAvailableNonSpecialCompilerTemps() { 233 if (num_non_special_compiler_temps_ >= max_available_non_special_compiler_temps_) { 234 return 0; 235 } else { 236 return max_available_non_special_compiler_temps_ - num_non_special_compiler_temps_; 237 } 238} 239 240 241// FIXME - will probably need to revisit all uses of this, as type not defined. 242static const RegLocation temp_loc = {kLocCompilerTemp, 243 0, 1 /*defined*/, 0, 0, 0, 0, 0, 1 /*home*/, 244 RegStorage(), INVALID_SREG, INVALID_SREG}; 245 246CompilerTemp* MIRGraph::GetNewCompilerTemp(CompilerTempType ct_type, bool wide) { 247 // There is a limit to the number of non-special temps so check to make sure it wasn't exceeded. 248 if (ct_type == kCompilerTempVR) { 249 size_t available_temps = GetNumAvailableNonSpecialCompilerTemps(); 250 if (available_temps <= 0 || (available_temps <= 1 && wide)) { 251 return 0; 252 } 253 } 254 255 CompilerTemp *compiler_temp = static_cast<CompilerTemp *>(arena_->Alloc(sizeof(CompilerTemp), 256 kArenaAllocRegAlloc)); 257 258 // Create the type of temp requested. Special temps need special handling because 259 // they have a specific virtual register assignment. 260 if (ct_type == kCompilerTempSpecialMethodPtr) { 261 DCHECK_EQ(wide, false); 262 compiler_temp->v_reg = static_cast<int>(kVRegMethodPtrBaseReg); 263 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); 264 265 // The MIR graph keeps track of the sreg for method pointer specially, so record that now. 266 method_sreg_ = compiler_temp->s_reg_low; 267 } else { 268 DCHECK_EQ(ct_type, kCompilerTempVR); 269 270 // The new non-special compiler temp must receive a unique v_reg with a negative value. 271 compiler_temp->v_reg = static_cast<int>(kVRegNonSpecialTempBaseReg) - num_non_special_compiler_temps_; 272 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); 273 num_non_special_compiler_temps_++; 274 275 if (wide) { 276 // Ensure that the two registers are consecutive. Since the virtual registers used for temps grow in a 277 // negative fashion, we need the smaller to refer to the low part. Thus, we redefine the v_reg and s_reg_low. 278 compiler_temp->v_reg--; 279 int ssa_reg_high = compiler_temp->s_reg_low; 280 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); 281 int ssa_reg_low = compiler_temp->s_reg_low; 282 283 // If needed initialize the register location for the high part. 284 // The low part is handled later in this method on a common path. 285 if (reg_location_ != nullptr) { 286 reg_location_[ssa_reg_high] = temp_loc; 287 reg_location_[ssa_reg_high].high_word = 1; 288 reg_location_[ssa_reg_high].s_reg_low = ssa_reg_low; 289 reg_location_[ssa_reg_high].wide = true; 290 } 291 292 num_non_special_compiler_temps_++; 293 } 294 } 295 296 // Have we already allocated the register locations? 297 if (reg_location_ != nullptr) { 298 int ssa_reg_low = compiler_temp->s_reg_low; 299 reg_location_[ssa_reg_low] = temp_loc; 300 reg_location_[ssa_reg_low].s_reg_low = ssa_reg_low; 301 reg_location_[ssa_reg_low].wide = wide; 302 } 303 304 compiler_temps_.Insert(compiler_temp); 305 return compiler_temp; 306} 307 308/* Do some MIR-level extended basic block optimizations */ 309bool MIRGraph::BasicBlockOpt(BasicBlock* bb) { 310 if (bb->block_type == kDead) { 311 return true; 312 } 313 bool use_lvn = bb->use_lvn; 314 UniquePtr<LocalValueNumbering> local_valnum; 315 if (use_lvn) { 316 local_valnum.reset(LocalValueNumbering::Create(cu_)); 317 } 318 while (bb != NULL) { 319 for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 320 // TUNING: use the returned value number for CSE. 321 if (use_lvn) { 322 local_valnum->GetValueNumber(mir); 323 } 324 // Look for interesting opcodes, skip otherwise 325 Instruction::Code opcode = mir->dalvikInsn.opcode; 326 switch (opcode) { 327 case Instruction::CMPL_FLOAT: 328 case Instruction::CMPL_DOUBLE: 329 case Instruction::CMPG_FLOAT: 330 case Instruction::CMPG_DOUBLE: 331 case Instruction::CMP_LONG: 332 if ((cu_->disable_opt & (1 << kBranchFusing)) != 0) { 333 // Bitcode doesn't allow this optimization. 334 break; 335 } 336 if (mir->next != NULL) { 337 MIR* mir_next = mir->next; 338 // Make sure result of cmp is used by next insn and nowhere else 339 if (IsInstructionIfCcZ(mir->next->dalvikInsn.opcode) && 340 (mir->ssa_rep->defs[0] == mir_next->ssa_rep->uses[0]) && 341 (GetSSAUseCount(mir->ssa_rep->defs[0]) == 1)) { 342 mir_next->meta.ccode = ConditionCodeForIfCcZ(mir_next->dalvikInsn.opcode); 343 switch (opcode) { 344 case Instruction::CMPL_FLOAT: 345 mir_next->dalvikInsn.opcode = 346 static_cast<Instruction::Code>(kMirOpFusedCmplFloat); 347 break; 348 case Instruction::CMPL_DOUBLE: 349 mir_next->dalvikInsn.opcode = 350 static_cast<Instruction::Code>(kMirOpFusedCmplDouble); 351 break; 352 case Instruction::CMPG_FLOAT: 353 mir_next->dalvikInsn.opcode = 354 static_cast<Instruction::Code>(kMirOpFusedCmpgFloat); 355 break; 356 case Instruction::CMPG_DOUBLE: 357 mir_next->dalvikInsn.opcode = 358 static_cast<Instruction::Code>(kMirOpFusedCmpgDouble); 359 break; 360 case Instruction::CMP_LONG: 361 mir_next->dalvikInsn.opcode = 362 static_cast<Instruction::Code>(kMirOpFusedCmpLong); 363 break; 364 default: LOG(ERROR) << "Unexpected opcode: " << opcode; 365 } 366 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop); 367 mir_next->ssa_rep->num_uses = mir->ssa_rep->num_uses; 368 mir_next->ssa_rep->uses = mir->ssa_rep->uses; 369 mir_next->ssa_rep->fp_use = mir->ssa_rep->fp_use; 370 mir_next->ssa_rep->num_defs = 0; 371 mir->ssa_rep->num_uses = 0; 372 mir->ssa_rep->num_defs = 0; 373 } 374 } 375 break; 376 case Instruction::GOTO: 377 case Instruction::GOTO_16: 378 case Instruction::GOTO_32: 379 case Instruction::IF_EQ: 380 case Instruction::IF_NE: 381 case Instruction::IF_LT: 382 case Instruction::IF_GE: 383 case Instruction::IF_GT: 384 case Instruction::IF_LE: 385 case Instruction::IF_EQZ: 386 case Instruction::IF_NEZ: 387 case Instruction::IF_LTZ: 388 case Instruction::IF_GEZ: 389 case Instruction::IF_GTZ: 390 case Instruction::IF_LEZ: 391 // If we've got a backwards branch to return, no need to suspend check. 392 if ((IsBackedge(bb, bb->taken) && GetBasicBlock(bb->taken)->dominates_return) || 393 (IsBackedge(bb, bb->fall_through) && 394 GetBasicBlock(bb->fall_through)->dominates_return)) { 395 mir->optimization_flags |= MIR_IGNORE_SUSPEND_CHECK; 396 if (cu_->verbose) { 397 LOG(INFO) << "Suppressed suspend check on branch to return at 0x" << std::hex 398 << mir->offset; 399 } 400 } 401 break; 402 default: 403 break; 404 } 405 // Is this the select pattern? 406 // TODO: flesh out support for Mips. NOTE: llvm's select op doesn't quite work here. 407 // TUNING: expand to support IF_xx compare & branches 408 if (!cu_->compiler->IsPortable() && 409 (cu_->instruction_set == kThumb2 || cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) && 410 IsInstructionIfCcZ(mir->dalvikInsn.opcode)) { 411 BasicBlock* ft = GetBasicBlock(bb->fall_through); 412 DCHECK(ft != NULL); 413 BasicBlock* ft_ft = GetBasicBlock(ft->fall_through); 414 BasicBlock* ft_tk = GetBasicBlock(ft->taken); 415 416 BasicBlock* tk = GetBasicBlock(bb->taken); 417 DCHECK(tk != NULL); 418 BasicBlock* tk_ft = GetBasicBlock(tk->fall_through); 419 BasicBlock* tk_tk = GetBasicBlock(tk->taken); 420 421 /* 422 * In the select pattern, the taken edge goes to a block that unconditionally 423 * transfers to the rejoin block and the fall_though edge goes to a block that 424 * unconditionally falls through to the rejoin block. 425 */ 426 if ((tk_ft == NULL) && (ft_tk == NULL) && (tk_tk == ft_ft) && 427 (Predecessors(tk) == 1) && (Predecessors(ft) == 1)) { 428 /* 429 * Okay - we have the basic diamond shape. At the very least, we can eliminate the 430 * suspend check on the taken-taken branch back to the join point. 431 */ 432 if (SelectKind(tk->last_mir_insn) == kSelectGoto) { 433 tk->last_mir_insn->optimization_flags |= (MIR_IGNORE_SUSPEND_CHECK); 434 } 435 // Are the block bodies something we can handle? 436 if ((ft->first_mir_insn == ft->last_mir_insn) && 437 (tk->first_mir_insn != tk->last_mir_insn) && 438 (tk->first_mir_insn->next == tk->last_mir_insn) && 439 ((SelectKind(ft->first_mir_insn) == kSelectMove) || 440 (SelectKind(ft->first_mir_insn) == kSelectConst)) && 441 (SelectKind(ft->first_mir_insn) == SelectKind(tk->first_mir_insn)) && 442 (SelectKind(tk->last_mir_insn) == kSelectGoto)) { 443 // Almost there. Are the instructions targeting the same vreg? 444 MIR* if_true = tk->first_mir_insn; 445 MIR* if_false = ft->first_mir_insn; 446 // It's possible that the target of the select isn't used - skip those (rare) cases. 447 MIR* phi = FindPhi(tk_tk, if_true->ssa_rep->defs[0]); 448 if ((phi != NULL) && (if_true->dalvikInsn.vA == if_false->dalvikInsn.vA)) { 449 /* 450 * We'll convert the IF_EQZ/IF_NEZ to a SELECT. We need to find the 451 * Phi node in the merge block and delete it (while using the SSA name 452 * of the merge as the target of the SELECT. Delete both taken and 453 * fallthrough blocks, and set fallthrough to merge block. 454 * NOTE: not updating other dataflow info (no longer used at this point). 455 * If this changes, need to update i_dom, etc. here (and in CombineBlocks). 456 */ 457 mir->meta.ccode = ConditionCodeForIfCcZ(mir->dalvikInsn.opcode); 458 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpSelect); 459 bool const_form = (SelectKind(if_true) == kSelectConst); 460 if ((SelectKind(if_true) == kSelectMove)) { 461 if (IsConst(if_true->ssa_rep->uses[0]) && 462 IsConst(if_false->ssa_rep->uses[0])) { 463 const_form = true; 464 if_true->dalvikInsn.vB = ConstantValue(if_true->ssa_rep->uses[0]); 465 if_false->dalvikInsn.vB = ConstantValue(if_false->ssa_rep->uses[0]); 466 } 467 } 468 if (const_form) { 469 /* 470 * TODO: If both constants are the same value, then instead of generating 471 * a select, we should simply generate a const bytecode. This should be 472 * considered after inlining which can lead to CFG of this form. 473 */ 474 // "true" set val in vB 475 mir->dalvikInsn.vB = if_true->dalvikInsn.vB; 476 // "false" set val in vC 477 mir->dalvikInsn.vC = if_false->dalvikInsn.vB; 478 } else { 479 DCHECK_EQ(SelectKind(if_true), kSelectMove); 480 DCHECK_EQ(SelectKind(if_false), kSelectMove); 481 int* src_ssa = 482 static_cast<int*>(arena_->Alloc(sizeof(int) * 3, kArenaAllocDFInfo)); 483 src_ssa[0] = mir->ssa_rep->uses[0]; 484 src_ssa[1] = if_true->ssa_rep->uses[0]; 485 src_ssa[2] = if_false->ssa_rep->uses[0]; 486 mir->ssa_rep->uses = src_ssa; 487 mir->ssa_rep->num_uses = 3; 488 } 489 mir->ssa_rep->num_defs = 1; 490 mir->ssa_rep->defs = 491 static_cast<int*>(arena_->Alloc(sizeof(int) * 1, kArenaAllocDFInfo)); 492 mir->ssa_rep->fp_def = 493 static_cast<bool*>(arena_->Alloc(sizeof(bool) * 1, kArenaAllocDFInfo)); 494 mir->ssa_rep->fp_def[0] = if_true->ssa_rep->fp_def[0]; 495 // Match type of uses to def. 496 mir->ssa_rep->fp_use = 497 static_cast<bool*>(arena_->Alloc(sizeof(bool) * mir->ssa_rep->num_uses, 498 kArenaAllocDFInfo)); 499 for (int i = 0; i < mir->ssa_rep->num_uses; i++) { 500 mir->ssa_rep->fp_use[i] = mir->ssa_rep->fp_def[0]; 501 } 502 /* 503 * There is usually a Phi node in the join block for our two cases. If the 504 * Phi node only contains our two cases as input, we will use the result 505 * SSA name of the Phi node as our select result and delete the Phi. If 506 * the Phi node has more than two operands, we will arbitrarily use the SSA 507 * name of the "true" path, delete the SSA name of the "false" path from the 508 * Phi node (and fix up the incoming arc list). 509 */ 510 if (phi->ssa_rep->num_uses == 2) { 511 mir->ssa_rep->defs[0] = phi->ssa_rep->defs[0]; 512 phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop); 513 } else { 514 int dead_def = if_false->ssa_rep->defs[0]; 515 int live_def = if_true->ssa_rep->defs[0]; 516 mir->ssa_rep->defs[0] = live_def; 517 BasicBlockId* incoming = phi->meta.phi_incoming; 518 for (int i = 0; i < phi->ssa_rep->num_uses; i++) { 519 if (phi->ssa_rep->uses[i] == live_def) { 520 incoming[i] = bb->id; 521 } 522 } 523 for (int i = 0; i < phi->ssa_rep->num_uses; i++) { 524 if (phi->ssa_rep->uses[i] == dead_def) { 525 int last_slot = phi->ssa_rep->num_uses - 1; 526 phi->ssa_rep->uses[i] = phi->ssa_rep->uses[last_slot]; 527 incoming[i] = incoming[last_slot]; 528 } 529 } 530 } 531 phi->ssa_rep->num_uses--; 532 bb->taken = NullBasicBlockId; 533 tk->block_type = kDead; 534 for (MIR* tmir = ft->first_mir_insn; tmir != NULL; tmir = tmir->next) { 535 tmir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop); 536 } 537 } 538 } 539 } 540 } 541 } 542 bb = ((cu_->disable_opt & (1 << kSuppressExceptionEdges)) != 0) ? NextDominatedBlock(bb) : NULL; 543 } 544 545 return true; 546} 547 548/* Collect stats on number of checks removed */ 549void MIRGraph::CountChecks(struct BasicBlock* bb) { 550 if (bb->data_flow_info != NULL) { 551 for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 552 if (mir->ssa_rep == NULL) { 553 continue; 554 } 555 uint64_t df_attributes = GetDataFlowAttributes(mir); 556 if (df_attributes & DF_HAS_NULL_CHKS) { 557 checkstats_->null_checks++; 558 if (mir->optimization_flags & MIR_IGNORE_NULL_CHECK) { 559 checkstats_->null_checks_eliminated++; 560 } 561 } 562 if (df_attributes & DF_HAS_RANGE_CHKS) { 563 checkstats_->range_checks++; 564 if (mir->optimization_flags & MIR_IGNORE_RANGE_CHECK) { 565 checkstats_->range_checks_eliminated++; 566 } 567 } 568 } 569 } 570} 571 572/* Try to make common case the fallthrough path */ 573bool MIRGraph::LayoutBlocks(BasicBlock* bb) { 574 // TODO: For now, just looking for direct throws. Consider generalizing for profile feedback 575 if (!bb->explicit_throw) { 576 return false; 577 } 578 BasicBlock* walker = bb; 579 while (true) { 580 // Check termination conditions 581 if ((walker->block_type == kEntryBlock) || (Predecessors(walker) != 1)) { 582 break; 583 } 584 BasicBlock* prev = GetBasicBlock(walker->predecessors->Get(0)); 585 if (prev->conditional_branch) { 586 if (GetBasicBlock(prev->fall_through) == walker) { 587 // Already done - return 588 break; 589 } 590 DCHECK_EQ(walker, GetBasicBlock(prev->taken)); 591 // Got one. Flip it and exit 592 Instruction::Code opcode = prev->last_mir_insn->dalvikInsn.opcode; 593 switch (opcode) { 594 case Instruction::IF_EQ: opcode = Instruction::IF_NE; break; 595 case Instruction::IF_NE: opcode = Instruction::IF_EQ; break; 596 case Instruction::IF_LT: opcode = Instruction::IF_GE; break; 597 case Instruction::IF_GE: opcode = Instruction::IF_LT; break; 598 case Instruction::IF_GT: opcode = Instruction::IF_LE; break; 599 case Instruction::IF_LE: opcode = Instruction::IF_GT; break; 600 case Instruction::IF_EQZ: opcode = Instruction::IF_NEZ; break; 601 case Instruction::IF_NEZ: opcode = Instruction::IF_EQZ; break; 602 case Instruction::IF_LTZ: opcode = Instruction::IF_GEZ; break; 603 case Instruction::IF_GEZ: opcode = Instruction::IF_LTZ; break; 604 case Instruction::IF_GTZ: opcode = Instruction::IF_LEZ; break; 605 case Instruction::IF_LEZ: opcode = Instruction::IF_GTZ; break; 606 default: LOG(FATAL) << "Unexpected opcode " << opcode; 607 } 608 prev->last_mir_insn->dalvikInsn.opcode = opcode; 609 BasicBlockId t_bb = prev->taken; 610 prev->taken = prev->fall_through; 611 prev->fall_through = t_bb; 612 break; 613 } 614 walker = prev; 615 } 616 return false; 617} 618 619/* Combine any basic blocks terminated by instructions that we now know can't throw */ 620void MIRGraph::CombineBlocks(struct BasicBlock* bb) { 621 // Loop here to allow combining a sequence of blocks 622 while (true) { 623 // Check termination conditions 624 if ((bb->first_mir_insn == NULL) 625 || (bb->data_flow_info == NULL) 626 || (bb->block_type == kExceptionHandling) 627 || (bb->block_type == kExitBlock) 628 || (bb->block_type == kDead) 629 || (bb->taken == NullBasicBlockId) 630 || (GetBasicBlock(bb->taken)->block_type != kExceptionHandling) 631 || (bb->successor_block_list_type != kNotUsed) 632 || (static_cast<int>(bb->last_mir_insn->dalvikInsn.opcode) != kMirOpCheck)) { 633 break; 634 } 635 636 // Test the kMirOpCheck instruction 637 MIR* mir = bb->last_mir_insn; 638 // Grab the attributes from the paired opcode 639 MIR* throw_insn = mir->meta.throw_insn; 640 uint64_t df_attributes = GetDataFlowAttributes(throw_insn); 641 bool can_combine = true; 642 if (df_attributes & DF_HAS_NULL_CHKS) { 643 can_combine &= ((throw_insn->optimization_flags & MIR_IGNORE_NULL_CHECK) != 0); 644 } 645 if (df_attributes & DF_HAS_RANGE_CHKS) { 646 can_combine &= ((throw_insn->optimization_flags & MIR_IGNORE_RANGE_CHECK) != 0); 647 } 648 if (!can_combine) { 649 break; 650 } 651 // OK - got one. Combine 652 BasicBlock* bb_next = GetBasicBlock(bb->fall_through); 653 DCHECK(!bb_next->catch_entry); 654 DCHECK_EQ(Predecessors(bb_next), 1U); 655 // Overwrite the kOpCheck insn with the paired opcode 656 DCHECK_EQ(bb_next->first_mir_insn, throw_insn); 657 *bb->last_mir_insn = *throw_insn; 658 // Use the successor info from the next block 659 bb->successor_block_list_type = bb_next->successor_block_list_type; 660 bb->successor_blocks = bb_next->successor_blocks; 661 // Use the ending block linkage from the next block 662 bb->fall_through = bb_next->fall_through; 663 GetBasicBlock(bb->taken)->block_type = kDead; // Kill the unused exception block 664 bb->taken = bb_next->taken; 665 // Include the rest of the instructions 666 bb->last_mir_insn = bb_next->last_mir_insn; 667 /* 668 * If lower-half of pair of blocks to combine contained a return, move the flag 669 * to the newly combined block. 670 */ 671 bb->terminated_by_return = bb_next->terminated_by_return; 672 673 /* 674 * NOTE: we aren't updating all dataflow info here. Should either make sure this pass 675 * happens after uses of i_dominated, dom_frontier or update the dataflow info here. 676 */ 677 678 // Kill bb_next and remap now-dead id to parent 679 bb_next->block_type = kDead; 680 block_id_map_.Overwrite(bb_next->id, bb->id); 681 682 // Now, loop back and see if we can keep going 683 } 684} 685 686void MIRGraph::EliminateNullChecksAndInferTypesStart() { 687 if ((cu_->disable_opt & (1 << kNullCheckElimination)) == 0) { 688 if (kIsDebugBuild) { 689 AllNodesIterator iter(this); 690 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) { 691 CHECK(bb->data_flow_info == nullptr || bb->data_flow_info->ending_check_v == nullptr); 692 } 693 } 694 695 DCHECK(temp_scoped_alloc_.get() == nullptr); 696 temp_scoped_alloc_.reset(ScopedArenaAllocator::Create(&cu_->arena_stack)); 697 temp_bit_vector_size_ = GetNumSSARegs(); 698 temp_bit_vector_ = new (temp_scoped_alloc_.get()) ArenaBitVector( 699 temp_scoped_alloc_.get(), temp_bit_vector_size_, false, kBitMapTempSSARegisterV); 700 } 701} 702 703/* 704 * Eliminate unnecessary null checks for a basic block. Also, while we're doing 705 * an iterative walk go ahead and perform type and size inference. 706 */ 707bool MIRGraph::EliminateNullChecksAndInferTypes(BasicBlock* bb) { 708 if (bb->data_flow_info == NULL) return false; 709 bool infer_changed = false; 710 bool do_nce = ((cu_->disable_opt & (1 << kNullCheckElimination)) == 0); 711 712 ArenaBitVector* ssa_regs_to_check = temp_bit_vector_; 713 if (do_nce) { 714 /* 715 * Set initial state. Be conservative with catch 716 * blocks and start with no assumptions about null check 717 * status (except for "this"). 718 */ 719 if ((bb->block_type == kEntryBlock) | bb->catch_entry) { 720 ssa_regs_to_check->ClearAllBits(); 721 // Assume all ins are objects. 722 for (uint16_t in_reg = cu_->num_dalvik_registers - cu_->num_ins; 723 in_reg < cu_->num_dalvik_registers; in_reg++) { 724 ssa_regs_to_check->SetBit(in_reg); 725 } 726 if ((cu_->access_flags & kAccStatic) == 0) { 727 // If non-static method, mark "this" as non-null 728 int this_reg = cu_->num_dalvik_registers - cu_->num_ins; 729 ssa_regs_to_check->ClearBit(this_reg); 730 } 731 } else if (bb->predecessors->Size() == 1) { 732 BasicBlock* pred_bb = GetBasicBlock(bb->predecessors->Get(0)); 733 // pred_bb must have already been processed at least once. 734 DCHECK(pred_bb->data_flow_info->ending_check_v != nullptr); 735 ssa_regs_to_check->Copy(pred_bb->data_flow_info->ending_check_v); 736 if (pred_bb->block_type == kDalvikByteCode) { 737 // Check to see if predecessor had an explicit null-check. 738 MIR* last_insn = pred_bb->last_mir_insn; 739 if (last_insn != nullptr) { 740 Instruction::Code last_opcode = last_insn->dalvikInsn.opcode; 741 if (last_opcode == Instruction::IF_EQZ) { 742 if (pred_bb->fall_through == bb->id) { 743 // The fall-through of a block following a IF_EQZ, set the vA of the IF_EQZ to show that 744 // it can't be null. 745 ssa_regs_to_check->ClearBit(last_insn->ssa_rep->uses[0]); 746 } 747 } else if (last_opcode == Instruction::IF_NEZ) { 748 if (pred_bb->taken == bb->id) { 749 // The taken block following a IF_NEZ, set the vA of the IF_NEZ to show that it can't be 750 // null. 751 ssa_regs_to_check->ClearBit(last_insn->ssa_rep->uses[0]); 752 } 753 } 754 } 755 } 756 } else { 757 // Starting state is union of all incoming arcs 758 GrowableArray<BasicBlockId>::Iterator iter(bb->predecessors); 759 BasicBlock* pred_bb = GetBasicBlock(iter.Next()); 760 CHECK(pred_bb != NULL); 761 while (pred_bb->data_flow_info->ending_check_v == nullptr) { 762 pred_bb = GetBasicBlock(iter.Next()); 763 // At least one predecessor must have been processed before this bb. 764 DCHECK(pred_bb != nullptr); 765 DCHECK(pred_bb->data_flow_info != nullptr); 766 } 767 ssa_regs_to_check->Copy(pred_bb->data_flow_info->ending_check_v); 768 while (true) { 769 pred_bb = GetBasicBlock(iter.Next()); 770 if (!pred_bb) break; 771 DCHECK(pred_bb->data_flow_info != nullptr); 772 if (pred_bb->data_flow_info->ending_check_v == nullptr) { 773 continue; 774 } 775 ssa_regs_to_check->Union(pred_bb->data_flow_info->ending_check_v); 776 } 777 } 778 // At this point, ssa_regs_to_check shows which sregs have an object definition with 779 // no intervening uses. 780 } 781 782 // Walk through the instruction in the block, updating as necessary 783 for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 784 if (mir->ssa_rep == NULL) { 785 continue; 786 } 787 788 // Propagate type info. 789 infer_changed = InferTypeAndSize(bb, mir, infer_changed); 790 if (!do_nce) { 791 continue; 792 } 793 794 uint64_t df_attributes = GetDataFlowAttributes(mir); 795 796 // Might need a null check? 797 if (df_attributes & DF_HAS_NULL_CHKS) { 798 int src_idx; 799 if (df_attributes & DF_NULL_CHK_1) { 800 src_idx = 1; 801 } else if (df_attributes & DF_NULL_CHK_2) { 802 src_idx = 2; 803 } else { 804 src_idx = 0; 805 } 806 int src_sreg = mir->ssa_rep->uses[src_idx]; 807 if (!ssa_regs_to_check->IsBitSet(src_sreg)) { 808 // Eliminate the null check. 809 mir->optimization_flags |= MIR_IGNORE_NULL_CHECK; 810 } else { 811 // Do the null check. 812 mir->optimization_flags &= ~MIR_IGNORE_NULL_CHECK; 813 // Mark s_reg as null-checked 814 ssa_regs_to_check->ClearBit(src_sreg); 815 } 816 } 817 818 if ((df_attributes & DF_A_WIDE) || 819 (df_attributes & (DF_REF_A | DF_SETS_CONST | DF_NULL_TRANSFER)) == 0) { 820 continue; 821 } 822 823 /* 824 * First, mark all object definitions as requiring null check. 825 * Note: we can't tell if a CONST definition might be used as an object, so treat 826 * them all as object definitions. 827 */ 828 if (((df_attributes & (DF_DA | DF_REF_A)) == (DF_DA | DF_REF_A)) || 829 (df_attributes & DF_SETS_CONST)) { 830 ssa_regs_to_check->SetBit(mir->ssa_rep->defs[0]); 831 } 832 833 // Now, remove mark from all object definitions we know are non-null. 834 if (df_attributes & DF_NON_NULL_DST) { 835 // Mark target of NEW* as non-null 836 ssa_regs_to_check->ClearBit(mir->ssa_rep->defs[0]); 837 } 838 839 // Mark non-null returns from invoke-style NEW* 840 if (df_attributes & DF_NON_NULL_RET) { 841 MIR* next_mir = mir->next; 842 // Next should be an MOVE_RESULT_OBJECT 843 if (next_mir && 844 next_mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) { 845 // Mark as null checked 846 ssa_regs_to_check->ClearBit(next_mir->ssa_rep->defs[0]); 847 } else { 848 if (next_mir) { 849 LOG(WARNING) << "Unexpected opcode following new: " << next_mir->dalvikInsn.opcode; 850 } else if (bb->fall_through != NullBasicBlockId) { 851 // Look in next basic block 852 struct BasicBlock* next_bb = GetBasicBlock(bb->fall_through); 853 for (MIR* tmir = next_bb->first_mir_insn; tmir != NULL; 854 tmir =tmir->next) { 855 if (static_cast<int>(tmir->dalvikInsn.opcode) >= static_cast<int>(kMirOpFirst)) { 856 continue; 857 } 858 // First non-pseudo should be MOVE_RESULT_OBJECT 859 if (tmir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) { 860 // Mark as null checked 861 ssa_regs_to_check->ClearBit(tmir->ssa_rep->defs[0]); 862 } else { 863 LOG(WARNING) << "Unexpected op after new: " << tmir->dalvikInsn.opcode; 864 } 865 break; 866 } 867 } 868 } 869 } 870 871 /* 872 * Propagate nullcheck state on register copies (including 873 * Phi pseudo copies. For the latter, nullcheck state is 874 * the "or" of all the Phi's operands. 875 */ 876 if (df_attributes & (DF_NULL_TRANSFER_0 | DF_NULL_TRANSFER_N)) { 877 int tgt_sreg = mir->ssa_rep->defs[0]; 878 int operands = (df_attributes & DF_NULL_TRANSFER_0) ? 1 : 879 mir->ssa_rep->num_uses; 880 bool needs_null_check = false; 881 for (int i = 0; i < operands; i++) { 882 needs_null_check |= ssa_regs_to_check->IsBitSet(mir->ssa_rep->uses[i]); 883 } 884 if (needs_null_check) { 885 ssa_regs_to_check->SetBit(tgt_sreg); 886 } else { 887 ssa_regs_to_check->ClearBit(tgt_sreg); 888 } 889 } 890 } 891 892 // Did anything change? 893 bool nce_changed = false; 894 if (do_nce) { 895 if (bb->data_flow_info->ending_check_v == nullptr) { 896 DCHECK(temp_scoped_alloc_.get() != nullptr); 897 bb->data_flow_info->ending_check_v = new (temp_scoped_alloc_.get()) ArenaBitVector( 898 temp_scoped_alloc_.get(), temp_bit_vector_size_, false, kBitMapNullCheck); 899 nce_changed = ssa_regs_to_check->GetHighestBitSet() != -1; 900 bb->data_flow_info->ending_check_v->Copy(ssa_regs_to_check); 901 } else if (!ssa_regs_to_check->SameBitsSet(bb->data_flow_info->ending_check_v)) { 902 nce_changed = true; 903 bb->data_flow_info->ending_check_v->Copy(ssa_regs_to_check); 904 } 905 } 906 return infer_changed | nce_changed; 907} 908 909void MIRGraph::EliminateNullChecksAndInferTypesEnd() { 910 if ((cu_->disable_opt & (1 << kNullCheckElimination)) == 0) { 911 // Clean up temporaries. 912 temp_bit_vector_size_ = 0u; 913 temp_bit_vector_ = nullptr; 914 AllNodesIterator iter(this); 915 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) { 916 if (bb->data_flow_info != nullptr) { 917 bb->data_flow_info->ending_check_v = nullptr; 918 } 919 } 920 DCHECK(temp_scoped_alloc_.get() != nullptr); 921 temp_scoped_alloc_.reset(); 922 } 923} 924 925bool MIRGraph::EliminateClassInitChecksGate() { 926 if ((cu_->disable_opt & (1 << kClassInitCheckElimination)) != 0 || 927 !cu_->mir_graph->HasStaticFieldAccess()) { 928 return false; 929 } 930 931 if (kIsDebugBuild) { 932 AllNodesIterator iter(this); 933 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) { 934 CHECK(bb->data_flow_info == nullptr || bb->data_flow_info->ending_check_v == nullptr); 935 } 936 } 937 938 DCHECK(temp_scoped_alloc_.get() == nullptr); 939 temp_scoped_alloc_.reset(ScopedArenaAllocator::Create(&cu_->arena_stack)); 940 941 // Each insn we use here has at least 2 code units, offset/2 will be a unique index. 942 const size_t end = (cu_->code_item->insns_size_in_code_units_ + 1u) / 2u; 943 temp_insn_data_ = static_cast<uint16_t*>( 944 temp_scoped_alloc_->Alloc(end * sizeof(*temp_insn_data_), kArenaAllocGrowableArray)); 945 946 uint32_t unique_class_count = 0u; 947 { 948 // Get unique_class_count and store indexes in temp_insn_data_ using a map on a nested 949 // ScopedArenaAllocator. 950 951 // Embed the map value in the entry to save space. 952 struct MapEntry { 953 // Map key: the class identified by the declaring dex file and type index. 954 const DexFile* declaring_dex_file; 955 uint16_t declaring_class_idx; 956 // Map value: index into bit vectors of classes requiring initialization checks. 957 uint16_t index; 958 }; 959 struct MapEntryComparator { 960 bool operator()(const MapEntry& lhs, const MapEntry& rhs) const { 961 if (lhs.declaring_class_idx != rhs.declaring_class_idx) { 962 return lhs.declaring_class_idx < rhs.declaring_class_idx; 963 } 964 return lhs.declaring_dex_file < rhs.declaring_dex_file; 965 } 966 }; 967 968 ScopedArenaAllocator allocator(&cu_->arena_stack); 969 ScopedArenaSet<MapEntry, MapEntryComparator> class_to_index_map(MapEntryComparator(), 970 allocator.Adapter()); 971 972 // First, find all SGET/SPUTs that may need class initialization checks, record INVOKE_STATICs. 973 AllNodesIterator iter(this); 974 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) { 975 for (MIR* mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) { 976 DCHECK(bb->data_flow_info != nullptr); 977 if (mir->dalvikInsn.opcode >= Instruction::SGET && 978 mir->dalvikInsn.opcode <= Instruction::SPUT_SHORT) { 979 const MirSFieldLoweringInfo& field_info = GetSFieldLoweringInfo(mir); 980 uint16_t index = 0xffffu; 981 if (field_info.IsResolved() && !field_info.IsInitialized()) { 982 DCHECK_LT(class_to_index_map.size(), 0xffffu); 983 MapEntry entry = { 984 field_info.DeclaringDexFile(), 985 field_info.DeclaringClassIndex(), 986 static_cast<uint16_t>(class_to_index_map.size()) 987 }; 988 index = class_to_index_map.insert(entry).first->index; 989 } 990 // Using offset/2 for index into temp_insn_data_. 991 temp_insn_data_[mir->offset / 2u] = index; 992 } 993 } 994 } 995 unique_class_count = static_cast<uint32_t>(class_to_index_map.size()); 996 } 997 998 if (unique_class_count == 0u) { 999 // All SGET/SPUTs refer to initialized classes. Nothing to do. 1000 temp_insn_data_ = nullptr; 1001 temp_scoped_alloc_.reset(); 1002 return false; 1003 } 1004 1005 temp_bit_vector_size_ = unique_class_count; 1006 temp_bit_vector_ = new (temp_scoped_alloc_.get()) ArenaBitVector( 1007 temp_scoped_alloc_.get(), temp_bit_vector_size_, false, kBitMapClInitCheck); 1008 DCHECK_GT(temp_bit_vector_size_, 0u); 1009 return true; 1010} 1011 1012/* 1013 * Eliminate unnecessary class initialization checks for a basic block. 1014 */ 1015bool MIRGraph::EliminateClassInitChecks(BasicBlock* bb) { 1016 DCHECK_EQ((cu_->disable_opt & (1 << kClassInitCheckElimination)), 0u); 1017 if (bb->data_flow_info == NULL) { 1018 return false; 1019 } 1020 1021 /* 1022 * Set initial state. Be conservative with catch 1023 * blocks and start with no assumptions about class init check status. 1024 */ 1025 ArenaBitVector* classes_to_check = temp_bit_vector_; 1026 DCHECK(classes_to_check != nullptr); 1027 if ((bb->block_type == kEntryBlock) | bb->catch_entry) { 1028 classes_to_check->SetInitialBits(temp_bit_vector_size_); 1029 } else if (bb->predecessors->Size() == 1) { 1030 BasicBlock* pred_bb = GetBasicBlock(bb->predecessors->Get(0)); 1031 // pred_bb must have already been processed at least once. 1032 DCHECK(pred_bb != nullptr); 1033 DCHECK(pred_bb->data_flow_info != nullptr); 1034 DCHECK(pred_bb->data_flow_info->ending_check_v != nullptr); 1035 classes_to_check->Copy(pred_bb->data_flow_info->ending_check_v); 1036 } else { 1037 // Starting state is union of all incoming arcs 1038 GrowableArray<BasicBlockId>::Iterator iter(bb->predecessors); 1039 BasicBlock* pred_bb = GetBasicBlock(iter.Next()); 1040 DCHECK(pred_bb != NULL); 1041 DCHECK(pred_bb->data_flow_info != NULL); 1042 while (pred_bb->data_flow_info->ending_check_v == nullptr) { 1043 pred_bb = GetBasicBlock(iter.Next()); 1044 // At least one predecessor must have been processed before this bb. 1045 DCHECK(pred_bb != nullptr); 1046 DCHECK(pred_bb->data_flow_info != nullptr); 1047 } 1048 classes_to_check->Copy(pred_bb->data_flow_info->ending_check_v); 1049 while (true) { 1050 pred_bb = GetBasicBlock(iter.Next()); 1051 if (!pred_bb) break; 1052 DCHECK(pred_bb->data_flow_info != nullptr); 1053 if (pred_bb->data_flow_info->ending_check_v == nullptr) { 1054 continue; 1055 } 1056 classes_to_check->Union(pred_bb->data_flow_info->ending_check_v); 1057 } 1058 } 1059 // At this point, classes_to_check shows which classes need clinit checks. 1060 1061 // Walk through the instruction in the block, updating as necessary 1062 for (MIR* mir = bb->first_mir_insn; mir != nullptr; mir = mir->next) { 1063 if (mir->dalvikInsn.opcode >= Instruction::SGET && 1064 mir->dalvikInsn.opcode <= Instruction::SPUT_SHORT) { 1065 uint16_t index = temp_insn_data_[mir->offset / 2u]; 1066 if (index != 0xffffu) { 1067 if (mir->dalvikInsn.opcode >= Instruction::SGET && 1068 mir->dalvikInsn.opcode <= Instruction::SPUT_SHORT) { 1069 if (!classes_to_check->IsBitSet(index)) { 1070 // Eliminate the class init check. 1071 mir->optimization_flags |= MIR_IGNORE_CLINIT_CHECK; 1072 } else { 1073 // Do the class init check. 1074 mir->optimization_flags &= ~MIR_IGNORE_CLINIT_CHECK; 1075 } 1076 } 1077 // Mark the class as initialized. 1078 classes_to_check->ClearBit(index); 1079 } 1080 } 1081 } 1082 1083 // Did anything change? 1084 bool changed = false; 1085 if (bb->data_flow_info->ending_check_v == nullptr) { 1086 DCHECK(temp_scoped_alloc_.get() != nullptr); 1087 DCHECK(bb->data_flow_info != nullptr); 1088 bb->data_flow_info->ending_check_v = new (temp_scoped_alloc_.get()) ArenaBitVector( 1089 temp_scoped_alloc_.get(), temp_bit_vector_size_, false, kBitMapClInitCheck); 1090 changed = classes_to_check->GetHighestBitSet() != -1; 1091 bb->data_flow_info->ending_check_v->Copy(classes_to_check); 1092 } else if (!classes_to_check->Equal(bb->data_flow_info->ending_check_v)) { 1093 changed = true; 1094 bb->data_flow_info->ending_check_v->Copy(classes_to_check); 1095 } 1096 return changed; 1097} 1098 1099void MIRGraph::EliminateClassInitChecksEnd() { 1100 // Clean up temporaries. 1101 temp_bit_vector_size_ = 0u; 1102 temp_bit_vector_ = nullptr; 1103 AllNodesIterator iter(this); 1104 for (BasicBlock* bb = iter.Next(); bb != nullptr; bb = iter.Next()) { 1105 if (bb->data_flow_info != nullptr) { 1106 bb->data_flow_info->ending_check_v = nullptr; 1107 } 1108 } 1109 1110 DCHECK(temp_insn_data_ != nullptr); 1111 temp_insn_data_ = nullptr; 1112 DCHECK(temp_scoped_alloc_.get() != nullptr); 1113 temp_scoped_alloc_.reset(); 1114} 1115 1116void MIRGraph::ComputeInlineIFieldLoweringInfo(uint16_t field_idx, MIR* invoke, MIR* iget_or_iput) { 1117 uint32_t method_index = invoke->meta.method_lowering_info; 1118 if (temp_bit_vector_->IsBitSet(method_index)) { 1119 iget_or_iput->meta.ifield_lowering_info = temp_insn_data_[method_index]; 1120 DCHECK_EQ(field_idx, GetIFieldLoweringInfo(iget_or_iput).FieldIndex()); 1121 return; 1122 } 1123 1124 const MirMethodLoweringInfo& method_info = GetMethodLoweringInfo(invoke); 1125 MethodReference target = method_info.GetTargetMethod(); 1126 DexCompilationUnit inlined_unit( 1127 cu_, cu_->class_loader, cu_->class_linker, *target.dex_file, 1128 nullptr /* code_item not used */, 0u /* class_def_idx not used */, target.dex_method_index, 1129 0u /* access_flags not used */, nullptr /* verified_method not used */); 1130 MirIFieldLoweringInfo inlined_field_info(field_idx); 1131 MirIFieldLoweringInfo::Resolve(cu_->compiler_driver, &inlined_unit, &inlined_field_info, 1u); 1132 DCHECK(inlined_field_info.IsResolved()); 1133 1134 uint32_t field_info_index = ifield_lowering_infos_.Size(); 1135 ifield_lowering_infos_.Insert(inlined_field_info); 1136 temp_bit_vector_->SetBit(method_index); 1137 temp_insn_data_[method_index] = field_info_index; 1138 iget_or_iput->meta.ifield_lowering_info = field_info_index; 1139} 1140 1141bool MIRGraph::InlineCallsGate() { 1142 if ((cu_->disable_opt & (1 << kSuppressMethodInlining)) != 0 || 1143 method_lowering_infos_.Size() == 0u) { 1144 return false; 1145 } 1146 if (cu_->compiler_driver->GetMethodInlinerMap() == nullptr) { 1147 // This isn't the Quick compiler. 1148 return false; 1149 } 1150 return true; 1151} 1152 1153void MIRGraph::InlineCallsStart() { 1154 // Prepare for inlining getters/setters. Since we're inlining at most 1 IGET/IPUT from 1155 // each INVOKE, we can index the data by the MIR::meta::method_lowering_info index. 1156 1157 DCHECK(temp_scoped_alloc_.get() == nullptr); 1158 temp_scoped_alloc_.reset(ScopedArenaAllocator::Create(&cu_->arena_stack)); 1159 temp_bit_vector_size_ = method_lowering_infos_.Size(); 1160 temp_bit_vector_ = new (temp_scoped_alloc_.get()) ArenaBitVector( 1161 temp_scoped_alloc_.get(), temp_bit_vector_size_, false, kBitMapMisc); 1162 temp_bit_vector_->ClearAllBits(); 1163 temp_insn_data_ = static_cast<uint16_t*>(temp_scoped_alloc_->Alloc( 1164 temp_bit_vector_size_ * sizeof(*temp_insn_data_), kArenaAllocGrowableArray)); 1165} 1166 1167void MIRGraph::InlineCalls(BasicBlock* bb) { 1168 if (bb->block_type != kDalvikByteCode) { 1169 return; 1170 } 1171 for (MIR* mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 1172 if (!(Instruction::FlagsOf(mir->dalvikInsn.opcode) & Instruction::kInvoke)) { 1173 continue; 1174 } 1175 const MirMethodLoweringInfo& method_info = GetMethodLoweringInfo(mir); 1176 if (!method_info.FastPath()) { 1177 continue; 1178 } 1179 InvokeType sharp_type = method_info.GetSharpType(); 1180 if ((sharp_type != kDirect) && 1181 (sharp_type != kStatic || method_info.NeedsClassInitialization())) { 1182 continue; 1183 } 1184 DCHECK(cu_->compiler_driver->GetMethodInlinerMap() != nullptr); 1185 MethodReference target = method_info.GetTargetMethod(); 1186 if (cu_->compiler_driver->GetMethodInlinerMap()->GetMethodInliner(target.dex_file) 1187 ->GenInline(this, bb, mir, target.dex_method_index)) { 1188 if (cu_->verbose) { 1189 LOG(INFO) << "In \"" << PrettyMethod(cu_->method_idx, *cu_->dex_file) 1190 << "\" @0x" << std::hex << mir->offset 1191 << " inlined " << method_info.GetInvokeType() << " (" << sharp_type << ") call to \"" 1192 << PrettyMethod(target.dex_method_index, *target.dex_file) << "\""; 1193 } 1194 } 1195 } 1196} 1197 1198void MIRGraph::InlineCallsEnd() { 1199 DCHECK(temp_insn_data_ != nullptr); 1200 temp_insn_data_ = nullptr; 1201 DCHECK(temp_bit_vector_ != nullptr); 1202 temp_bit_vector_ = nullptr; 1203 DCHECK(temp_scoped_alloc_.get() != nullptr); 1204 temp_scoped_alloc_.reset(); 1205} 1206 1207void MIRGraph::DumpCheckStats() { 1208 Checkstats* stats = 1209 static_cast<Checkstats*>(arena_->Alloc(sizeof(Checkstats), kArenaAllocDFInfo)); 1210 checkstats_ = stats; 1211 AllNodesIterator iter(this); 1212 for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) { 1213 CountChecks(bb); 1214 } 1215 if (stats->null_checks > 0) { 1216 float eliminated = static_cast<float>(stats->null_checks_eliminated); 1217 float checks = static_cast<float>(stats->null_checks); 1218 LOG(INFO) << "Null Checks: " << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 1219 << stats->null_checks_eliminated << " of " << stats->null_checks << " -> " 1220 << (eliminated/checks) * 100.0 << "%"; 1221 } 1222 if (stats->range_checks > 0) { 1223 float eliminated = static_cast<float>(stats->range_checks_eliminated); 1224 float checks = static_cast<float>(stats->range_checks); 1225 LOG(INFO) << "Range Checks: " << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 1226 << stats->range_checks_eliminated << " of " << stats->range_checks << " -> " 1227 << (eliminated/checks) * 100.0 << "%"; 1228 } 1229} 1230 1231bool MIRGraph::BuildExtendedBBList(struct BasicBlock* bb) { 1232 if (bb->visited) return false; 1233 if (!((bb->block_type == kEntryBlock) || (bb->block_type == kDalvikByteCode) 1234 || (bb->block_type == kExitBlock))) { 1235 // Ignore special blocks 1236 bb->visited = true; 1237 return false; 1238 } 1239 // Must be head of extended basic block. 1240 BasicBlock* start_bb = bb; 1241 extended_basic_blocks_.push_back(bb->id); 1242 bool terminated_by_return = false; 1243 bool do_local_value_numbering = false; 1244 // Visit blocks strictly dominated by this head. 1245 while (bb != NULL) { 1246 bb->visited = true; 1247 terminated_by_return |= bb->terminated_by_return; 1248 do_local_value_numbering |= bb->use_lvn; 1249 bb = NextDominatedBlock(bb); 1250 } 1251 if (terminated_by_return || do_local_value_numbering) { 1252 // Do lvn for all blocks in this extended set. 1253 bb = start_bb; 1254 while (bb != NULL) { 1255 bb->use_lvn = do_local_value_numbering; 1256 bb->dominates_return = terminated_by_return; 1257 bb = NextDominatedBlock(bb); 1258 } 1259 } 1260 return false; // Not iterative - return value will be ignored 1261} 1262 1263void MIRGraph::BasicBlockOptimization() { 1264 if ((cu_->disable_opt & (1 << kSuppressExceptionEdges)) != 0) { 1265 ClearAllVisitedFlags(); 1266 PreOrderDfsIterator iter2(this); 1267 for (BasicBlock* bb = iter2.Next(); bb != NULL; bb = iter2.Next()) { 1268 BuildExtendedBBList(bb); 1269 } 1270 // Perform extended basic block optimizations. 1271 for (unsigned int i = 0; i < extended_basic_blocks_.size(); i++) { 1272 BasicBlockOpt(GetBasicBlock(extended_basic_blocks_[i])); 1273 } 1274 } else { 1275 PreOrderDfsIterator iter(this); 1276 for (BasicBlock* bb = iter.Next(); bb != NULL; bb = iter.Next()) { 1277 BasicBlockOpt(bb); 1278 } 1279 } 1280} 1281 1282} // namespace art 1283