arm_lir.h revision 091cc408e9dc87e60fb64c61e186bea568fc3d3a 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_
18#define ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_
19
20#include "dex/compiler_internals.h"
21
22namespace art {
23
24/*
25 * Runtime register usage conventions.
26 *
27 * r0-r3: Argument registers in both Dalvik and C/C++ conventions.
28 *        However, for Dalvik->Dalvik calls we'll pass the target's Method*
29 *        pointer in r0 as a hidden arg0. Otherwise used as codegen scratch
30 *        registers.
31 * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit
32 * r4   : (rARM_SUSPEND) is reserved (suspend check/debugger assist)
33 * r5   : Callee save (promotion target)
34 * r6   : Callee save (promotion target)
35 * r7   : Callee save (promotion target)
36 * r8   : Callee save (promotion target)
37 * r9   : (rARM_SELF) is reserved (pointer to thread-local storage)
38 * r10  : Callee save (promotion target)
39 * r11  : Callee save (promotion target)
40 * r12  : Scratch, may be trashed by linkage stubs
41 * r13  : (sp) is reserved
42 * r14  : (lr) is reserved
43 * r15  : (pc) is reserved
44 *
45 * 5 core temps that codegen can use (r0, r1, r2, r3, r12)
46 * 7 core registers that can be used for promotion
47 *
48 * Floating pointer registers
49 * s0-s31
50 * d0-d15, where d0={s0,s1}, d1={s2,s3}, ... , d15={s30,s31}
51 *
52 * s16-s31 (d8-d15) preserved across C calls
53 * s0-s15 (d0-d7) trashed across C calls
54 *
55 * s0-s15/d0-d7 used as codegen temp/scratch
56 * s16-s31/d8-d31 can be used for promotion.
57 *
58 * Calling convention
59 *     o On a call to a Dalvik method, pass target's Method* in r0
60 *     o r1-r3 will be used for up to the first 3 words of arguments
61 *     o Arguments past the first 3 words will be placed in appropriate
62 *       out slots by the caller.
63 *     o If a 64-bit argument would span the register/memory argument
64 *       boundary, it will instead be fully passed in the frame.
65 *     o Maintain a 16-byte stack alignment
66 *
67 *  Stack frame diagram (stack grows down, higher addresses at top):
68 *
69 * +------------------------+
70 * | IN[ins-1]              |  {Note: resides in caller's frame}
71 * |       .                |
72 * | IN[0]                  |
73 * | caller's Method*       |
74 * +========================+  {Note: start of callee's frame}
75 * | spill region           |  {variable sized - will include lr if non-leaf.}
76 * +------------------------+
77 * | ...filler word...      |  {Note: used as 2nd word of V[locals-1] if long]
78 * +------------------------+
79 * | V[locals-1]            |
80 * | V[locals-2]            |
81 * |      .                 |
82 * |      .                 |
83 * | V[1]                   |
84 * | V[0]                   |
85 * +------------------------+
86 * |  0 to 3 words padding  |
87 * +------------------------+
88 * | OUT[outs-1]            |
89 * | OUT[outs-2]            |
90 * |       .                |
91 * | OUT[0]                 |
92 * | cur_method*            | <<== sp w/ 16-byte alignment
93 * +========================+
94 */
95
96// First FP callee save.
97#define ARM_FP_CALLEE_SAVE_BASE 16
98
99enum ArmResourceEncodingPos {
100  kArmGPReg0   = 0,
101  kArmRegSP    = 13,
102  kArmRegLR    = 14,
103  kArmRegPC    = 15,
104  kArmFPReg0   = 16,
105  kArmFPReg16  = 32,
106  kArmRegEnd   = 48,
107};
108
109#define ENCODE_ARM_REG_LIST(N)      (static_cast<uint64_t>(N))
110#define ENCODE_ARM_REG_SP           (1ULL << kArmRegSP)
111#define ENCODE_ARM_REG_LR           (1ULL << kArmRegLR)
112#define ENCODE_ARM_REG_PC           (1ULL << kArmRegPC)
113#define ENCODE_ARM_REG_FPCS_LIST(N) (static_cast<uint64_t>(N) << kArmFPReg16)
114
115enum ArmNativeRegisterPool {
116  r0           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  0,
117  r1           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  1,
118  r2           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  2,
119  r3           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  3,
120  rARM_SUSPEND = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  4,
121  r5           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  5,
122  r6           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  6,
123  r7           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  7,
124  r8           = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  8,
125  rARM_SELF    = RegStorage::k32BitSolo | RegStorage::kCoreRegister |  9,
126  r10          = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 10,
127  r11          = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 11,
128  r12          = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 12,
129  r13sp        = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 13,
130  rARM_SP      = r13sp,
131  r14lr        = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 14,
132  rARM_LR      = r14lr,
133  r15pc        = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 15,
134  rARM_PC      = r15pc,
135
136  fr0          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  0,
137  fr1          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  1,
138  fr2          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  2,
139  fr3          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  3,
140  fr4          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  4,
141  fr5          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  5,
142  fr6          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  6,
143  fr7          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  7,
144  fr8          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  8,
145  fr9          = RegStorage::k32BitSolo | RegStorage::kFloatingPoint |  9,
146  fr10         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 10,
147  fr11         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 11,
148  fr12         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 12,
149  fr13         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 13,
150  fr14         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 14,
151  fr15         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 15,
152  fr16         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 16,
153  fr17         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 17,
154  fr18         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 18,
155  fr19         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 19,
156  fr20         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 20,
157  fr21         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 21,
158  fr22         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 22,
159  fr23         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 23,
160  fr24         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 24,
161  fr25         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 25,
162  fr26         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 26,
163  fr27         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 27,
164  fr28         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 28,
165  fr29         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 29,
166  fr30         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 30,
167  fr31         = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 31,
168
169  dr0          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  0,
170  dr1          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  1,
171  dr2          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  2,
172  dr3          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  3,
173  dr4          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  4,
174  dr5          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  5,
175  dr6          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  6,
176  dr7          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  7,
177  dr8          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  8,
178  dr9          = RegStorage::k64BitSolo | RegStorage::kFloatingPoint |  9,
179  dr10         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 10,
180  dr11         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 11,
181  dr12         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 12,
182  dr13         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 13,
183  dr14         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 14,
184  dr15         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 15,
185#if 0
186  // Enable when def/use and runtime able to handle these.
187  dr16         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 16,
188  dr17         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 17,
189  dr18         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 18,
190  dr19         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 19,
191  dr20         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 20,
192  dr21         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 21,
193  dr22         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 22,
194  dr23         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 23,
195  dr24         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 24,
196  dr25         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 25,
197  dr26         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 26,
198  dr27         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 27,
199  dr28         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 28,
200  dr29         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 29,
201  dr30         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 30,
202  dr31         = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 31,
203#endif
204};
205
206constexpr RegStorage rs_r0(RegStorage::kValid | r0);
207constexpr RegStorage rs_r1(RegStorage::kValid | r1);
208constexpr RegStorage rs_r2(RegStorage::kValid | r2);
209constexpr RegStorage rs_r3(RegStorage::kValid | r3);
210constexpr RegStorage rs_rARM_SUSPEND(RegStorage::kValid | rARM_SUSPEND);
211constexpr RegStorage rs_r5(RegStorage::kValid | r5);
212constexpr RegStorage rs_r6(RegStorage::kValid | r6);
213constexpr RegStorage rs_r7(RegStorage::kValid | r7);
214constexpr RegStorage rs_r8(RegStorage::kValid | r8);
215constexpr RegStorage rs_rARM_SELF(RegStorage::kValid | rARM_SELF);
216constexpr RegStorage rs_r10(RegStorage::kValid | r10);
217constexpr RegStorage rs_r11(RegStorage::kValid | r11);
218constexpr RegStorage rs_r12(RegStorage::kValid | r12);
219constexpr RegStorage rs_r13sp(RegStorage::kValid | r13sp);
220constexpr RegStorage rs_rARM_SP(RegStorage::kValid | rARM_SP);
221constexpr RegStorage rs_r14lr(RegStorage::kValid | r14lr);
222constexpr RegStorage rs_rARM_LR(RegStorage::kValid | rARM_LR);
223constexpr RegStorage rs_r15pc(RegStorage::kValid | r15pc);
224constexpr RegStorage rs_rARM_PC(RegStorage::kValid | rARM_PC);
225constexpr RegStorage rs_invalid(RegStorage::kInvalid);
226
227constexpr RegStorage rs_fr0(RegStorage::kValid | fr0);
228constexpr RegStorage rs_fr1(RegStorage::kValid | fr1);
229constexpr RegStorage rs_fr2(RegStorage::kValid | fr2);
230constexpr RegStorage rs_fr3(RegStorage::kValid | fr3);
231constexpr RegStorage rs_fr4(RegStorage::kValid | fr4);
232constexpr RegStorage rs_fr5(RegStorage::kValid | fr5);
233constexpr RegStorage rs_fr6(RegStorage::kValid | fr6);
234constexpr RegStorage rs_fr7(RegStorage::kValid | fr7);
235constexpr RegStorage rs_fr8(RegStorage::kValid | fr8);
236constexpr RegStorage rs_fr9(RegStorage::kValid | fr9);
237constexpr RegStorage rs_fr10(RegStorage::kValid | fr10);
238constexpr RegStorage rs_fr11(RegStorage::kValid | fr11);
239constexpr RegStorage rs_fr12(RegStorage::kValid | fr12);
240constexpr RegStorage rs_fr13(RegStorage::kValid | fr13);
241constexpr RegStorage rs_fr14(RegStorage::kValid | fr14);
242constexpr RegStorage rs_fr15(RegStorage::kValid | fr15);
243constexpr RegStorage rs_fr16(RegStorage::kValid | fr16);
244constexpr RegStorage rs_fr17(RegStorage::kValid | fr17);
245constexpr RegStorage rs_fr18(RegStorage::kValid | fr18);
246constexpr RegStorage rs_fr19(RegStorage::kValid | fr19);
247constexpr RegStorage rs_fr20(RegStorage::kValid | fr20);
248constexpr RegStorage rs_fr21(RegStorage::kValid | fr21);
249constexpr RegStorage rs_fr22(RegStorage::kValid | fr22);
250constexpr RegStorage rs_fr23(RegStorage::kValid | fr23);
251constexpr RegStorage rs_fr24(RegStorage::kValid | fr24);
252constexpr RegStorage rs_fr25(RegStorage::kValid | fr25);
253constexpr RegStorage rs_fr26(RegStorage::kValid | fr26);
254constexpr RegStorage rs_fr27(RegStorage::kValid | fr27);
255constexpr RegStorage rs_fr28(RegStorage::kValid | fr28);
256constexpr RegStorage rs_fr29(RegStorage::kValid | fr29);
257constexpr RegStorage rs_fr30(RegStorage::kValid | fr30);
258constexpr RegStorage rs_fr31(RegStorage::kValid | fr31);
259
260constexpr RegStorage rs_dr0(RegStorage::kValid | dr0);
261constexpr RegStorage rs_dr1(RegStorage::kValid | dr1);
262constexpr RegStorage rs_dr2(RegStorage::kValid | dr2);
263constexpr RegStorage rs_dr3(RegStorage::kValid | dr3);
264constexpr RegStorage rs_dr4(RegStorage::kValid | dr4);
265constexpr RegStorage rs_dr5(RegStorage::kValid | dr5);
266constexpr RegStorage rs_dr6(RegStorage::kValid | dr6);
267constexpr RegStorage rs_dr7(RegStorage::kValid | dr7);
268constexpr RegStorage rs_dr8(RegStorage::kValid | dr8);
269constexpr RegStorage rs_dr9(RegStorage::kValid | dr9);
270constexpr RegStorage rs_dr10(RegStorage::kValid | dr10);
271constexpr RegStorage rs_dr11(RegStorage::kValid | dr11);
272constexpr RegStorage rs_dr12(RegStorage::kValid | dr12);
273constexpr RegStorage rs_dr13(RegStorage::kValid | dr13);
274constexpr RegStorage rs_dr14(RegStorage::kValid | dr14);
275constexpr RegStorage rs_dr15(RegStorage::kValid | dr15);
276#if 0
277constexpr RegStorage rs_dr16(RegStorage::kValid | dr16);
278constexpr RegStorage rs_dr17(RegStorage::kValid | dr17);
279constexpr RegStorage rs_dr18(RegStorage::kValid | dr18);
280constexpr RegStorage rs_dr19(RegStorage::kValid | dr19);
281constexpr RegStorage rs_dr20(RegStorage::kValid | dr20);
282constexpr RegStorage rs_dr21(RegStorage::kValid | dr21);
283constexpr RegStorage rs_dr22(RegStorage::kValid | dr22);
284constexpr RegStorage rs_dr23(RegStorage::kValid | dr23);
285constexpr RegStorage rs_dr24(RegStorage::kValid | dr24);
286constexpr RegStorage rs_dr25(RegStorage::kValid | dr25);
287constexpr RegStorage rs_dr26(RegStorage::kValid | dr26);
288constexpr RegStorage rs_dr27(RegStorage::kValid | dr27);
289constexpr RegStorage rs_dr28(RegStorage::kValid | dr28);
290constexpr RegStorage rs_dr29(RegStorage::kValid | dr29);
291constexpr RegStorage rs_dr30(RegStorage::kValid | dr30);
292constexpr RegStorage rs_dr31(RegStorage::kValid | dr31);
293#endif
294
295// RegisterLocation templates return values (r0, or r0/r1).
296const RegLocation arm_loc_c_return
297    {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1,
298     RegStorage(RegStorage::k32BitSolo, r0), INVALID_SREG, INVALID_SREG};
299const RegLocation arm_loc_c_return_wide
300    {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1,
301     RegStorage(RegStorage::k64BitPair, r0, r1), INVALID_SREG, INVALID_SREG};
302const RegLocation arm_loc_c_return_float
303    {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1,
304     RegStorage(RegStorage::k32BitSolo, r0), INVALID_SREG, INVALID_SREG};
305const RegLocation arm_loc_c_return_double
306    {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1,
307     RegStorage(RegStorage::k64BitPair, r0, r1), INVALID_SREG, INVALID_SREG};
308
309enum ArmShiftEncodings {
310  kArmLsl = 0x0,
311  kArmLsr = 0x1,
312  kArmAsr = 0x2,
313  kArmRor = 0x3
314};
315
316/*
317 * The following enum defines the list of supported Thumb instructions by the
318 * assembler. Their corresponding EncodingMap positions will be defined in
319 * Assemble.cc.
320 */
321enum ArmOpcode {
322  kArmFirst = 0,
323  kArm16BitData = kArmFirst,  // DATA   [0] rd[15..0].
324  kThumbAdcRR,       // adc   [0100000101] rm[5..3] rd[2..0].
325  kThumbAddRRI3,     // add(1)  [0001110] imm_3[8..6] rn[5..3] rd[2..0].
326  kThumbAddRI8,      // add(2)  [00110] rd[10..8] imm_8[7..0].
327  kThumbAddRRR,      // add(3)  [0001100] rm[8..6] rn[5..3] rd[2..0].
328  kThumbAddRRLH,     // add(4)  [01000100] H12[01] rm[5..3] rd[2..0].
329  kThumbAddRRHL,     // add(4)  [01001000] H12[10] rm[5..3] rd[2..0].
330  kThumbAddRRHH,     // add(4)  [01001100] H12[11] rm[5..3] rd[2..0].
331  kThumbAddPcRel,    // add(5)  [10100] rd[10..8] imm_8[7..0].
332  kThumbAddSpRel,    // add(6)  [10101] rd[10..8] imm_8[7..0].
333  kThumbAddSpI7,     // add(7)  [101100000] imm_7[6..0].
334  kThumbAndRR,       // and   [0100000000] rm[5..3] rd[2..0].
335  kThumbAsrRRI5,     // asr(1)  [00010] imm_5[10..6] rm[5..3] rd[2..0].
336  kThumbAsrRR,       // asr(2)  [0100000100] rs[5..3] rd[2..0].
337  kThumbBCond,       // b(1)  [1101] cond[11..8] offset_8[7..0].
338  kThumbBUncond,     // b(2)  [11100] offset_11[10..0].
339  kThumbBicRR,       // bic   [0100001110] rm[5..3] rd[2..0].
340  kThumbBkpt,        // bkpt  [10111110] imm_8[7..0].
341  kThumbBlx1,        // blx(1)  [111] H[10] offset_11[10..0].
342  kThumbBlx2,        // blx(1)  [111] H[01] offset_11[10..0].
343  kThumbBl1,         // blx(1)  [111] H[10] offset_11[10..0].
344  kThumbBl2,         // blx(1)  [111] H[11] offset_11[10..0].
345  kThumbBlxR,        // blx(2)  [010001111] rm[6..3] [000].
346  kThumbBx,          // bx    [010001110] H2[6..6] rm[5..3] SBZ[000].
347  kThumbCmnRR,       // cmn   [0100001011] rm[5..3] rd[2..0].
348  kThumbCmpRI8,      // cmp(1)  [00101] rn[10..8] imm_8[7..0].
349  kThumbCmpRR,       // cmp(2)  [0100001010] rm[5..3] rd[2..0].
350  kThumbCmpLH,       // cmp(3)  [01000101] H12[01] rm[5..3] rd[2..0].
351  kThumbCmpHL,       // cmp(3)  [01000110] H12[10] rm[5..3] rd[2..0].
352  kThumbCmpHH,       // cmp(3)  [01000111] H12[11] rm[5..3] rd[2..0].
353  kThumbEorRR,       // eor   [0100000001] rm[5..3] rd[2..0].
354  kThumbLdmia,       // ldmia   [11001] rn[10..8] reglist [7..0].
355  kThumbLdrRRI5,     // ldr(1)  [01101] imm_5[10..6] rn[5..3] rd[2..0].
356  kThumbLdrRRR,      // ldr(2)  [0101100] rm[8..6] rn[5..3] rd[2..0].
357  kThumbLdrPcRel,    // ldr(3)  [01001] rd[10..8] imm_8[7..0].
358  kThumbLdrSpRel,    // ldr(4)  [10011] rd[10..8] imm_8[7..0].
359  kThumbLdrbRRI5,    // ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0].
360  kThumbLdrbRRR,     // ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0].
361  kThumbLdrhRRI5,    // ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0].
362  kThumbLdrhRRR,     // ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0].
363  kThumbLdrsbRRR,    // ldrsb   [0101011] rm[8..6] rn[5..3] rd[2..0].
364  kThumbLdrshRRR,    // ldrsh   [0101111] rm[8..6] rn[5..3] rd[2..0].
365  kThumbLslRRI5,     // lsl(1)  [00000] imm_5[10..6] rm[5..3] rd[2..0].
366  kThumbLslRR,       // lsl(2)  [0100000010] rs[5..3] rd[2..0].
367  kThumbLsrRRI5,     // lsr(1)  [00001] imm_5[10..6] rm[5..3] rd[2..0].
368  kThumbLsrRR,       // lsr(2)  [0100000011] rs[5..3] rd[2..0].
369  kThumbMovImm,      // mov(1)  [00100] rd[10..8] imm_8[7..0].
370  kThumbMovRR,       // mov(2)  [0001110000] rn[5..3] rd[2..0].
371  kThumbMovRR_H2H,   // mov(3)  [01000111] H12[11] rm[5..3] rd[2..0].
372  kThumbMovRR_H2L,   // mov(3)  [01000110] H12[01] rm[5..3] rd[2..0].
373  kThumbMovRR_L2H,   // mov(3)  [01000101] H12[10] rm[5..3] rd[2..0].
374  kThumbMul,         // mul   [0100001101] rm[5..3] rd[2..0].
375  kThumbMvn,         // mvn   [0100001111] rm[5..3] rd[2..0].
376  kThumbNeg,         // neg   [0100001001] rm[5..3] rd[2..0].
377  kThumbOrr,         // orr   [0100001100] rm[5..3] rd[2..0].
378  kThumbPop,         // pop   [1011110] r[8..8] rl[7..0].
379  kThumbPush,        // push  [1011010] r[8..8] rl[7..0].
380  kThumbRev,         // rev   [1011101000] rm[5..3] rd[2..0]
381  kThumbRevsh,       // revsh   [1011101011] rm[5..3] rd[2..0]
382  kThumbRorRR,       // ror   [0100000111] rs[5..3] rd[2..0].
383  kThumbSbc,         // sbc   [0100000110] rm[5..3] rd[2..0].
384  kThumbStmia,       // stmia   [11000] rn[10..8] reglist [7.. 0].
385  kThumbStrRRI5,     // str(1)  [01100] imm_5[10..6] rn[5..3] rd[2..0].
386  kThumbStrRRR,      // str(2)  [0101000] rm[8..6] rn[5..3] rd[2..0].
387  kThumbStrSpRel,    // str(3)  [10010] rd[10..8] imm_8[7..0].
388  kThumbStrbRRI5,    // strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0].
389  kThumbStrbRRR,     // strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0].
390  kThumbStrhRRI5,    // strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0].
391  kThumbStrhRRR,     // strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0].
392  kThumbSubRRI3,     // sub(1)  [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
393  kThumbSubRI8,      // sub(2)  [00111] rd[10..8] imm_8[7..0].
394  kThumbSubRRR,      // sub(3)  [0001101] rm[8..6] rn[5..3] rd[2..0].
395  kThumbSubSpI7,     // sub(4)  [101100001] imm_7[6..0].
396  kThumbSwi,         // swi   [11011111] imm_8[7..0].
397  kThumbTst,         // tst   [0100001000] rm[5..3] rn[2..0].
398  kThumb2Vldrs,      // vldr low  sx [111011011001] rn[19..16] rd[15-12] [1010] imm_8[7..0].
399  kThumb2Vldrd,      // vldr low  dx [111011011001] rn[19..16] rd[15-12] [1011] imm_8[7..0].
400  kThumb2Vmuls,      // vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10100000] rm[3..0].
401  kThumb2Vmuld,      // vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10110000] rm[3..0].
402  kThumb2Vstrs,      // vstr low  sx [111011011000] rn[19..16] rd[15-12] [1010] imm_8[7..0].
403  kThumb2Vstrd,      // vstr low  dx [111011011000] rn[19..16] rd[15-12] [1011] imm_8[7..0].
404  kThumb2Vsubs,      // vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100040] rm[3..0].
405  kThumb2Vsubd,      // vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110040] rm[3..0].
406  kThumb2Vadds,      // vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100000] rm[3..0].
407  kThumb2Vaddd,      // vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110000] rm[3..0].
408  kThumb2Vdivs,      // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10100000] rm[3..0].
409  kThumb2Vdivd,      // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10110000] rm[3..0].
410  kThumb2VmlaF64,    // vmla.F64 vd, vn, vm [111011100000] vn[19..16] vd[15..12] [10110000] vm[3..0].
411  kThumb2VcvtIF,     // vcvt.F32.S32 vd, vm [1110111010111000] vd[15..12] [10101100] vm[3..0].
412  kThumb2VcvtFI,     // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10101100] vm[3..0].
413  kThumb2VcvtDI,     // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10111100] vm[3..0].
414  kThumb2VcvtFd,     // vcvt.F64.F32 vd, vm [1110111010110111] vd[15..12] [10101100] vm[3..0].
415  kThumb2VcvtDF,     // vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12] [10111100] vm[3..0].
416  kThumb2VcvtF64S32,  // vcvt.F64.S32 vd, vm [1110111010111000] vd[15..12] [10111100] vm[3..0].
417  kThumb2VcvtF64U32,  // vcvt.F64.U32 vd, vm [1110111010111000] vd[15..12] [10110100] vm[3..0].
418  kThumb2Vsqrts,     // vsqrt.f32 vd, vm [1110111010110001] vd[15..12] [10101100] vm[3..0].
419  kThumb2Vsqrtd,     // vsqrt.f64 vd, vm [1110111010110001] vd[15..12] [10111100] vm[3..0].
420  kThumb2MovI8M,     // mov(T2) rd, #<const> [11110] i [00001001111] imm3 rd[11..8] imm8.
421  kThumb2MovImm16,   // mov(T3) rd, #<const> [11110] i [0010100] imm4 [0] imm3 rd[11..8] imm8.
422  kThumb2StrRRI12,   // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
423  kThumb2LdrRRI12,   // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
424  kThumb2StrRRI8Predec,  // str(Imm,T4) rd,[rn,#-imm8] [111110000100] rn[19..16] rt[15..12] [1100] imm[7..0].
425  kThumb2LdrRRI8Predec,  // ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] rn[19..16] rt[15..12] [1100] imm[7..0].
426  kThumb2Cbnz,       // cbnz rd,<label> [101110] i [1] imm5[7..3] rn[2..0].
427  kThumb2Cbz,        // cbn rd,<label> [101100] i [1] imm5[7..3] rn[2..0].
428  kThumb2AddRRI12,   // add rd, rn, #imm12 [11110] i [100000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
429  kThumb2MovRR,      // mov rd, rm [11101010010011110000] rd[11..8] [0000] rm[3..0].
430  kThumb2Vmovs,      // vmov.f32 vd, vm [111011101] D [110000] vd[15..12] 101001] M [0] vm[3..0].
431  kThumb2Vmovd,      // vmov.f64 vd, vm [111011101] D [110000] vd[15..12] 101101] M [0] vm[3..0].
432  kThumb2Ldmia,      // ldmia  [111010001001] rn[19..16] mask[15..0].
433  kThumb2Stmia,      // stmia  [111010001000] rn[19..16] mask[15..0].
434  kThumb2AddRRR,     // add [111010110000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
435  kThumb2SubRRR,     // sub [111010111010] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
436  kThumb2SbcRRR,     // sbc [111010110110] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
437  kThumb2CmpRR,      // cmp [111010111011] rn[19..16] [0000] [1111] [0000] rm[3..0].
438  kThumb2SubRRI12,   // sub rd, rn, #imm12 [11110] i [101010] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
439  kThumb2MvnI8M,     // mov(T2) rd, #<const> [11110] i [00011011110] imm3 rd[11..8] imm8.
440  kThumb2Sel,        // sel rd, rn, rm [111110101010] rn[19-16] rd[11-8] rm[3-0].
441  kThumb2Ubfx,       // ubfx rd,rn,#lsb,#width [111100111100] rn[19..16] [0] imm3[14-12] rd[11-8] w[4-0].
442  kThumb2Sbfx,       // ubfx rd,rn,#lsb,#width [111100110100] rn[19..16] [0] imm3[14-12] rd[11-8] w[4-0].
443  kThumb2LdrRRR,     // ldr rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
444  kThumb2LdrhRRR,    // ldrh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
445  kThumb2LdrshRRR,   // ldrsh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
446  kThumb2LdrbRRR,    // ldrb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
447  kThumb2LdrsbRRR,   // ldrsb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
448  kThumb2StrRRR,     // str rt,[rn,rm,LSL #imm] [111110000100] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
449  kThumb2StrhRRR,    // str rt,[rn,rm,LSL #imm] [111110000010] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
450  kThumb2StrbRRR,    // str rt,[rn,rm,LSL #imm] [111110000000] rn[19-16] rt[15-12] [000000] imm[5-4] rm[3-0].
451  kThumb2LdrhRRI12,  // ldrh rt,[rn,#imm12] [111110001011] rt[15..12] rn[19..16] imm12[11..0].
452  kThumb2LdrshRRI12,  // ldrsh rt,[rn,#imm12] [111110011011] rt[15..12] rn[19..16] imm12[11..0].
453  kThumb2LdrbRRI12,  // ldrb rt,[rn,#imm12] [111110001001] rt[15..12] rn[19..16] imm12[11..0].
454  kThumb2LdrsbRRI12,  // ldrsb rt,[rn,#imm12] [111110011001] rt[15..12] rn[19..16] imm12[11..0].
455  kThumb2StrhRRI12,  // strh rt,[rn,#imm12] [111110001010] rt[15..12] rn[19..16] imm12[11..0].
456  kThumb2StrbRRI12,  // strb rt,[rn,#imm12] [111110001000] rt[15..12] rn[19..16] imm12[11..0].
457  kThumb2Pop,        // pop   [1110100010111101] list[15-0]*/
458  kThumb2Push,       // push  [1110100100101101] list[15-0]*/
459  kThumb2CmpRI8M,    // cmp rn, #<const> [11110] i [011011] rn[19-16] [0] imm3 [1111] imm8[7..0].
460  kThumb2CmnRI8M,    // cmn rn, #<const> [11110] i [010001] rn[19-16] [0] imm3 [1111] imm8[7..0].
461  kThumb2AdcRRR,     // adc [111010110101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
462  kThumb2AndRRR,     // and [111010100000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
463  kThumb2BicRRR,     // bic [111010100010] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
464  kThumb2CmnRR,      // cmn [111010110001] rn[19..16] [0000] [1111] [0000] rm[3..0].
465  kThumb2EorRRR,     // eor [111010101000] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
466  kThumb2MulRRR,     // mul [111110110000] rn[19..16] [1111] rd[11..8] [0000] rm[3..0].
467  kThumb2SdivRRR,    // sdiv [111110111001] rn[19..16] [1111] rd[11..8] [1111] rm[3..0].
468  kThumb2UdivRRR,    // udiv [111110111011] rn[19..16] [1111] rd[11..8] [1111] rm[3..0].
469  kThumb2MnvRR,      // mvn [11101010011011110] rd[11-8] [0000] rm[3..0].
470  kThumb2RsubRRI8M,  // rsb rd, rn, #<const> [11110] i [011101] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
471  kThumb2NegRR,      // actually rsub rd, rn, #0.
472  kThumb2OrrRRR,     // orr [111010100100] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
473  kThumb2TstRR,      // tst [111010100001] rn[19..16] [0000] [1111] [0000] rm[3..0].
474  kThumb2LslRRR,     // lsl [111110100000] rn[19..16] [1111] rd[11..8] [0000] rm[3..0].
475  kThumb2LsrRRR,     // lsr [111110100010] rn[19..16] [1111] rd[11..8] [0000] rm[3..0].
476  kThumb2AsrRRR,     // asr [111110100100] rn[19..16] [1111] rd[11..8] [0000] rm[3..0].
477  kThumb2RorRRR,     // ror [111110100110] rn[19..16] [1111] rd[11..8] [0000] rm[3..0].
478  kThumb2LslRRI5,    // lsl [11101010010011110] imm[14.12] rd[11..8] [00] rm[3..0].
479  kThumb2LsrRRI5,    // lsr [11101010010011110] imm[14.12] rd[11..8] [01] rm[3..0].
480  kThumb2AsrRRI5,    // asr [11101010010011110] imm[14.12] rd[11..8] [10] rm[3..0].
481  kThumb2RorRRI5,    // ror [11101010010011110] imm[14.12] rd[11..8] [11] rm[3..0].
482  kThumb2BicRRI8M,   // bic rd, rn, #<const> [11110] i [000010] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
483  kThumb2AndRRI8M,   // and rd, rn, #<const> [11110] i [000000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
484  kThumb2OrrRRI8M,   // orr rd, rn, #<const> [11110] i [000100] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
485  kThumb2EorRRI8M,   // eor rd, rn, #<const> [11110] i [001000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
486  kThumb2AddRRI8M,   // add rd, rn, #<const> [11110] i [010001] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
487  kThumb2AdcRRI8M,   // adc rd, rn, #<const> [11110] i [010101] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
488  kThumb2SubRRI8M,   // sub rd, rn, #<const> [11110] i [011011] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
489  kThumb2SbcRRI8M,   // sub rd, rn, #<const> [11110] i [010111] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
490  kThumb2RevRR,      // rev [111110101001] rm[19..16] [1111] rd[11..8] 1000 rm[3..0]
491  kThumb2RevshRR,    // rev [111110101001] rm[19..16] [1111] rd[11..8] 1011 rm[3..0]
492  kThumb2It,         // it [10111111] firstcond[7-4] mask[3-0].
493  kThumb2Fmstat,     // fmstat [11101110111100011111101000010000].
494  kThumb2Vcmpd,      // vcmp [111011101] D [11011] rd[15-12] [1011] E [1] M [0] rm[3-0].
495  kThumb2Vcmps,      // vcmp [111011101] D [11010] rd[15-12] [1011] E [1] M [0] rm[3-0].
496  kThumb2LdrPcRel12,  // ldr rd,[pc,#imm12] [1111100011011111] rt[15-12] imm12[11-0].
497  kThumb2BCond,      // b<c> [1110] S cond[25-22] imm6[21-16] [10] J1 [0] J2 imm11[10..0].
498  kThumb2Fmrs,       // vmov [111011100000] vn[19-16] rt[15-12] [1010] N [0010000].
499  kThumb2Fmsr,       // vmov [111011100001] vn[19-16] rt[15-12] [1010] N [0010000].
500  kThumb2Fmrrd,      // vmov [111011000100] rt2[19-16] rt[15-12] [101100] M [1] vm[3-0].
501  kThumb2Fmdrr,      // vmov [111011000101] rt2[19-16] rt[15-12] [101100] M [1] vm[3-0].
502  kThumb2Vabsd,      // vabs.f64 [111011101] D [110000] rd[15-12] [1011110] M [0] vm[3-0].
503  kThumb2Vabss,      // vabs.f32 [111011101] D [110000] rd[15-12] [1010110] M [0] vm[3-0].
504  kThumb2Vnegd,      // vneg.f64 [111011101] D [110000] rd[15-12] [1011110] M [0] vm[3-0].
505  kThumb2Vnegs,      // vneg.f32 [111011101] D [110000] rd[15-12] [1010110] M [0] vm[3-0].
506  kThumb2Vmovs_IMM8,  // vmov.f32 [111011101] D [11] imm4h[19-16] vd[15-12] [10100000] imm4l[3-0].
507  kThumb2Vmovd_IMM8,  // vmov.f64 [111011101] D [11] imm4h[19-16] vd[15-12] [10110000] imm4l[3-0].
508  kThumb2Mla,        // mla [111110110000] rn[19-16] ra[15-12] rd[7-4] [0000] rm[3-0].
509  kThumb2Umull,      // umull [111110111010] rn[19-16], rdlo[15-12] rdhi[11-8] [0000] rm[3-0].
510  kThumb2Ldrex,      // ldrex [111010000101] rn[19-16] rt[15-12] [1111] imm8[7-0].
511  kThumb2Ldrexd,     // ldrexd [111010001101] rn[19-16] rt[15-12] rt2[11-8] [11111111].
512  kThumb2Strex,      // strex [111010000100] rn[19-16] rt[15-12] rd[11-8] imm8[7-0].
513  kThumb2Strexd,     // strexd [111010001100] rn[19-16] rt[15-12] rt2[11-8] [0111] Rd[3-0].
514  kThumb2Clrex,      // clrex [11110011101111111000111100101111].
515  kThumb2Bfi,        // bfi [111100110110] rn[19-16] [0] imm3[14-12] rd[11-8] imm2[7-6] [0] msb[4-0].
516  kThumb2Bfc,        // bfc [11110011011011110] [0] imm3[14-12] rd[11-8] imm2[7-6] [0] msb[4-0].
517  kThumb2Dmb,        // dmb [1111001110111111100011110101] option[3-0].
518  kThumb2LdrPcReln12,  // ldr rd,[pc,-#imm12] [1111100011011111] rt[15-12] imm12[11-0].
519  kThumb2Stm,        // stm <list> [111010010000] rn[19-16] 000 rl[12-0].
520  kThumbUndefined,   // undefined [11011110xxxxxxxx].
521  kThumb2VPopCS,     // vpop <list of callee save fp singles (s16+).
522  kThumb2VPushCS,    // vpush <list callee save fp singles (s16+).
523  kThumb2Vldms,      // vldms rd, <list>.
524  kThumb2Vstms,      // vstms rd, <list>.
525  kThumb2BUncond,    // b <label>.
526  kThumb2MovImm16H,  // similar to kThumb2MovImm16, but target high hw.
527  kThumb2AddPCR,     // Thumb2 2-operand add with hard-coded PC target.
528  kThumb2Adr,        // Special purpose encoding of ADR for switch tables.
529  kThumb2MovImm16LST,  // Special purpose version for switch table use.
530  kThumb2MovImm16HST,  // Special purpose version for switch table use.
531  kThumb2LdmiaWB,    // ldmia  [111010011001[ rn[19..16] mask[15..0].
532  kThumb2OrrRRRs,    // orrs [111010100101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
533  kThumb2Push1,      // t3 encoding of push.
534  kThumb2Pop1,       // t3 encoding of pop.
535  kThumb2RsubRRR,    // rsb [111010111101] rn[19..16] [0000] rd[11..8] [0000] rm[3..0].
536  kThumb2Smull,      // smull [111110111000] rn[19-16], rdlo[15-12] rdhi[11-8] [0000] rm[3-0].
537  kThumb2LdrdPcRel8,  // ldrd rt, rt2, pc +-/1024.
538  kThumb2LdrdI8,     // ldrd rt, rt2, [rn +-/1024].
539  kThumb2StrdI8,     // strd rt, rt2, [rn +-/1024].
540  kArmLast,
541};
542
543enum ArmOpDmbOptions {
544  kSY = 0xf,
545  kST = 0xe,
546  kISH = 0xb,
547  kISHST = 0xa,
548  kNSH = 0x7,
549  kNSHST = 0x6
550};
551
552// Instruction assembly field_loc kind.
553enum ArmEncodingKind {
554  kFmtUnused,    // Unused field and marks end of formats.
555  kFmtBitBlt,    // Bit string using end/start.
556  kFmtDfp,       // Double FP reg.
557  kFmtSfp,       // Single FP reg.
558  kFmtModImm,    // Shifted 8-bit immed using [26,14..12,7..0].
559  kFmtImm16,     // Zero-extended immed using [26,19..16,14..12,7..0].
560  kFmtImm6,      // Encoded branch target using [9,7..3]0.
561  kFmtImm12,     // Zero-extended immediate using [26,14..12,7..0].
562  kFmtShift,     // Shift descriptor, [14..12,7..4].
563  kFmtLsb,       // least significant bit using [14..12][7..6].
564  kFmtBWidth,    // bit-field width, encoded as width-1.
565  kFmtShift5,    // Shift count, [14..12,7..6].
566  kFmtBrOffset,  // Signed extended [26,11,13,21-16,10-0]:0.
567  kFmtFPImm,     // Encoded floating point immediate.
568  kFmtOff24,     // 24-bit Thumb2 unconditional branch encoding.
569  kFmtSkip,      // Unused field, but continue to next.
570};
571
572// Struct used to define the snippet positions for each Thumb opcode.
573struct ArmEncodingMap {
574  uint32_t skeleton;
575  struct {
576    ArmEncodingKind kind;
577    int end;   // end for kFmtBitBlt, 1-bit slice end for FP regs.
578    int start;  // start for kFmtBitBlt, 4-bit slice end for FP regs.
579  } field_loc[4];
580  ArmOpcode opcode;
581  uint64_t flags;
582  const char* name;
583  const char* fmt;
584  int size;   // Note: size is in bytes.
585  FixupKind fixup;
586};
587
588}  // namespace art
589
590#endif  // ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_
591