codegen_arm.h revision 2c1ed456dcdb027d097825dd98dbe48c71599b6c 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
19
20#include "arm_lir.h"
21#include "dex/compiler_internals.h"
22
23namespace art {
24
25class ArmMir2Lir : public Mir2Lir {
26  public:
27    ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                                    RegLocation rl_dest, int lit);
32    int LoadHelper(ThreadOffset offset);
33    LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34    LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35                          int s_reg);
36    LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37    LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
38                             int r_dest, int r_dest_hi, OpSize size, int s_reg);
39    LIR* LoadConstantNoClobber(int r_dest, int value);
40    LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value);
41    LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42    LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43    LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44    LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
45                              int r_src, int r_src_hi, OpSize size, int s_reg);
46    void MarkGCCard(int val_reg, int tgt_addr_reg);
47
48    // Required for target - register utilities.
49    bool IsFpReg(int reg);
50    bool SameRegType(int reg1, int reg2);
51    int AllocTypedTemp(bool fp_hint, int reg_class);
52    RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);
53    int S2d(int low_reg, int high_reg);
54    int TargetReg(SpecialTargetRegister reg);
55    int GetArgMappingToPhysicalReg(int arg_num);
56    RegLocation GetReturnAlt();
57    RegLocation GetReturnWideAlt();
58    RegLocation LocCReturn();
59    RegLocation LocCReturnDouble();
60    RegLocation LocCReturnFloat();
61    RegLocation LocCReturnWide();
62    uint32_t FpRegMask();
63    uint64_t GetRegMaskCommon(int reg);
64    void AdjustSpillMask();
65    void ClobberCallerSave();
66    void FlushReg(int reg);
67    void FlushRegWide(int reg1, int reg2);
68    void FreeCallTemps();
69    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
70    void LockCallTemps();
71    void MarkPreservedSingle(int v_reg, int reg);
72    void CompilerInitializeRegAlloc();
73
74    // Required for target - miscellaneous.
75    void AssembleLIR();
76    uint32_t EncodeRange(LIR* head_lir, LIR* tail_lir, uint32_t starting_offset);
77    int AssignInsnOffsets();
78    void AssignOffsets();
79    void EncodeLIR(LIR* lir);
80    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
81    void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
82    const char* GetTargetInstFmt(int opcode);
83    const char* GetTargetInstName(int opcode);
84    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
85    uint64_t GetPCUseDefEncoding();
86    uint64_t GetTargetInstFlags(int opcode);
87    int GetInsnSize(LIR* lir);
88    bool IsUnconditionalBranch(LIR* lir);
89
90    // Required for target - Dalvik-level generators.
91    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
92                           RegLocation rl_src1, RegLocation rl_src2);
93    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
94                     RegLocation rl_index, RegLocation rl_dest, int scale);
95    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
96                     RegLocation rl_src, int scale, bool card_mark);
97    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
98                           RegLocation rl_src1, RegLocation rl_shift);
99    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
100    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
101    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
102    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest,
103                          RegLocation rl_src1, RegLocation rl_src2);
104    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
105                         RegLocation rl_src1, RegLocation rl_src2);
106    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                  RegLocation rl_src2);
108    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
109    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
110    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
111    bool GenInlinedSqrt(CallInfo* info);
112    bool GenInlinedPeek(CallInfo* info, OpSize size);
113    bool GenInlinedPoke(CallInfo* info, OpSize size);
114    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
115    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
116    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
117    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
118    LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset,
119                                ThrowKind kind);
120    RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div);
121    RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div);
122    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
123    void GenDivZeroCheck(int reg_lo, int reg_hi);
124    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
125    void GenExitSequence();
126    void GenSpecialExitSequence();
127    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
128    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
129    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
130    void GenSelect(BasicBlock* bb, MIR* mir);
131    void GenMemBarrier(MemBarrierKind barrier_kind);
132    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
133    void GenMonitorExit(int opt_flags, RegLocation rl_src);
134    void GenMoveException(RegLocation rl_dest);
135    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
136                                               int first_bit, int second_bit);
137    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
138    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
139    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
140    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
141
142    // Required for target - single operation generators.
143    LIR* OpUnconditionalBranch(LIR* target);
144    LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target);
145    LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target);
146    LIR* OpCondBranch(ConditionCode cc, LIR* target);
147    LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target);
148    LIR* OpFpRegCopy(int r_dest, int r_src);
149    LIR* OpIT(ConditionCode cond, const char* guide);
150    LIR* OpMem(OpKind op, int rBase, int disp);
151    LIR* OpPcRelLoad(int reg, LIR* target);
152    LIR* OpReg(OpKind op, int r_dest_src);
153    LIR* OpRegCopy(int r_dest, int r_src);
154    LIR* OpRegCopyNoInsert(int r_dest, int r_src);
155    LIR* OpRegImm(OpKind op, int r_dest_src1, int value);
156    LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset);
157    LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2);
158    LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type);
159    LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type);
160    LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src);
161    LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value);
162    LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2);
163    LIR* OpTestSuspend(LIR* target);
164    LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
165    LIR* OpVldm(int rBase, int count);
166    LIR* OpVstm(int rBase, int count);
167    void OpLea(int rBase, int reg1, int reg2, int scale, int offset);
168    void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi);
169    void OpTlsCmp(ThreadOffset offset, int val);
170
171    LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
172                          int s_reg);
173    LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
174    LIR* OpRegRegRegShift(OpKind op, int r_dest, int r_src1, int r_src2, int shift);
175    LIR* OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, int shift);
176    static const ArmEncodingMap EncodingMap[kArmLast];
177    int EncodeShift(int code, int amount);
178    int ModifiedImmediate(uint32_t value);
179    ArmConditionCode ArmConditionEncoding(ConditionCode code);
180    bool InexpensiveConstantInt(int32_t value);
181    bool InexpensiveConstantFloat(int32_t value);
182    bool InexpensiveConstantLong(int64_t value);
183    bool InexpensiveConstantDouble(int64_t value);
184
185  private:
186    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
187                                  ConditionCode ccode);
188    LIR* LoadFPConstantValue(int r_dest, int value);
189    void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
190    void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
191    void AssignDataOffsets();
192    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
193                          RegLocation rl_src2, bool is_div, bool check_zero);
194    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
195};
196
197}  // namespace art
198
199#endif  // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
200