codegen_arm.h revision 306f017dd883c0bf806d239d97e0bca3194afbd7 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
19
20#include "arm_lir.h"
21#include "dex/compiler_internals.h"
22
23namespace art {
24
25class ArmMir2Lir : public Mir2Lir {
26  public:
27    ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    LIR* CheckSuspendUsingLoad() OVERRIDE;
33    RegStorage LoadHelper(ThreadOffset offset);
34    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
35                      int s_reg);
36    LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg);
37    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
38                         OpSize size);
39    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
40                             RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg);
41    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
42    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
43    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
44    LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src);
45    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
46                          OpSize size);
47    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
48                              RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg);
49    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
50
51    // Required for target - register utilities.
52    bool IsFpReg(int reg);
53    bool IsFpReg(RegStorage reg);
54    bool SameRegType(int reg1, int reg2);
55    RegStorage AllocTypedTemp(bool fp_hint, int reg_class);
56    RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);
57    int S2d(int low_reg, int high_reg);
58    RegStorage TargetReg(SpecialTargetRegister reg);
59    RegStorage GetArgMappingToPhysicalReg(int arg_num);
60    RegLocation GetReturnAlt();
61    RegLocation GetReturnWideAlt();
62    RegLocation LocCReturn();
63    RegLocation LocCReturnDouble();
64    RegLocation LocCReturnFloat();
65    RegLocation LocCReturnWide();
66    uint32_t FpRegMask();
67    uint64_t GetRegMaskCommon(int reg);
68    void AdjustSpillMask();
69    void ClobberCallerSave();
70    void FlushReg(RegStorage reg);
71    void FlushRegWide(RegStorage reg);
72    void FreeCallTemps();
73    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
74    void LockCallTemps();
75    void MarkPreservedSingle(int v_reg, int reg);
76    void CompilerInitializeRegAlloc();
77
78    // Required for target - miscellaneous.
79    void AssembleLIR();
80    uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
81    int AssignInsnOffsets();
82    void AssignOffsets();
83    static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
84    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
85    void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
86    const char* GetTargetInstFmt(int opcode);
87    const char* GetTargetInstName(int opcode);
88    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
89    uint64_t GetPCUseDefEncoding();
90    uint64_t GetTargetInstFlags(int opcode);
91    int GetInsnSize(LIR* lir);
92    bool IsUnconditionalBranch(LIR* lir);
93
94    // Required for target - Dalvik-level generators.
95    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
96                           RegLocation rl_src1, RegLocation rl_src2);
97    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
98                     RegLocation rl_index, RegLocation rl_dest, int scale);
99    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
100                     RegLocation rl_src, int scale, bool card_mark);
101    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
102                           RegLocation rl_src1, RegLocation rl_shift);
103    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
104                    RegLocation rl_src2);
105    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106                    RegLocation rl_src2);
107    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
108                    RegLocation rl_src2);
109    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
110                          RegLocation rl_src2);
111    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
112                         RegLocation rl_src2);
113    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
114                  RegLocation rl_src2);
115    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
116    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
117    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
118    bool GenInlinedSqrt(CallInfo* info);
119    bool GenInlinedPeek(CallInfo* info, OpSize size);
120    bool GenInlinedPoke(CallInfo* info, OpSize size);
121    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
122    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
123                   RegLocation rl_src2);
124    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
125                    RegLocation rl_src2);
126    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
127                    RegLocation rl_src2);
128    LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset,
129                        ThrowKind kind);
130    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
131    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
132    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
133    void GenDivZeroCheck(RegStorage reg);
134    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
135    void GenExitSequence();
136    void GenSpecialExitSequence();
137    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
138    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
139    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
140    void GenSelect(BasicBlock* bb, MIR* mir);
141    void GenMemBarrier(MemBarrierKind barrier_kind);
142    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
143    void GenMonitorExit(int opt_flags, RegLocation rl_src);
144    void GenMoveException(RegLocation rl_dest);
145    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
146                                       int first_bit, int second_bit);
147    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
148    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
149    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
150    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
151
152    // Required for target - single operation generators.
153    LIR* OpUnconditionalBranch(LIR* target);
154    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
155    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
156    LIR* OpCondBranch(ConditionCode cc, LIR* target);
157    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
158    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
159    LIR* OpIT(ConditionCode cond, const char* guide);
160    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
161    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
162    LIR* OpReg(OpKind op, RegStorage r_dest_src);
163    LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src);
164    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
165    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
166    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
167    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
168    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
169    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
170    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
171    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
172    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
173    LIR* OpTestSuspend(LIR* target);
174    LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset);
175    LIR* OpVldm(RegStorage r_base, int count);
176    LIR* OpVstm(RegStorage r_base, int count);
177    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
178    void OpRegCopyWide(RegStorage dest, RegStorage src);
179    void OpTlsCmp(ThreadOffset offset, int val);
180
181    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
182                          int s_reg);
183    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
184    LIR* OpRegRegRegShift(OpKind op, int r_dest, int r_src1, int r_src2, int shift);
185    LIR* OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, int shift);
186    static const ArmEncodingMap EncodingMap[kArmLast];
187    int EncodeShift(int code, int amount);
188    int ModifiedImmediate(uint32_t value);
189    ArmConditionCode ArmConditionEncoding(ConditionCode code);
190    bool InexpensiveConstantInt(int32_t value);
191    bool InexpensiveConstantFloat(int32_t value);
192    bool InexpensiveConstantLong(int64_t value);
193    bool InexpensiveConstantDouble(int64_t value);
194
195  private:
196    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
197                                  ConditionCode ccode);
198    LIR* LoadFPConstantValue(int r_dest, int value);
199    void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
200    void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
201    void AssignDataOffsets();
202    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
203                          bool is_div, bool check_zero);
204    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
205};
206
207}  // namespace art
208
209#endif  // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
210