codegen_arm.h revision de68676b24f61a55adc0b22fe828f036a5925c41 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
18#define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
19
20#include "arm_lir.h"
21#include "dex/compiler_internals.h"
22
23namespace art {
24
25class ArmMir2Lir FINAL : public Mir2Lir {
26  public:
27    ArmMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen helpers.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE;
35    RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE;
36    LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest,
37                              OpSize size) OVERRIDE;
38    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
39                      OpSize size) OVERRIDE;
40    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
41                         OpSize size) OVERRIDE;
42    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
43                             RegStorage r_dest, OpSize size) OVERRIDE;
44    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
45    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
46    LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src,
47                               OpSize size) OVERRIDE;
48    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
49                       OpSize size) OVERRIDE;
50    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
51                          OpSize size) OVERRIDE;
52    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
53                              RegStorage r_src, OpSize size) OVERRIDE;
54    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
55
56    // Required for target - register utilities.
57    RegStorage TargetReg(SpecialTargetRegister reg);
58    RegStorage GetArgMappingToPhysicalReg(int arg_num);
59    RegLocation GetReturnAlt();
60    RegLocation GetReturnWideAlt();
61    RegLocation LocCReturn();
62    RegLocation LocCReturnRef();
63    RegLocation LocCReturnDouble();
64    RegLocation LocCReturnFloat();
65    RegLocation LocCReturnWide();
66    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
67    void AdjustSpillMask();
68    void ClobberCallerSave();
69    void FreeCallTemps();
70    void LockCallTemps();
71    void MarkPreservedSingle(int v_reg, RegStorage reg);
72    void MarkPreservedDouble(int v_reg, RegStorage reg);
73    void CompilerInitializeRegAlloc();
74    RegStorage AllocPreservedDouble(int s_reg);
75
76    // Required for target - miscellaneous.
77    void AssembleLIR();
78    uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset);
79    int AssignInsnOffsets();
80    void AssignOffsets();
81    static uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir);
82    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
83    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
84                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
85    const char* GetTargetInstFmt(int opcode);
86    const char* GetTargetInstName(int opcode);
87    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
88    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
89    uint64_t GetTargetInstFlags(int opcode);
90    size_t GetInsnSize(LIR* lir) OVERRIDE;
91    bool IsUnconditionalBranch(LIR* lir);
92
93    // Check support for volatile load/store of a given size.
94    bool SupportsVolatileLoadStore(OpSize size) OVERRIDE;
95    // Get the register class for load/store of a field.
96    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
97
98    // Required for target - Dalvik-level generators.
99    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
100                           RegLocation rl_src1, RegLocation rl_src2);
101    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
102                     RegLocation rl_index, RegLocation rl_dest, int scale);
103    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index,
104                     RegLocation rl_src, int scale, bool card_mark);
105    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
106                           RegLocation rl_src1, RegLocation rl_shift);
107    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
108                    RegLocation rl_src2);
109    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
110                    RegLocation rl_src2);
111    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
112                    RegLocation rl_src2);
113    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
114                          RegLocation rl_src2);
115    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
116                         RegLocation rl_src2);
117    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
118                  RegLocation rl_src2);
119    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
120    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
121    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
122    bool GenInlinedSqrt(CallInfo* info);
123    bool GenInlinedPeek(CallInfo* info, OpSize size);
124    bool GenInlinedPoke(CallInfo* info, OpSize size);
125    void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
126    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
127    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
128                   RegLocation rl_src2);
129    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
130                    RegLocation rl_src2);
131    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
132                    RegLocation rl_src2);
133    void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
134                       RegLocation rl_src2, bool is_div);
135    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
136    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
137    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
138    void GenDivZeroCheckWide(RegStorage reg);
139    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
140    void GenExitSequence();
141    void GenSpecialExitSequence();
142    void GenFillArrayData(DexOffset table_offset, RegLocation rl_src);
143    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
144    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
145    void GenSelect(BasicBlock* bb, MIR* mir);
146    bool GenMemBarrier(MemBarrierKind barrier_kind);
147    void GenMonitorEnter(int opt_flags, RegLocation rl_src);
148    void GenMonitorExit(int opt_flags, RegLocation rl_src);
149    void GenMoveException(RegLocation rl_dest);
150    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
151                                       int first_bit, int second_bit);
152    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
153    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
154    void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
155    void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
156
157    // Required for target - single operation generators.
158    LIR* OpUnconditionalBranch(LIR* target);
159    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
160    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
161    LIR* OpCondBranch(ConditionCode cc, LIR* target);
162    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
163    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
164    LIR* OpIT(ConditionCode cond, const char* guide);
165    void UpdateIT(LIR* it, const char* new_guide);
166    void OpEndIT(LIR* it);
167    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
168    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
169    LIR* OpReg(OpKind op, RegStorage r_dest_src);
170    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
171    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
172    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
173    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
174    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
175    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
176    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
177    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
178    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
179    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
180    LIR* OpTestSuspend(LIR* target);
181    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE;
182    LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE;
183    LIR* OpVldm(RegStorage r_base, int count);
184    LIR* OpVstm(RegStorage r_base, int count);
185    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
186    void OpRegCopyWide(RegStorage dest, RegStorage src);
187    void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE;
188    void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE;
189
190    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
191    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
192    LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
193                          int shift);
194    LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
195    static const ArmEncodingMap EncodingMap[kArmLast];
196    int EncodeShift(int code, int amount);
197    int ModifiedImmediate(uint32_t value);
198    ArmConditionCode ArmConditionEncoding(ConditionCode code);
199    bool InexpensiveConstantInt(int32_t value);
200    bool InexpensiveConstantFloat(int32_t value);
201    bool InexpensiveConstantLong(int64_t value);
202    bool InexpensiveConstantDouble(int64_t value);
203
204  private:
205    void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, int64_t val,
206                                  ConditionCode ccode);
207    LIR* LoadFPConstantValue(int r_dest, int value);
208    LIR* LoadStoreUsingInsnWithOffsetImm8Shl2(ArmOpcode opcode, RegStorage r_base,
209                                              int displacement, RegStorage r_src_dest,
210                                              RegStorage r_work = RegStorage::InvalidReg());
211    void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
212    void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir);
213    void AssignDataOffsets();
214    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
215                          bool is_div, bool check_zero);
216    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
217    typedef struct {
218      OpKind op;
219      uint32_t shift;
220    } EasyMultiplyOp;
221    bool GetEasyMultiplyOp(int lit, EasyMultiplyOp* op);
222    bool GetEasyMultiplyTwoOps(int lit, EasyMultiplyOp* ops);
223    void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
224
225    static constexpr ResourceMask GetRegMaskArm(RegStorage reg);
226    static constexpr ResourceMask EncodeArmRegList(int reg_list);
227    static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
228};
229
230}  // namespace art
231
232#endif  // ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_
233