utility_arm.cc revision 0f6784737882199197796b67b99e5f1ded383bee
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "arm_lir.h" 18#include "codegen_arm.h" 19#include "dex/quick/mir_to_lir-inl.h" 20 21namespace art { 22 23/* This file contains codegen for the Thumb ISA. */ 24 25static int32_t EncodeImmSingle(int32_t value) { 26 int32_t res; 27 int32_t bit_a = (value & 0x80000000) >> 31; 28 int32_t not_bit_b = (value & 0x40000000) >> 30; 29 int32_t bit_b = (value & 0x20000000) >> 29; 30 int32_t b_smear = (value & 0x3e000000) >> 25; 31 int32_t slice = (value & 0x01f80000) >> 19; 32 int32_t zeroes = (value & 0x0007ffff); 33 if (zeroes != 0) 34 return -1; 35 if (bit_b) { 36 if ((not_bit_b != 0) || (b_smear != 0x1f)) 37 return -1; 38 } else { 39 if ((not_bit_b != 1) || (b_smear != 0x0)) 40 return -1; 41 } 42 res = (bit_a << 7) | (bit_b << 6) | slice; 43 return res; 44} 45 46/* 47 * Determine whether value can be encoded as a Thumb2 floating point 48 * immediate. If not, return -1. If so return encoded 8-bit value. 49 */ 50static int32_t EncodeImmDouble(int64_t value) { 51 int32_t res; 52 int32_t bit_a = (value & INT64_C(0x8000000000000000)) >> 63; 53 int32_t not_bit_b = (value & INT64_C(0x4000000000000000)) >> 62; 54 int32_t bit_b = (value & INT64_C(0x2000000000000000)) >> 61; 55 int32_t b_smear = (value & INT64_C(0x3fc0000000000000)) >> 54; 56 int32_t slice = (value & INT64_C(0x003f000000000000)) >> 48; 57 uint64_t zeroes = (value & INT64_C(0x0000ffffffffffff)); 58 if (zeroes != 0ull) 59 return -1; 60 if (bit_b) { 61 if ((not_bit_b != 0) || (b_smear != 0xff)) 62 return -1; 63 } else { 64 if ((not_bit_b != 1) || (b_smear != 0x0)) 65 return -1; 66 } 67 res = (bit_a << 7) | (bit_b << 6) | slice; 68 return res; 69} 70 71LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { 72 DCHECK(ARM_SINGLEREG(r_dest)); 73 if (value == 0) { 74 // TODO: we need better info about the target CPU. a vector exclusive or 75 // would probably be better here if we could rely on its existance. 76 // Load an immediate +2.0 (which encodes to 0) 77 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0); 78 // +0.0 = +2.0 - +2.0 79 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest); 80 } else { 81 int encoded_imm = EncodeImmSingle(value); 82 if (encoded_imm >= 0) { 83 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm); 84 } 85 } 86 LIR* data_target = ScanLiteralPool(literal_list_, value, 0); 87 if (data_target == NULL) { 88 data_target = AddWordData(&literal_list_, value); 89 } 90 LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs, 91 r_dest, r15pc, 0, 0, 0, data_target); 92 SetMemRefType(load_pc_rel, true, kLiteral); 93 AppendLIR(load_pc_rel); 94 return load_pc_rel; 95} 96 97static int LeadingZeros(uint32_t val) { 98 uint32_t alt; 99 int32_t n; 100 int32_t count; 101 102 count = 16; 103 n = 32; 104 do { 105 alt = val >> count; 106 if (alt != 0) { 107 n = n - count; 108 val = alt; 109 } 110 count >>= 1; 111 } while (count); 112 return n - val; 113} 114 115/* 116 * Determine whether value can be encoded as a Thumb2 modified 117 * immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form. 118 */ 119int ArmMir2Lir::ModifiedImmediate(uint32_t value) { 120 int32_t z_leading; 121 int32_t z_trailing; 122 uint32_t b0 = value & 0xff; 123 124 /* Note: case of value==0 must use 0:000:0:0000000 encoding */ 125 if (value <= 0xFF) 126 return b0; // 0:000:a:bcdefgh 127 if (value == ((b0 << 16) | b0)) 128 return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */ 129 if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0)) 130 return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */ 131 b0 = (value >> 8) & 0xff; 132 if (value == ((b0 << 24) | (b0 << 8))) 133 return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */ 134 /* Can we do it with rotation? */ 135 z_leading = LeadingZeros(value); 136 z_trailing = 32 - LeadingZeros(~value & (value - 1)); 137 /* A run of eight or fewer active bits? */ 138 if ((z_leading + z_trailing) < 24) 139 return -1; /* No - bail */ 140 /* left-justify the constant, discarding msb (known to be 1) */ 141 value <<= z_leading + 1; 142 /* Create bcdefgh */ 143 value >>= 25; 144 /* Put it all together */ 145 return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */ 146} 147 148bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { 149 return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); 150} 151 152bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { 153 return EncodeImmSingle(value) >= 0; 154} 155 156bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { 157 return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); 158} 159 160bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { 161 return EncodeImmDouble(value) >= 0; 162} 163 164/* 165 * Load a immediate using a shortcut if possible; otherwise 166 * grab from the per-translation literal pool. 167 * 168 * No additional register clobbering operation performed. Use this version when 169 * 1) r_dest is freshly returned from AllocTemp or 170 * 2) The codegen is under fixed register usage 171 */ 172LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) { 173 LIR* res; 174 int mod_imm; 175 176 if (ARM_FPREG(r_dest)) { 177 return LoadFPConstantValue(r_dest, value); 178 } 179 180 /* See if the value can be constructed cheaply */ 181 if (ARM_LOWREG(r_dest) && (value >= 0) && (value <= 255)) { 182 return NewLIR2(kThumbMovImm, r_dest, value); 183 } 184 /* Check Modified immediate special cases */ 185 mod_imm = ModifiedImmediate(value); 186 if (mod_imm >= 0) { 187 res = NewLIR2(kThumb2MovI8M, r_dest, mod_imm); 188 return res; 189 } 190 mod_imm = ModifiedImmediate(~value); 191 if (mod_imm >= 0) { 192 res = NewLIR2(kThumb2MvnI8M, r_dest, mod_imm); 193 return res; 194 } 195 /* 16-bit immediate? */ 196 if ((value & 0xffff) == value) { 197 res = NewLIR2(kThumb2MovImm16, r_dest, value); 198 return res; 199 } 200 /* Do a low/high pair */ 201 res = NewLIR2(kThumb2MovImm16, r_dest, Low16Bits(value)); 202 NewLIR2(kThumb2MovImm16H, r_dest, High16Bits(value)); 203 return res; 204} 205 206LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { 207 LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly*/); 208 res->target = target; 209 return res; 210} 211 212LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 213 // This is kThumb2BCond instead of kThumbBCond for performance reasons. The assembly 214 // time required for a new pass after kThumbBCond is fixed up to kThumb2BCond is 215 // substantial. 216 LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */, 217 ArmConditionEncoding(cc)); 218 branch->target = target; 219 return branch; 220} 221 222LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) { 223 ArmOpcode opcode = kThumbBkpt; 224 switch (op) { 225 case kOpBlx: 226 opcode = kThumbBlxR; 227 break; 228 default: 229 LOG(FATAL) << "Bad opcode " << op; 230 } 231 return NewLIR1(opcode, r_dest_src); 232} 233 234LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, 235 int shift) { 236 bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)); 237 ArmOpcode opcode = kThumbBkpt; 238 switch (op) { 239 case kOpAdc: 240 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 241 break; 242 case kOpAnd: 243 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; 244 break; 245 case kOpBic: 246 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; 247 break; 248 case kOpCmn: 249 DCHECK_EQ(shift, 0); 250 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR; 251 break; 252 case kOpCmp: 253 if (thumb_form) 254 opcode = kThumbCmpRR; 255 else if ((shift == 0) && !ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 256 opcode = kThumbCmpHH; 257 else if ((shift == 0) && ARM_LOWREG(r_dest_src1)) 258 opcode = kThumbCmpLH; 259 else if (shift == 0) 260 opcode = kThumbCmpHL; 261 else 262 opcode = kThumb2CmpRR; 263 break; 264 case kOpXor: 265 opcode = (thumb_form) ? kThumbEorRR : kThumb2EorRRR; 266 break; 267 case kOpMov: 268 DCHECK_EQ(shift, 0); 269 if (ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)) 270 opcode = kThumbMovRR; 271 else if (!ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 272 opcode = kThumbMovRR_H2H; 273 else if (ARM_LOWREG(r_dest_src1)) 274 opcode = kThumbMovRR_H2L; 275 else 276 opcode = kThumbMovRR_L2H; 277 break; 278 case kOpMul: 279 DCHECK_EQ(shift, 0); 280 opcode = (thumb_form) ? kThumbMul : kThumb2MulRRR; 281 break; 282 case kOpMvn: 283 opcode = (thumb_form) ? kThumbMvn : kThumb2MnvRR; 284 break; 285 case kOpNeg: 286 DCHECK_EQ(shift, 0); 287 opcode = (thumb_form) ? kThumbNeg : kThumb2NegRR; 288 break; 289 case kOpOr: 290 opcode = (thumb_form) ? kThumbOrr : kThumb2OrrRRR; 291 break; 292 case kOpSbc: 293 opcode = (thumb_form) ? kThumbSbc : kThumb2SbcRRR; 294 break; 295 case kOpTst: 296 opcode = (thumb_form) ? kThumbTst : kThumb2TstRR; 297 break; 298 case kOpLsl: 299 DCHECK_EQ(shift, 0); 300 opcode = (thumb_form) ? kThumbLslRR : kThumb2LslRRR; 301 break; 302 case kOpLsr: 303 DCHECK_EQ(shift, 0); 304 opcode = (thumb_form) ? kThumbLsrRR : kThumb2LsrRRR; 305 break; 306 case kOpAsr: 307 DCHECK_EQ(shift, 0); 308 opcode = (thumb_form) ? kThumbAsrRR : kThumb2AsrRRR; 309 break; 310 case kOpRor: 311 DCHECK_EQ(shift, 0); 312 opcode = (thumb_form) ? kThumbRorRR : kThumb2RorRRR; 313 break; 314 case kOpAdd: 315 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 316 break; 317 case kOpSub: 318 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 319 break; 320 case kOpRev: 321 DCHECK_EQ(shift, 0); 322 if (!thumb_form) { 323 // Binary, but rm is encoded twice. 324 return NewLIR3(kThumb2RevRR, r_dest_src1, r_src2, r_src2); 325 } 326 opcode = kThumbRev; 327 break; 328 case kOpRevsh: 329 DCHECK_EQ(shift, 0); 330 if (!thumb_form) { 331 // Binary, but rm is encoded twice. 332 return NewLIR3(kThumb2RevshRR, r_dest_src1, r_src2, r_src2); 333 } 334 opcode = kThumbRevsh; 335 break; 336 case kOp2Byte: 337 DCHECK_EQ(shift, 0); 338 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 8); 339 case kOp2Short: 340 DCHECK_EQ(shift, 0); 341 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 16); 342 case kOp2Char: 343 DCHECK_EQ(shift, 0); 344 return NewLIR4(kThumb2Ubfx, r_dest_src1, r_src2, 0, 16); 345 default: 346 LOG(FATAL) << "Bad opcode: " << op; 347 break; 348 } 349 DCHECK(!IsPseudoLirOp(opcode)); 350 if (EncodingMap[opcode].flags & IS_BINARY_OP) { 351 return NewLIR2(opcode, r_dest_src1, r_src2); 352 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { 353 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { 354 return NewLIR3(opcode, r_dest_src1, r_src2, shift); 355 } else { 356 return NewLIR3(opcode, r_dest_src1, r_dest_src1, r_src2); 357 } 358 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { 359 return NewLIR4(opcode, r_dest_src1, r_dest_src1, r_src2, shift); 360 } else { 361 LOG(FATAL) << "Unexpected encoding operand count"; 362 return NULL; 363 } 364} 365 366LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) { 367 return OpRegRegShift(op, r_dest_src1, r_src2, 0); 368} 369 370LIR* ArmMir2Lir::OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) { 371 UNIMPLEMENTED(FATAL); 372 return nullptr; 373} 374 375LIR* ArmMir2Lir::OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) { 376 UNIMPLEMENTED(FATAL); 377 return nullptr; 378} 379 380LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) { 381 LOG(FATAL) << "Unexpected use of OpCondRegReg for Arm"; 382 return NULL; 383} 384 385LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1, 386 int r_src2, int shift) { 387 ArmOpcode opcode = kThumbBkpt; 388 bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) && 389 ARM_LOWREG(r_src2); 390 switch (op) { 391 case kOpAdd: 392 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 393 break; 394 case kOpSub: 395 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 396 break; 397 case kOpRsub: 398 opcode = kThumb2RsubRRR; 399 break; 400 case kOpAdc: 401 opcode = kThumb2AdcRRR; 402 break; 403 case kOpAnd: 404 opcode = kThumb2AndRRR; 405 break; 406 case kOpBic: 407 opcode = kThumb2BicRRR; 408 break; 409 case kOpXor: 410 opcode = kThumb2EorRRR; 411 break; 412 case kOpMul: 413 DCHECK_EQ(shift, 0); 414 opcode = kThumb2MulRRR; 415 break; 416 case kOpDiv: 417 DCHECK_EQ(shift, 0); 418 opcode = kThumb2SdivRRR; 419 break; 420 case kOpOr: 421 opcode = kThumb2OrrRRR; 422 break; 423 case kOpSbc: 424 opcode = kThumb2SbcRRR; 425 break; 426 case kOpLsl: 427 DCHECK_EQ(shift, 0); 428 opcode = kThumb2LslRRR; 429 break; 430 case kOpLsr: 431 DCHECK_EQ(shift, 0); 432 opcode = kThumb2LsrRRR; 433 break; 434 case kOpAsr: 435 DCHECK_EQ(shift, 0); 436 opcode = kThumb2AsrRRR; 437 break; 438 case kOpRor: 439 DCHECK_EQ(shift, 0); 440 opcode = kThumb2RorRRR; 441 break; 442 default: 443 LOG(FATAL) << "Bad opcode: " << op; 444 break; 445 } 446 DCHECK(!IsPseudoLirOp(opcode)); 447 if (EncodingMap[opcode].flags & IS_QUAD_OP) { 448 return NewLIR4(opcode, r_dest, r_src1, r_src2, shift); 449 } else { 450 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); 451 return NewLIR3(opcode, r_dest, r_src1, r_src2); 452 } 453} 454 455LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) { 456 return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0); 457} 458 459LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) { 460 LIR* res; 461 bool neg = (value < 0); 462 int32_t abs_value = (neg) ? -value : value; 463 ArmOpcode opcode = kThumbBkpt; 464 ArmOpcode alt_opcode = kThumbBkpt; 465 bool all_low_regs = (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1)); 466 int32_t mod_imm = ModifiedImmediate(value); 467 468 switch (op) { 469 case kOpLsl: 470 if (all_low_regs) 471 return NewLIR3(kThumbLslRRI5, r_dest, r_src1, value); 472 else 473 return NewLIR3(kThumb2LslRRI5, r_dest, r_src1, value); 474 case kOpLsr: 475 if (all_low_regs) 476 return NewLIR3(kThumbLsrRRI5, r_dest, r_src1, value); 477 else 478 return NewLIR3(kThumb2LsrRRI5, r_dest, r_src1, value); 479 case kOpAsr: 480 if (all_low_regs) 481 return NewLIR3(kThumbAsrRRI5, r_dest, r_src1, value); 482 else 483 return NewLIR3(kThumb2AsrRRI5, r_dest, r_src1, value); 484 case kOpRor: 485 return NewLIR3(kThumb2RorRRI5, r_dest, r_src1, value); 486 case kOpAdd: 487 if (ARM_LOWREG(r_dest) && (r_src1 == r13sp) && 488 (value <= 1020) && ((value & 0x3) == 0)) { 489 return NewLIR3(kThumbAddSpRel, r_dest, r_src1, value >> 2); 490 } else if (ARM_LOWREG(r_dest) && (r_src1 == r15pc) && 491 (value <= 1020) && ((value & 0x3) == 0)) { 492 return NewLIR3(kThumbAddPcRel, r_dest, r_src1, value >> 2); 493 } 494 // Note: intentional fallthrough 495 case kOpSub: 496 if (all_low_regs && ((abs_value & 0x7) == abs_value)) { 497 if (op == kOpAdd) 498 opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; 499 else 500 opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; 501 return NewLIR3(opcode, r_dest, r_src1, abs_value); 502 } 503 if (mod_imm < 0) { 504 mod_imm = ModifiedImmediate(-value); 505 if (mod_imm >= 0) { 506 op = (op == kOpAdd) ? kOpSub : kOpAdd; 507 } 508 } 509 if (mod_imm < 0 && (abs_value & 0x3ff) == abs_value) { 510 // This is deliberately used only if modified immediate encoding is inadequate since 511 // we sometimes actually use the flags for small values but not necessarily low regs. 512 if (op == kOpAdd) 513 opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; 514 else 515 opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; 516 return NewLIR3(opcode, r_dest, r_src1, abs_value); 517 } 518 if (op == kOpSub) { 519 opcode = kThumb2SubRRI8M; 520 alt_opcode = kThumb2SubRRR; 521 } else { 522 opcode = kThumb2AddRRI8M; 523 alt_opcode = kThumb2AddRRR; 524 } 525 break; 526 case kOpRsub: 527 opcode = kThumb2RsubRRI8M; 528 alt_opcode = kThumb2RsubRRR; 529 break; 530 case kOpAdc: 531 opcode = kThumb2AdcRRI8M; 532 alt_opcode = kThumb2AdcRRR; 533 break; 534 case kOpSbc: 535 opcode = kThumb2SbcRRI8M; 536 alt_opcode = kThumb2SbcRRR; 537 break; 538 case kOpOr: 539 opcode = kThumb2OrrRRI8M; 540 alt_opcode = kThumb2OrrRRR; 541 break; 542 case kOpAnd: 543 if (mod_imm < 0) { 544 mod_imm = ModifiedImmediate(~value); 545 if (mod_imm >= 0) { 546 return NewLIR3(kThumb2BicRRI8M, r_dest, r_src1, mod_imm); 547 } 548 } 549 opcode = kThumb2AndRRI8M; 550 alt_opcode = kThumb2AndRRR; 551 break; 552 case kOpXor: 553 opcode = kThumb2EorRRI8M; 554 alt_opcode = kThumb2EorRRR; 555 break; 556 case kOpMul: 557 // TUNING: power of 2, shift & add 558 mod_imm = -1; 559 alt_opcode = kThumb2MulRRR; 560 break; 561 case kOpCmp: { 562 LIR* res; 563 if (mod_imm >= 0) { 564 res = NewLIR2(kThumb2CmpRI8M, r_src1, mod_imm); 565 } else { 566 mod_imm = ModifiedImmediate(-value); 567 if (mod_imm >= 0) { 568 res = NewLIR2(kThumb2CmnRI8M, r_src1, mod_imm); 569 } else { 570 int r_tmp = AllocTemp(); 571 res = LoadConstant(r_tmp, value); 572 OpRegReg(kOpCmp, r_src1, r_tmp); 573 FreeTemp(r_tmp); 574 } 575 } 576 return res; 577 } 578 default: 579 LOG(FATAL) << "Bad opcode: " << op; 580 } 581 582 if (mod_imm >= 0) { 583 return NewLIR3(opcode, r_dest, r_src1, mod_imm); 584 } else { 585 int r_scratch = AllocTemp(); 586 LoadConstant(r_scratch, value); 587 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) 588 res = NewLIR4(alt_opcode, r_dest, r_src1, r_scratch, 0); 589 else 590 res = NewLIR3(alt_opcode, r_dest, r_src1, r_scratch); 591 FreeTemp(r_scratch); 592 return res; 593 } 594} 595 596/* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */ 597LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) { 598 bool neg = (value < 0); 599 int32_t abs_value = (neg) ? -value : value; 600 bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1)); 601 ArmOpcode opcode = kThumbBkpt; 602 switch (op) { 603 case kOpAdd: 604 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 605 DCHECK_EQ((value & 0x3), 0); 606 return NewLIR1(kThumbAddSpI7, value >> 2); 607 } else if (short_form) { 608 opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; 609 } 610 break; 611 case kOpSub: 612 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 613 DCHECK_EQ((value & 0x3), 0); 614 return NewLIR1(kThumbSubSpI7, value >> 2); 615 } else if (short_form) { 616 opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; 617 } 618 break; 619 case kOpCmp: 620 if (!neg && short_form) { 621 opcode = kThumbCmpRI8; 622 } else { 623 short_form = false; 624 } 625 break; 626 default: 627 /* Punt to OpRegRegImm - if bad case catch it there */ 628 short_form = false; 629 break; 630 } 631 if (short_form) { 632 return NewLIR2(opcode, r_dest_src1, abs_value); 633 } else { 634 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); 635 } 636} 637 638LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) { 639 LIR* res = NULL; 640 int32_t val_lo = Low32Bits(value); 641 int32_t val_hi = High32Bits(value); 642 int target_reg = S2d(r_dest_lo, r_dest_hi); 643 if (ARM_FPREG(r_dest_lo)) { 644 if ((val_lo == 0) && (val_hi == 0)) { 645 // TODO: we need better info about the target CPU. a vector exclusive or 646 // would probably be better here if we could rely on its existance. 647 // Load an immediate +2.0 (which encodes to 0) 648 NewLIR2(kThumb2Vmovd_IMM8, target_reg, 0); 649 // +0.0 = +2.0 - +2.0 650 res = NewLIR3(kThumb2Vsubd, target_reg, target_reg, target_reg); 651 } else { 652 int encoded_imm = EncodeImmDouble(value); 653 if (encoded_imm >= 0) { 654 res = NewLIR2(kThumb2Vmovd_IMM8, target_reg, encoded_imm); 655 } 656 } 657 } else { 658 if ((InexpensiveConstantInt(val_lo) && (InexpensiveConstantInt(val_hi)))) { 659 res = LoadConstantNoClobber(r_dest_lo, val_lo); 660 LoadConstantNoClobber(r_dest_hi, val_hi); 661 } 662 } 663 if (res == NULL) { 664 // No short form - load from the literal pool. 665 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 666 if (data_target == NULL) { 667 data_target = AddWideData(&literal_list_, val_lo, val_hi); 668 } 669 if (ARM_FPREG(r_dest_lo)) { 670 res = RawLIR(current_dalvik_offset_, kThumb2Vldrd, 671 target_reg, r15pc, 0, 0, 0, data_target); 672 } else { 673 res = RawLIR(current_dalvik_offset_, kThumb2LdrdPcRel8, 674 r_dest_lo, r_dest_hi, r15pc, 0, 0, data_target); 675 } 676 SetMemRefType(res, true, kLiteral); 677 AppendLIR(res); 678 } 679 return res; 680} 681 682int ArmMir2Lir::EncodeShift(int code, int amount) { 683 return ((amount & 0x1f) << 2) | code; 684} 685 686LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, 687 int scale, OpSize size) { 688 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest); 689 LIR* load; 690 ArmOpcode opcode = kThumbBkpt; 691 bool thumb_form = (all_low_regs && (scale == 0)); 692 int reg_ptr; 693 694 if (ARM_FPREG(r_dest)) { 695 if (ARM_SINGLEREG(r_dest)) { 696 DCHECK((size == kWord) || (size == kSingle)); 697 opcode = kThumb2Vldrs; 698 size = kSingle; 699 } else { 700 DCHECK(ARM_DOUBLEREG(r_dest)); 701 DCHECK((size == kLong) || (size == kDouble)); 702 DCHECK_EQ((r_dest & 0x1), 0); 703 opcode = kThumb2Vldrd; 704 size = kDouble; 705 } 706 } else { 707 if (size == kSingle) 708 size = kWord; 709 } 710 711 switch (size) { 712 case kDouble: // fall-through 713 case kSingle: 714 reg_ptr = AllocTemp(); 715 if (scale) { 716 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 717 EncodeShift(kArmLsl, scale)); 718 } else { 719 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 720 } 721 load = NewLIR3(opcode, r_dest, reg_ptr, 0); 722 FreeTemp(reg_ptr); 723 return load; 724 case kWord: 725 opcode = (thumb_form) ? kThumbLdrRRR : kThumb2LdrRRR; 726 break; 727 case kUnsignedHalf: 728 opcode = (thumb_form) ? kThumbLdrhRRR : kThumb2LdrhRRR; 729 break; 730 case kSignedHalf: 731 opcode = (thumb_form) ? kThumbLdrshRRR : kThumb2LdrshRRR; 732 break; 733 case kUnsignedByte: 734 opcode = (thumb_form) ? kThumbLdrbRRR : kThumb2LdrbRRR; 735 break; 736 case kSignedByte: 737 opcode = (thumb_form) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; 738 break; 739 default: 740 LOG(FATAL) << "Bad size: " << size; 741 } 742 if (thumb_form) 743 load = NewLIR3(opcode, r_dest, rBase, r_index); 744 else 745 load = NewLIR4(opcode, r_dest, rBase, r_index, scale); 746 747 return load; 748} 749 750LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, 751 int scale, OpSize size) { 752 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 753 LIR* store = NULL; 754 ArmOpcode opcode = kThumbBkpt; 755 bool thumb_form = (all_low_regs && (scale == 0)); 756 int reg_ptr; 757 758 if (ARM_FPREG(r_src)) { 759 if (ARM_SINGLEREG(r_src)) { 760 DCHECK((size == kWord) || (size == kSingle)); 761 opcode = kThumb2Vstrs; 762 size = kSingle; 763 } else { 764 DCHECK(ARM_DOUBLEREG(r_src)); 765 DCHECK((size == kLong) || (size == kDouble)); 766 DCHECK_EQ((r_src & 0x1), 0); 767 opcode = kThumb2Vstrd; 768 size = kDouble; 769 } 770 } else { 771 if (size == kSingle) 772 size = kWord; 773 } 774 775 switch (size) { 776 case kDouble: // fall-through 777 case kSingle: 778 reg_ptr = AllocTemp(); 779 if (scale) { 780 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 781 EncodeShift(kArmLsl, scale)); 782 } else { 783 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 784 } 785 store = NewLIR3(opcode, r_src, reg_ptr, 0); 786 FreeTemp(reg_ptr); 787 return store; 788 case kWord: 789 opcode = (thumb_form) ? kThumbStrRRR : kThumb2StrRRR; 790 break; 791 case kUnsignedHalf: 792 case kSignedHalf: 793 opcode = (thumb_form) ? kThumbStrhRRR : kThumb2StrhRRR; 794 break; 795 case kUnsignedByte: 796 case kSignedByte: 797 opcode = (thumb_form) ? kThumbStrbRRR : kThumb2StrbRRR; 798 break; 799 default: 800 LOG(FATAL) << "Bad size: " << size; 801 } 802 if (thumb_form) 803 store = NewLIR3(opcode, r_src, rBase, r_index); 804 else 805 store = NewLIR4(opcode, r_src, rBase, r_index, scale); 806 807 return store; 808} 809 810/* 811 * Load value from base + displacement. Optionally perform null check 812 * on base (which must have an associated s_reg and MIR). If not 813 * performing null check, incoming MIR can be null. 814 */ 815LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, 816 int r_dest_hi, OpSize size, int s_reg) { 817 LIR* load = NULL; 818 ArmOpcode opcode = kThumbBkpt; 819 bool short_form = false; 820 bool thumb2Form = (displacement < 4092 && displacement >= 0); 821 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_dest)); 822 int encoded_disp = displacement; 823 bool is64bit = false; 824 bool already_generated = false; 825 switch (size) { 826 case kDouble: 827 case kLong: 828 is64bit = true; 829 if (ARM_FPREG(r_dest)) { 830 if (ARM_SINGLEREG(r_dest)) { 831 DCHECK(ARM_FPREG(r_dest_hi)); 832 r_dest = S2d(r_dest, r_dest_hi); 833 } 834 opcode = kThumb2Vldrd; 835 if (displacement <= 1020) { 836 short_form = true; 837 encoded_disp >>= 2; 838 } 839 break; 840 } else { 841 if (displacement <= 1020) { 842 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2); 843 } else { 844 load = LoadBaseDispBody(rBase, displacement, r_dest, 845 -1, kWord, s_reg); 846 LoadBaseDispBody(rBase, displacement + 4, r_dest_hi, 847 -1, kWord, INVALID_SREG); 848 } 849 already_generated = true; 850 } 851 case kSingle: 852 case kWord: 853 if (ARM_FPREG(r_dest)) { 854 opcode = kThumb2Vldrs; 855 if (displacement <= 1020) { 856 short_form = true; 857 encoded_disp >>= 2; 858 } 859 break; 860 } 861 if (ARM_LOWREG(r_dest) && (rBase == r15pc) && 862 (displacement <= 1020) && (displacement >= 0)) { 863 short_form = true; 864 encoded_disp >>= 2; 865 opcode = kThumbLdrPcRel; 866 } else if (ARM_LOWREG(r_dest) && (rBase == r13sp) && 867 (displacement <= 1020) && (displacement >= 0)) { 868 short_form = true; 869 encoded_disp >>= 2; 870 opcode = kThumbLdrSpRel; 871 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 872 DCHECK_EQ((displacement & 0x3), 0); 873 short_form = true; 874 encoded_disp >>= 2; 875 opcode = kThumbLdrRRI5; 876 } else if (thumb2Form) { 877 short_form = true; 878 opcode = kThumb2LdrRRI12; 879 } 880 break; 881 case kUnsignedHalf: 882 if (all_low_regs && displacement < 64 && displacement >= 0) { 883 DCHECK_EQ((displacement & 0x1), 0); 884 short_form = true; 885 encoded_disp >>= 1; 886 opcode = kThumbLdrhRRI5; 887 } else if (displacement < 4092 && displacement >= 0) { 888 short_form = true; 889 opcode = kThumb2LdrhRRI12; 890 } 891 break; 892 case kSignedHalf: 893 if (thumb2Form) { 894 short_form = true; 895 opcode = kThumb2LdrshRRI12; 896 } 897 break; 898 case kUnsignedByte: 899 if (all_low_regs && displacement < 32 && displacement >= 0) { 900 short_form = true; 901 opcode = kThumbLdrbRRI5; 902 } else if (thumb2Form) { 903 short_form = true; 904 opcode = kThumb2LdrbRRI12; 905 } 906 break; 907 case kSignedByte: 908 if (thumb2Form) { 909 short_form = true; 910 opcode = kThumb2LdrsbRRI12; 911 } 912 break; 913 default: 914 LOG(FATAL) << "Bad size: " << size; 915 } 916 917 if (!already_generated) { 918 if (short_form) { 919 load = NewLIR3(opcode, r_dest, rBase, encoded_disp); 920 } else { 921 int reg_offset = AllocTemp(); 922 LoadConstant(reg_offset, encoded_disp); 923 load = LoadBaseIndexed(rBase, reg_offset, r_dest, 0, size); 924 FreeTemp(reg_offset); 925 } 926 } 927 928 // TODO: in future may need to differentiate Dalvik accesses w/ spills 929 if (rBase == rARM_SP) { 930 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, is64bit); 931 } 932 return load; 933} 934 935LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest, 936 OpSize size, int s_reg) { 937 return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg); 938} 939 940LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, 941 int r_dest_hi, int s_reg) { 942 return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg); 943} 944 945 946LIR* ArmMir2Lir::StoreBaseDispBody(int rBase, int displacement, 947 int r_src, int r_src_hi, OpSize size) { 948 LIR* store = NULL; 949 ArmOpcode opcode = kThumbBkpt; 950 bool short_form = false; 951 bool thumb2Form = (displacement < 4092 && displacement >= 0); 952 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_src)); 953 int encoded_disp = displacement; 954 bool is64bit = false; 955 bool already_generated = false; 956 switch (size) { 957 case kLong: 958 case kDouble: 959 is64bit = true; 960 if (!ARM_FPREG(r_src)) { 961 if (displacement <= 1020) { 962 store = NewLIR4(kThumb2StrdI8, r_src, r_src_hi, rBase, displacement >> 2); 963 } else { 964 store = StoreBaseDispBody(rBase, displacement, r_src, -1, kWord); 965 StoreBaseDispBody(rBase, displacement + 4, r_src_hi, -1, kWord); 966 } 967 already_generated = true; 968 } else { 969 if (ARM_SINGLEREG(r_src)) { 970 DCHECK(ARM_FPREG(r_src_hi)); 971 r_src = S2d(r_src, r_src_hi); 972 } 973 opcode = kThumb2Vstrd; 974 if (displacement <= 1020) { 975 short_form = true; 976 encoded_disp >>= 2; 977 } 978 } 979 break; 980 case kSingle: 981 case kWord: 982 if (ARM_FPREG(r_src)) { 983 DCHECK(ARM_SINGLEREG(r_src)); 984 opcode = kThumb2Vstrs; 985 if (displacement <= 1020) { 986 short_form = true; 987 encoded_disp >>= 2; 988 } 989 break; 990 } 991 if (ARM_LOWREG(r_src) && (rBase == r13sp) && 992 (displacement <= 1020) && (displacement >= 0)) { 993 short_form = true; 994 encoded_disp >>= 2; 995 opcode = kThumbStrSpRel; 996 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 997 DCHECK_EQ((displacement & 0x3), 0); 998 short_form = true; 999 encoded_disp >>= 2; 1000 opcode = kThumbStrRRI5; 1001 } else if (thumb2Form) { 1002 short_form = true; 1003 opcode = kThumb2StrRRI12; 1004 } 1005 break; 1006 case kUnsignedHalf: 1007 case kSignedHalf: 1008 if (all_low_regs && displacement < 64 && displacement >= 0) { 1009 DCHECK_EQ((displacement & 0x1), 0); 1010 short_form = true; 1011 encoded_disp >>= 1; 1012 opcode = kThumbStrhRRI5; 1013 } else if (thumb2Form) { 1014 short_form = true; 1015 opcode = kThumb2StrhRRI12; 1016 } 1017 break; 1018 case kUnsignedByte: 1019 case kSignedByte: 1020 if (all_low_regs && displacement < 32 && displacement >= 0) { 1021 short_form = true; 1022 opcode = kThumbStrbRRI5; 1023 } else if (thumb2Form) { 1024 short_form = true; 1025 opcode = kThumb2StrbRRI12; 1026 } 1027 break; 1028 default: 1029 LOG(FATAL) << "Bad size: " << size; 1030 } 1031 if (!already_generated) { 1032 if (short_form) { 1033 store = NewLIR3(opcode, r_src, rBase, encoded_disp); 1034 } else { 1035 int r_scratch = AllocTemp(); 1036 LoadConstant(r_scratch, encoded_disp); 1037 store = StoreBaseIndexed(rBase, r_scratch, r_src, 0, size); 1038 FreeTemp(r_scratch); 1039 } 1040 } 1041 1042 // TODO: In future, may need to differentiate Dalvik & spill accesses 1043 if (rBase == rARM_SP) { 1044 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, is64bit); 1045 } 1046 return store; 1047} 1048 1049LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src, 1050 OpSize size) { 1051 return StoreBaseDispBody(rBase, displacement, r_src, -1, size); 1052} 1053 1054LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement, 1055 int r_src_lo, int r_src_hi) { 1056 return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong); 1057} 1058 1059LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) { 1060 int opcode; 1061 DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src)); 1062 if (ARM_DOUBLEREG(r_dest)) { 1063 opcode = kThumb2Vmovd; 1064 } else { 1065 if (ARM_SINGLEREG(r_dest)) { 1066 opcode = ARM_SINGLEREG(r_src) ? kThumb2Vmovs : kThumb2Fmsr; 1067 } else { 1068 DCHECK(ARM_SINGLEREG(r_src)); 1069 opcode = kThumb2Fmrs; 1070 } 1071 } 1072 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 1073 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 1074 res->flags.is_nop = true; 1075 } 1076 return res; 1077} 1078 1079LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) { 1080 LOG(FATAL) << "Unexpected use of OpThreadMem for Arm"; 1081 return NULL; 1082} 1083 1084LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) { 1085 LOG(FATAL) << "Unexpected use of OpMem for Arm"; 1086 return NULL; 1087} 1088 1089LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, 1090 int displacement, int r_src, int r_src_hi, OpSize size, 1091 int s_reg) { 1092 LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm"; 1093 return NULL; 1094} 1095 1096LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) { 1097 LOG(FATAL) << "Unexpected use of OpRegMem for Arm"; 1098 return NULL; 1099} 1100 1101LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, 1102 int displacement, int r_dest, int r_dest_hi, OpSize size, 1103 int s_reg) { 1104 LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm"; 1105 return NULL; 1106} 1107 1108} // namespace art 1109