utility_arm.cc revision 409fe94ad529d9334587be80b9f6a3d166805508
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "arm_lir.h" 18#include "codegen_arm.h" 19#include "dex/quick/mir_to_lir-inl.h" 20 21namespace art { 22 23/* This file contains codegen for the Thumb ISA. */ 24 25static int EncodeImmSingle(int value) { 26 int res; 27 int bit_a = (value & 0x80000000) >> 31; 28 int not_bit_b = (value & 0x40000000) >> 30; 29 int bit_b = (value & 0x20000000) >> 29; 30 int b_smear = (value & 0x3e000000) >> 25; 31 int slice = (value & 0x01f80000) >> 19; 32 int zeroes = (value & 0x0007ffff); 33 if (zeroes != 0) 34 return -1; 35 if (bit_b) { 36 if ((not_bit_b != 0) || (b_smear != 0x1f)) 37 return -1; 38 } else { 39 if ((not_bit_b != 1) || (b_smear != 0x0)) 40 return -1; 41 } 42 res = (bit_a << 7) | (bit_b << 6) | slice; 43 return res; 44} 45 46/* 47 * Determine whether value can be encoded as a Thumb2 floating point 48 * immediate. If not, return -1. If so return encoded 8-bit value. 49 */ 50static int EncodeImmDouble(int64_t value) { 51 int res; 52 int bit_a = (value & 0x8000000000000000ll) >> 63; 53 int not_bit_b = (value & 0x4000000000000000ll) >> 62; 54 int bit_b = (value & 0x2000000000000000ll) >> 61; 55 int b_smear = (value & 0x3fc0000000000000ll) >> 54; 56 int slice = (value & 0x003f000000000000ll) >> 48; 57 uint64_t zeroes = (value & 0x0000ffffffffffffll); 58 if (zeroes != 0) 59 return -1; 60 if (bit_b) { 61 if ((not_bit_b != 0) || (b_smear != 0xff)) 62 return -1; 63 } else { 64 if ((not_bit_b != 1) || (b_smear != 0x0)) 65 return -1; 66 } 67 res = (bit_a << 7) | (bit_b << 6) | slice; 68 return res; 69} 70 71LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { 72 DCHECK(ARM_SINGLEREG(r_dest)); 73 if (value == 0) { 74 // TODO: we need better info about the target CPU. a vector exclusive or 75 // would probably be better here if we could rely on its existance. 76 // Load an immediate +2.0 (which encodes to 0) 77 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0); 78 // +0.0 = +2.0 - +2.0 79 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest); 80 } else { 81 int encoded_imm = EncodeImmSingle(value); 82 if (encoded_imm >= 0) { 83 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm); 84 } 85 } 86 LIR* data_target = ScanLiteralPool(literal_list_, value, 0); 87 if (data_target == NULL) { 88 data_target = AddWordData(&literal_list_, value); 89 } 90 LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs, 91 r_dest, r15pc, 0, 0, 0, data_target); 92 SetMemRefType(load_pc_rel, true, kLiteral); 93 AppendLIR(load_pc_rel); 94 return load_pc_rel; 95} 96 97static int LeadingZeros(uint32_t val) { 98 uint32_t alt; 99 int n; 100 int count; 101 102 count = 16; 103 n = 32; 104 do { 105 alt = val >> count; 106 if (alt != 0) { 107 n = n - count; 108 val = alt; 109 } 110 count >>= 1; 111 } while (count); 112 return n - val; 113} 114 115/* 116 * Determine whether value can be encoded as a Thumb2 modified 117 * immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form. 118 */ 119int ArmMir2Lir::ModifiedImmediate(uint32_t value) { 120 int z_leading; 121 int z_trailing; 122 uint32_t b0 = value & 0xff; 123 124 /* Note: case of value==0 must use 0:000:0:0000000 encoding */ 125 if (value <= 0xFF) 126 return b0; // 0:000:a:bcdefgh 127 if (value == ((b0 << 16) | b0)) 128 return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */ 129 if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0)) 130 return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */ 131 b0 = (value >> 8) & 0xff; 132 if (value == ((b0 << 24) | (b0 << 8))) 133 return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */ 134 /* Can we do it with rotation? */ 135 z_leading = LeadingZeros(value); 136 z_trailing = 32 - LeadingZeros(~value & (value - 1)); 137 /* A run of eight or fewer active bits? */ 138 if ((z_leading + z_trailing) < 24) 139 return -1; /* No - bail */ 140 /* left-justify the constant, discarding msb (known to be 1) */ 141 value <<= z_leading + 1; 142 /* Create bcdefgh */ 143 value >>= 25; 144 /* Put it all together */ 145 return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */ 146} 147 148bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { 149 return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); 150} 151 152bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { 153 return EncodeImmSingle(value) >= 0; 154} 155 156bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { 157 return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); 158} 159 160bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { 161 return EncodeImmDouble(value) >= 0; 162} 163 164/* 165 * Load a immediate using a shortcut if possible; otherwise 166 * grab from the per-translation literal pool. 167 * 168 * No additional register clobbering operation performed. Use this version when 169 * 1) r_dest is freshly returned from AllocTemp or 170 * 2) The codegen is under fixed register usage 171 */ 172LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) { 173 LIR* res; 174 int mod_imm; 175 176 if (ARM_FPREG(r_dest)) { 177 return LoadFPConstantValue(r_dest, value); 178 } 179 180 /* See if the value can be constructed cheaply */ 181 if (ARM_LOWREG(r_dest) && (value >= 0) && (value <= 255)) { 182 return NewLIR2(kThumbMovImm, r_dest, value); 183 } 184 /* Check Modified immediate special cases */ 185 mod_imm = ModifiedImmediate(value); 186 if (mod_imm >= 0) { 187 res = NewLIR2(kThumb2MovImmShift, r_dest, mod_imm); 188 return res; 189 } 190 mod_imm = ModifiedImmediate(~value); 191 if (mod_imm >= 0) { 192 res = NewLIR2(kThumb2MvnImm12, r_dest, mod_imm); 193 return res; 194 } 195 /* 16-bit immediate? */ 196 if ((value & 0xffff) == value) { 197 res = NewLIR2(kThumb2MovImm16, r_dest, value); 198 return res; 199 } 200 /* Do a low/high pair */ 201 res = NewLIR2(kThumb2MovImm16, r_dest, Low16Bits(value)); 202 NewLIR2(kThumb2MovImm16H, r_dest, High16Bits(value)); 203 return res; 204} 205 206LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { 207 LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly*/); 208 res->target = target; 209 return res; 210} 211 212LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 213 LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */, 214 ArmConditionEncoding(cc)); 215 branch->target = target; 216 return branch; 217} 218 219LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) { 220 ArmOpcode opcode = kThumbBkpt; 221 switch (op) { 222 case kOpBlx: 223 opcode = kThumbBlxR; 224 break; 225 default: 226 LOG(FATAL) << "Bad opcode " << op; 227 } 228 return NewLIR1(opcode, r_dest_src); 229} 230 231LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, 232 int shift) { 233 bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)); 234 ArmOpcode opcode = kThumbBkpt; 235 switch (op) { 236 case kOpAdc: 237 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 238 break; 239 case kOpAnd: 240 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; 241 break; 242 case kOpBic: 243 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; 244 break; 245 case kOpCmn: 246 DCHECK_EQ(shift, 0); 247 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR; 248 break; 249 case kOpCmp: 250 if (thumb_form) 251 opcode = kThumbCmpRR; 252 else if ((shift == 0) && !ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 253 opcode = kThumbCmpHH; 254 else if ((shift == 0) && ARM_LOWREG(r_dest_src1)) 255 opcode = kThumbCmpLH; 256 else if (shift == 0) 257 opcode = kThumbCmpHL; 258 else 259 opcode = kThumb2CmpRR; 260 break; 261 case kOpXor: 262 opcode = (thumb_form) ? kThumbEorRR : kThumb2EorRRR; 263 break; 264 case kOpMov: 265 DCHECK_EQ(shift, 0); 266 if (ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)) 267 opcode = kThumbMovRR; 268 else if (!ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 269 opcode = kThumbMovRR_H2H; 270 else if (ARM_LOWREG(r_dest_src1)) 271 opcode = kThumbMovRR_H2L; 272 else 273 opcode = kThumbMovRR_L2H; 274 break; 275 case kOpMul: 276 DCHECK_EQ(shift, 0); 277 opcode = (thumb_form) ? kThumbMul : kThumb2MulRRR; 278 break; 279 case kOpMvn: 280 opcode = (thumb_form) ? kThumbMvn : kThumb2MnvRR; 281 break; 282 case kOpNeg: 283 DCHECK_EQ(shift, 0); 284 opcode = (thumb_form) ? kThumbNeg : kThumb2NegRR; 285 break; 286 case kOpOr: 287 opcode = (thumb_form) ? kThumbOrr : kThumb2OrrRRR; 288 break; 289 case kOpSbc: 290 opcode = (thumb_form) ? kThumbSbc : kThumb2SbcRRR; 291 break; 292 case kOpTst: 293 opcode = (thumb_form) ? kThumbTst : kThumb2TstRR; 294 break; 295 case kOpLsl: 296 DCHECK_EQ(shift, 0); 297 opcode = (thumb_form) ? kThumbLslRR : kThumb2LslRRR; 298 break; 299 case kOpLsr: 300 DCHECK_EQ(shift, 0); 301 opcode = (thumb_form) ? kThumbLsrRR : kThumb2LsrRRR; 302 break; 303 case kOpAsr: 304 DCHECK_EQ(shift, 0); 305 opcode = (thumb_form) ? kThumbAsrRR : kThumb2AsrRRR; 306 break; 307 case kOpRor: 308 DCHECK_EQ(shift, 0); 309 opcode = (thumb_form) ? kThumbRorRR : kThumb2RorRRR; 310 break; 311 case kOpAdd: 312 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 313 break; 314 case kOpSub: 315 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 316 break; 317 case kOp2Byte: 318 DCHECK_EQ(shift, 0); 319 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 8); 320 case kOp2Short: 321 DCHECK_EQ(shift, 0); 322 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 16); 323 case kOp2Char: 324 DCHECK_EQ(shift, 0); 325 return NewLIR4(kThumb2Ubfx, r_dest_src1, r_src2, 0, 16); 326 default: 327 LOG(FATAL) << "Bad opcode: " << op; 328 break; 329 } 330 DCHECK(!IsPseudoLirOp(opcode)); 331 if (EncodingMap[opcode].flags & IS_BINARY_OP) { 332 return NewLIR2(opcode, r_dest_src1, r_src2); 333 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { 334 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { 335 return NewLIR3(opcode, r_dest_src1, r_src2, shift); 336 } else { 337 return NewLIR3(opcode, r_dest_src1, r_dest_src1, r_src2); 338 } 339 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { 340 return NewLIR4(opcode, r_dest_src1, r_dest_src1, r_src2, shift); 341 } else { 342 LOG(FATAL) << "Unexpected encoding operand count"; 343 return NULL; 344 } 345} 346 347LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) { 348 return OpRegRegShift(op, r_dest_src1, r_src2, 0); 349} 350 351LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1, 352 int r_src2, int shift) { 353 ArmOpcode opcode = kThumbBkpt; 354 bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) && 355 ARM_LOWREG(r_src2); 356 switch (op) { 357 case kOpAdd: 358 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 359 break; 360 case kOpSub: 361 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 362 break; 363 case kOpRsub: 364 opcode = kThumb2RsubRRR; 365 break; 366 case kOpAdc: 367 opcode = kThumb2AdcRRR; 368 break; 369 case kOpAnd: 370 opcode = kThumb2AndRRR; 371 break; 372 case kOpBic: 373 opcode = kThumb2BicRRR; 374 break; 375 case kOpXor: 376 opcode = kThumb2EorRRR; 377 break; 378 case kOpMul: 379 DCHECK_EQ(shift, 0); 380 opcode = kThumb2MulRRR; 381 break; 382 case kOpOr: 383 opcode = kThumb2OrrRRR; 384 break; 385 case kOpSbc: 386 opcode = kThumb2SbcRRR; 387 break; 388 case kOpLsl: 389 DCHECK_EQ(shift, 0); 390 opcode = kThumb2LslRRR; 391 break; 392 case kOpLsr: 393 DCHECK_EQ(shift, 0); 394 opcode = kThumb2LsrRRR; 395 break; 396 case kOpAsr: 397 DCHECK_EQ(shift, 0); 398 opcode = kThumb2AsrRRR; 399 break; 400 case kOpRor: 401 DCHECK_EQ(shift, 0); 402 opcode = kThumb2RorRRR; 403 break; 404 default: 405 LOG(FATAL) << "Bad opcode: " << op; 406 break; 407 } 408 DCHECK(!IsPseudoLirOp(opcode)); 409 if (EncodingMap[opcode].flags & IS_QUAD_OP) { 410 return NewLIR4(opcode, r_dest, r_src1, r_src2, shift); 411 } else { 412 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); 413 return NewLIR3(opcode, r_dest, r_src1, r_src2); 414 } 415} 416 417LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) { 418 return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0); 419} 420 421LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) { 422 LIR* res; 423 bool neg = (value < 0); 424 int abs_value = (neg) ? -value : value; 425 ArmOpcode opcode = kThumbBkpt; 426 ArmOpcode alt_opcode = kThumbBkpt; 427 bool all_low_regs = (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1)); 428 int mod_imm = ModifiedImmediate(value); 429 int mod_imm_neg = ModifiedImmediate(-value); 430 431 switch (op) { 432 case kOpLsl: 433 if (all_low_regs) 434 return NewLIR3(kThumbLslRRI5, r_dest, r_src1, value); 435 else 436 return NewLIR3(kThumb2LslRRI5, r_dest, r_src1, value); 437 case kOpLsr: 438 if (all_low_regs) 439 return NewLIR3(kThumbLsrRRI5, r_dest, r_src1, value); 440 else 441 return NewLIR3(kThumb2LsrRRI5, r_dest, r_src1, value); 442 case kOpAsr: 443 if (all_low_regs) 444 return NewLIR3(kThumbAsrRRI5, r_dest, r_src1, value); 445 else 446 return NewLIR3(kThumb2AsrRRI5, r_dest, r_src1, value); 447 case kOpRor: 448 return NewLIR3(kThumb2RorRRI5, r_dest, r_src1, value); 449 case kOpAdd: 450 if (ARM_LOWREG(r_dest) && (r_src1 == r13sp) && 451 (value <= 1020) && ((value & 0x3) == 0)) { 452 return NewLIR3(kThumbAddSpRel, r_dest, r_src1, value >> 2); 453 } else if (ARM_LOWREG(r_dest) && (r_src1 == r15pc) && 454 (value <= 1020) && ((value & 0x3) == 0)) { 455 return NewLIR3(kThumbAddPcRel, r_dest, r_src1, value >> 2); 456 } 457 // Note: intentional fallthrough 458 case kOpSub: 459 if (all_low_regs && ((abs_value & 0x7) == abs_value)) { 460 if (op == kOpAdd) 461 opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; 462 else 463 opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; 464 return NewLIR3(opcode, r_dest, r_src1, abs_value); 465 } else if ((abs_value & 0xff) == abs_value) { 466 if (op == kOpAdd) 467 opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; 468 else 469 opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; 470 return NewLIR3(opcode, r_dest, r_src1, abs_value); 471 } 472 if (mod_imm_neg >= 0) { 473 op = (op == kOpAdd) ? kOpSub : kOpAdd; 474 mod_imm = mod_imm_neg; 475 } 476 if (op == kOpSub) { 477 opcode = kThumb2SubRRI8; 478 alt_opcode = kThumb2SubRRR; 479 } else { 480 opcode = kThumb2AddRRI8; 481 alt_opcode = kThumb2AddRRR; 482 } 483 break; 484 case kOpRsub: 485 opcode = kThumb2RsubRRI8; 486 alt_opcode = kThumb2RsubRRR; 487 break; 488 case kOpAdc: 489 opcode = kThumb2AdcRRI8; 490 alt_opcode = kThumb2AdcRRR; 491 break; 492 case kOpSbc: 493 opcode = kThumb2SbcRRI8; 494 alt_opcode = kThumb2SbcRRR; 495 break; 496 case kOpOr: 497 opcode = kThumb2OrrRRI8; 498 alt_opcode = kThumb2OrrRRR; 499 break; 500 case kOpAnd: 501 opcode = kThumb2AndRRI8; 502 alt_opcode = kThumb2AndRRR; 503 break; 504 case kOpXor: 505 opcode = kThumb2EorRRI8; 506 alt_opcode = kThumb2EorRRR; 507 break; 508 case kOpMul: 509 // TUNING: power of 2, shift & add 510 mod_imm = -1; 511 alt_opcode = kThumb2MulRRR; 512 break; 513 case kOpCmp: { 514 int mod_imm = ModifiedImmediate(value); 515 LIR* res; 516 if (mod_imm >= 0) { 517 res = NewLIR2(kThumb2CmpRI12, r_src1, mod_imm); 518 } else { 519 int r_tmp = AllocTemp(); 520 res = LoadConstant(r_tmp, value); 521 OpRegReg(kOpCmp, r_src1, r_tmp); 522 FreeTemp(r_tmp); 523 } 524 return res; 525 } 526 default: 527 LOG(FATAL) << "Bad opcode: " << op; 528 } 529 530 if (mod_imm >= 0) { 531 return NewLIR3(opcode, r_dest, r_src1, mod_imm); 532 } else { 533 int r_scratch = AllocTemp(); 534 LoadConstant(r_scratch, value); 535 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) 536 res = NewLIR4(alt_opcode, r_dest, r_src1, r_scratch, 0); 537 else 538 res = NewLIR3(alt_opcode, r_dest, r_src1, r_scratch); 539 FreeTemp(r_scratch); 540 return res; 541 } 542} 543 544/* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */ 545LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) { 546 bool neg = (value < 0); 547 int abs_value = (neg) ? -value : value; 548 bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1)); 549 ArmOpcode opcode = kThumbBkpt; 550 switch (op) { 551 case kOpAdd: 552 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 553 DCHECK_EQ((value & 0x3), 0); 554 return NewLIR1(kThumbAddSpI7, value >> 2); 555 } else if (short_form) { 556 opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; 557 } 558 break; 559 case kOpSub: 560 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 561 DCHECK_EQ((value & 0x3), 0); 562 return NewLIR1(kThumbSubSpI7, value >> 2); 563 } else if (short_form) { 564 opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; 565 } 566 break; 567 case kOpCmp: 568 if (ARM_LOWREG(r_dest_src1) && short_form) { 569 opcode = (short_form) ? kThumbCmpRI8 : kThumbCmpRR; 570 } else if (ARM_LOWREG(r_dest_src1)) { 571 opcode = kThumbCmpRR; 572 } else { 573 short_form = false; 574 opcode = kThumbCmpHL; 575 } 576 break; 577 default: 578 /* Punt to OpRegRegImm - if bad case catch it there */ 579 short_form = false; 580 break; 581 } 582 if (short_form) { 583 return NewLIR2(opcode, r_dest_src1, abs_value); 584 } else { 585 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); 586 } 587} 588 589LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) { 590 LIR* res = NULL; 591 int32_t val_lo = Low32Bits(value); 592 int32_t val_hi = High32Bits(value); 593 int target_reg = S2d(r_dest_lo, r_dest_hi); 594 if (ARM_FPREG(r_dest_lo)) { 595 if ((val_lo == 0) && (val_hi == 0)) { 596 // TODO: we need better info about the target CPU. a vector exclusive or 597 // would probably be better here if we could rely on its existance. 598 // Load an immediate +2.0 (which encodes to 0) 599 NewLIR2(kThumb2Vmovd_IMM8, target_reg, 0); 600 // +0.0 = +2.0 - +2.0 601 res = NewLIR3(kThumb2Vsubd, target_reg, target_reg, target_reg); 602 } else { 603 int encoded_imm = EncodeImmDouble(value); 604 if (encoded_imm >= 0) { 605 res = NewLIR2(kThumb2Vmovd_IMM8, target_reg, encoded_imm); 606 } 607 } 608 } else { 609 if ((InexpensiveConstantInt(val_lo) && (InexpensiveConstantInt(val_hi)))) { 610 res = LoadConstantNoClobber(r_dest_lo, val_lo); 611 LoadConstantNoClobber(r_dest_hi, val_hi); 612 } 613 } 614 if (res == NULL) { 615 // No short form - load from the literal pool. 616 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 617 if (data_target == NULL) { 618 data_target = AddWideData(&literal_list_, val_lo, val_hi); 619 } 620 if (ARM_FPREG(r_dest_lo)) { 621 res = RawLIR(current_dalvik_offset_, kThumb2Vldrd, 622 target_reg, r15pc, 0, 0, 0, data_target); 623 } else { 624 res = RawLIR(current_dalvik_offset_, kThumb2LdrdPcRel8, 625 r_dest_lo, r_dest_hi, r15pc, 0, 0, data_target); 626 } 627 SetMemRefType(res, true, kLiteral); 628 AppendLIR(res); 629 } 630 return res; 631} 632 633int ArmMir2Lir::EncodeShift(int code, int amount) { 634 return ((amount & 0x1f) << 2) | code; 635} 636 637LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, 638 int scale, OpSize size) { 639 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest); 640 LIR* load; 641 ArmOpcode opcode = kThumbBkpt; 642 bool thumb_form = (all_low_regs && (scale == 0)); 643 int reg_ptr; 644 645 if (ARM_FPREG(r_dest)) { 646 if (ARM_SINGLEREG(r_dest)) { 647 DCHECK((size == kWord) || (size == kSingle)); 648 opcode = kThumb2Vldrs; 649 size = kSingle; 650 } else { 651 DCHECK(ARM_DOUBLEREG(r_dest)); 652 DCHECK((size == kLong) || (size == kDouble)); 653 DCHECK_EQ((r_dest & 0x1), 0); 654 opcode = kThumb2Vldrd; 655 size = kDouble; 656 } 657 } else { 658 if (size == kSingle) 659 size = kWord; 660 } 661 662 switch (size) { 663 case kDouble: // fall-through 664 case kSingle: 665 reg_ptr = AllocTemp(); 666 if (scale) { 667 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 668 EncodeShift(kArmLsl, scale)); 669 } else { 670 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 671 } 672 load = NewLIR3(opcode, r_dest, reg_ptr, 0); 673 FreeTemp(reg_ptr); 674 return load; 675 case kWord: 676 opcode = (thumb_form) ? kThumbLdrRRR : kThumb2LdrRRR; 677 break; 678 case kUnsignedHalf: 679 opcode = (thumb_form) ? kThumbLdrhRRR : kThumb2LdrhRRR; 680 break; 681 case kSignedHalf: 682 opcode = (thumb_form) ? kThumbLdrshRRR : kThumb2LdrshRRR; 683 break; 684 case kUnsignedByte: 685 opcode = (thumb_form) ? kThumbLdrbRRR : kThumb2LdrbRRR; 686 break; 687 case kSignedByte: 688 opcode = (thumb_form) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; 689 break; 690 default: 691 LOG(FATAL) << "Bad size: " << size; 692 } 693 if (thumb_form) 694 load = NewLIR3(opcode, r_dest, rBase, r_index); 695 else 696 load = NewLIR4(opcode, r_dest, rBase, r_index, scale); 697 698 return load; 699} 700 701LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, 702 int scale, OpSize size) { 703 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 704 LIR* store = NULL; 705 ArmOpcode opcode = kThumbBkpt; 706 bool thumb_form = (all_low_regs && (scale == 0)); 707 int reg_ptr; 708 709 if (ARM_FPREG(r_src)) { 710 if (ARM_SINGLEREG(r_src)) { 711 DCHECK((size == kWord) || (size == kSingle)); 712 opcode = kThumb2Vstrs; 713 size = kSingle; 714 } else { 715 DCHECK(ARM_DOUBLEREG(r_src)); 716 DCHECK((size == kLong) || (size == kDouble)); 717 DCHECK_EQ((r_src & 0x1), 0); 718 opcode = kThumb2Vstrd; 719 size = kDouble; 720 } 721 } else { 722 if (size == kSingle) 723 size = kWord; 724 } 725 726 switch (size) { 727 case kDouble: // fall-through 728 case kSingle: 729 reg_ptr = AllocTemp(); 730 if (scale) { 731 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 732 EncodeShift(kArmLsl, scale)); 733 } else { 734 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 735 } 736 store = NewLIR3(opcode, r_src, reg_ptr, 0); 737 FreeTemp(reg_ptr); 738 return store; 739 case kWord: 740 opcode = (thumb_form) ? kThumbStrRRR : kThumb2StrRRR; 741 break; 742 case kUnsignedHalf: 743 case kSignedHalf: 744 opcode = (thumb_form) ? kThumbStrhRRR : kThumb2StrhRRR; 745 break; 746 case kUnsignedByte: 747 case kSignedByte: 748 opcode = (thumb_form) ? kThumbStrbRRR : kThumb2StrbRRR; 749 break; 750 default: 751 LOG(FATAL) << "Bad size: " << size; 752 } 753 if (thumb_form) 754 store = NewLIR3(opcode, r_src, rBase, r_index); 755 else 756 store = NewLIR4(opcode, r_src, rBase, r_index, scale); 757 758 return store; 759} 760 761/* 762 * Load value from base + displacement. Optionally perform null check 763 * on base (which must have an associated s_reg and MIR). If not 764 * performing null check, incoming MIR can be null. 765 */ 766LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, 767 int r_dest_hi, OpSize size, int s_reg) { 768 LIR* load = NULL; 769 ArmOpcode opcode = kThumbBkpt; 770 bool short_form = false; 771 bool thumb2Form = (displacement < 4092 && displacement >= 0); 772 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_dest)); 773 int encoded_disp = displacement; 774 bool is64bit = false; 775 bool already_generated = false; 776 switch (size) { 777 case kDouble: 778 case kLong: 779 is64bit = true; 780 if (ARM_FPREG(r_dest)) { 781 if (ARM_SINGLEREG(r_dest)) { 782 DCHECK(ARM_FPREG(r_dest_hi)); 783 r_dest = S2d(r_dest, r_dest_hi); 784 } 785 opcode = kThumb2Vldrd; 786 if (displacement <= 1020) { 787 short_form = true; 788 encoded_disp >>= 2; 789 } 790 break; 791 } else { 792 if (displacement <= 1020) { 793 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2); 794 } else { 795 load = LoadBaseDispBody(rBase, displacement, r_dest, 796 -1, kWord, s_reg); 797 LoadBaseDispBody(rBase, displacement + 4, r_dest_hi, 798 -1, kWord, INVALID_SREG); 799 } 800 already_generated = true; 801 } 802 case kSingle: 803 case kWord: 804 if (ARM_FPREG(r_dest)) { 805 opcode = kThumb2Vldrs; 806 if (displacement <= 1020) { 807 short_form = true; 808 encoded_disp >>= 2; 809 } 810 break; 811 } 812 if (ARM_LOWREG(r_dest) && (rBase == r15pc) && 813 (displacement <= 1020) && (displacement >= 0)) { 814 short_form = true; 815 encoded_disp >>= 2; 816 opcode = kThumbLdrPcRel; 817 } else if (ARM_LOWREG(r_dest) && (rBase == r13sp) && 818 (displacement <= 1020) && (displacement >= 0)) { 819 short_form = true; 820 encoded_disp >>= 2; 821 opcode = kThumbLdrSpRel; 822 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 823 DCHECK_EQ((displacement & 0x3), 0); 824 short_form = true; 825 encoded_disp >>= 2; 826 opcode = kThumbLdrRRI5; 827 } else if (thumb2Form) { 828 short_form = true; 829 opcode = kThumb2LdrRRI12; 830 } 831 break; 832 case kUnsignedHalf: 833 if (all_low_regs && displacement < 64 && displacement >= 0) { 834 DCHECK_EQ((displacement & 0x1), 0); 835 short_form = true; 836 encoded_disp >>= 1; 837 opcode = kThumbLdrhRRI5; 838 } else if (displacement < 4092 && displacement >= 0) { 839 short_form = true; 840 opcode = kThumb2LdrhRRI12; 841 } 842 break; 843 case kSignedHalf: 844 if (thumb2Form) { 845 short_form = true; 846 opcode = kThumb2LdrshRRI12; 847 } 848 break; 849 case kUnsignedByte: 850 if (all_low_regs && displacement < 32 && displacement >= 0) { 851 short_form = true; 852 opcode = kThumbLdrbRRI5; 853 } else if (thumb2Form) { 854 short_form = true; 855 opcode = kThumb2LdrbRRI12; 856 } 857 break; 858 case kSignedByte: 859 if (thumb2Form) { 860 short_form = true; 861 opcode = kThumb2LdrsbRRI12; 862 } 863 break; 864 default: 865 LOG(FATAL) << "Bad size: " << size; 866 } 867 868 if (!already_generated) { 869 if (short_form) { 870 load = NewLIR3(opcode, r_dest, rBase, encoded_disp); 871 } else { 872 int reg_offset = AllocTemp(); 873 LoadConstant(reg_offset, encoded_disp); 874 load = LoadBaseIndexed(rBase, reg_offset, r_dest, 0, size); 875 FreeTemp(reg_offset); 876 } 877 } 878 879 // TODO: in future may need to differentiate Dalvik accesses w/ spills 880 if (rBase == rARM_SP) { 881 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, is64bit); 882 } 883 return load; 884} 885 886LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest, 887 OpSize size, int s_reg) { 888 return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg); 889} 890 891LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, 892 int r_dest_hi, int s_reg) { 893 return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg); 894} 895 896 897LIR* ArmMir2Lir::StoreBaseDispBody(int rBase, int displacement, 898 int r_src, int r_src_hi, OpSize size) { 899 LIR* store = NULL; 900 ArmOpcode opcode = kThumbBkpt; 901 bool short_form = false; 902 bool thumb2Form = (displacement < 4092 && displacement >= 0); 903 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_src)); 904 int encoded_disp = displacement; 905 bool is64bit = false; 906 bool already_generated = false; 907 switch (size) { 908 case kLong: 909 case kDouble: 910 is64bit = true; 911 if (!ARM_FPREG(r_src)) { 912 if (displacement <= 1020) { 913 store = NewLIR4(kThumb2StrdI8, r_src, r_src_hi, rBase, displacement >> 2); 914 } else { 915 store = StoreBaseDispBody(rBase, displacement, r_src, -1, kWord); 916 StoreBaseDispBody(rBase, displacement + 4, r_src_hi, -1, kWord); 917 } 918 already_generated = true; 919 } else { 920 if (ARM_SINGLEREG(r_src)) { 921 DCHECK(ARM_FPREG(r_src_hi)); 922 r_src = S2d(r_src, r_src_hi); 923 } 924 opcode = kThumb2Vstrd; 925 if (displacement <= 1020) { 926 short_form = true; 927 encoded_disp >>= 2; 928 } 929 } 930 break; 931 case kSingle: 932 case kWord: 933 if (ARM_FPREG(r_src)) { 934 DCHECK(ARM_SINGLEREG(r_src)); 935 opcode = kThumb2Vstrs; 936 if (displacement <= 1020) { 937 short_form = true; 938 encoded_disp >>= 2; 939 } 940 break; 941 } 942 if (ARM_LOWREG(r_src) && (rBase == r13sp) && 943 (displacement <= 1020) && (displacement >= 0)) { 944 short_form = true; 945 encoded_disp >>= 2; 946 opcode = kThumbStrSpRel; 947 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 948 DCHECK_EQ((displacement & 0x3), 0); 949 short_form = true; 950 encoded_disp >>= 2; 951 opcode = kThumbStrRRI5; 952 } else if (thumb2Form) { 953 short_form = true; 954 opcode = kThumb2StrRRI12; 955 } 956 break; 957 case kUnsignedHalf: 958 case kSignedHalf: 959 if (all_low_regs && displacement < 64 && displacement >= 0) { 960 DCHECK_EQ((displacement & 0x1), 0); 961 short_form = true; 962 encoded_disp >>= 1; 963 opcode = kThumbStrhRRI5; 964 } else if (thumb2Form) { 965 short_form = true; 966 opcode = kThumb2StrhRRI12; 967 } 968 break; 969 case kUnsignedByte: 970 case kSignedByte: 971 if (all_low_regs && displacement < 32 && displacement >= 0) { 972 short_form = true; 973 opcode = kThumbStrbRRI5; 974 } else if (thumb2Form) { 975 short_form = true; 976 opcode = kThumb2StrbRRI12; 977 } 978 break; 979 default: 980 LOG(FATAL) << "Bad size: " << size; 981 } 982 if (!already_generated) { 983 if (short_form) { 984 store = NewLIR3(opcode, r_src, rBase, encoded_disp); 985 } else { 986 int r_scratch = AllocTemp(); 987 LoadConstant(r_scratch, encoded_disp); 988 store = StoreBaseIndexed(rBase, r_scratch, r_src, 0, size); 989 FreeTemp(r_scratch); 990 } 991 } 992 993 // TODO: In future, may need to differentiate Dalvik & spill accesses 994 if (rBase == rARM_SP) { 995 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, is64bit); 996 } 997 return store; 998} 999 1000LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src, 1001 OpSize size) { 1002 return StoreBaseDispBody(rBase, displacement, r_src, -1, size); 1003} 1004 1005LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement, 1006 int r_src_lo, int r_src_hi) { 1007 return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong); 1008} 1009 1010LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) { 1011 int opcode; 1012 DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src)); 1013 if (ARM_DOUBLEREG(r_dest)) { 1014 opcode = kThumb2Vmovd; 1015 } else { 1016 if (ARM_SINGLEREG(r_dest)) { 1017 opcode = ARM_SINGLEREG(r_src) ? kThumb2Vmovs : kThumb2Fmsr; 1018 } else { 1019 DCHECK(ARM_SINGLEREG(r_src)); 1020 opcode = kThumb2Fmrs; 1021 } 1022 } 1023 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 1024 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 1025 res->flags.is_nop = true; 1026 } 1027 return res; 1028} 1029 1030LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) { 1031 LOG(FATAL) << "Unexpected use of OpThreadMem for Arm"; 1032 return NULL; 1033} 1034 1035LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) { 1036 LOG(FATAL) << "Unexpected use of OpMem for Arm"; 1037 return NULL; 1038} 1039 1040LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, 1041 int displacement, int r_src, int r_src_hi, OpSize size, 1042 int s_reg) { 1043 LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm"; 1044 return NULL; 1045} 1046 1047LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) { 1048 LOG(FATAL) << "Unexpected use of OpRegMem for Arm"; 1049 return NULL; 1050} 1051 1052LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, 1053 int displacement, int r_dest, int r_dest_hi, OpSize size, 1054 int s_reg) { 1055 LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm"; 1056 return NULL; 1057} 1058 1059} // namespace art 1060