utility_arm.cc revision 60d7a65f7fb60f502160a2e479e86014c7787553
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "arm_lir.h" 18#include "codegen_arm.h" 19#include "dex/quick/mir_to_lir-inl.h" 20 21namespace art { 22 23/* This file contains codegen for the Thumb ISA. */ 24 25static int32_t EncodeImmSingle(int32_t value) { 26 int32_t res; 27 int32_t bit_a = (value & 0x80000000) >> 31; 28 int32_t not_bit_b = (value & 0x40000000) >> 30; 29 int32_t bit_b = (value & 0x20000000) >> 29; 30 int32_t b_smear = (value & 0x3e000000) >> 25; 31 int32_t slice = (value & 0x01f80000) >> 19; 32 int32_t zeroes = (value & 0x0007ffff); 33 if (zeroes != 0) 34 return -1; 35 if (bit_b) { 36 if ((not_bit_b != 0) || (b_smear != 0x1f)) 37 return -1; 38 } else { 39 if ((not_bit_b != 1) || (b_smear != 0x0)) 40 return -1; 41 } 42 res = (bit_a << 7) | (bit_b << 6) | slice; 43 return res; 44} 45 46/* 47 * Determine whether value can be encoded as a Thumb2 floating point 48 * immediate. If not, return -1. If so return encoded 8-bit value. 49 */ 50static int32_t EncodeImmDouble(int64_t value) { 51 int32_t res; 52 int32_t bit_a = (value & INT64_C(0x8000000000000000)) >> 63; 53 int32_t not_bit_b = (value & INT64_C(0x4000000000000000)) >> 62; 54 int32_t bit_b = (value & INT64_C(0x2000000000000000)) >> 61; 55 int32_t b_smear = (value & INT64_C(0x3fc0000000000000)) >> 54; 56 int32_t slice = (value & INT64_C(0x003f000000000000)) >> 48; 57 uint64_t zeroes = (value & INT64_C(0x0000ffffffffffff)); 58 if (zeroes != 0ull) 59 return -1; 60 if (bit_b) { 61 if ((not_bit_b != 0) || (b_smear != 0xff)) 62 return -1; 63 } else { 64 if ((not_bit_b != 1) || (b_smear != 0x0)) 65 return -1; 66 } 67 res = (bit_a << 7) | (bit_b << 6) | slice; 68 return res; 69} 70 71LIR* ArmMir2Lir::LoadFPConstantValue(int r_dest, int value) { 72 DCHECK(ARM_SINGLEREG(r_dest)); 73 if (value == 0) { 74 // TODO: we need better info about the target CPU. a vector exclusive or 75 // would probably be better here if we could rely on its existance. 76 // Load an immediate +2.0 (which encodes to 0) 77 NewLIR2(kThumb2Vmovs_IMM8, r_dest, 0); 78 // +0.0 = +2.0 - +2.0 79 return NewLIR3(kThumb2Vsubs, r_dest, r_dest, r_dest); 80 } else { 81 int encoded_imm = EncodeImmSingle(value); 82 if (encoded_imm >= 0) { 83 return NewLIR2(kThumb2Vmovs_IMM8, r_dest, encoded_imm); 84 } 85 } 86 LIR* data_target = ScanLiteralPool(literal_list_, value, 0); 87 if (data_target == NULL) { 88 data_target = AddWordData(&literal_list_, value); 89 } 90 LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kThumb2Vldrs, 91 r_dest, r15pc, 0, 0, 0, data_target); 92 SetMemRefType(load_pc_rel, true, kLiteral); 93 AppendLIR(load_pc_rel); 94 return load_pc_rel; 95} 96 97static int LeadingZeros(uint32_t val) { 98 uint32_t alt; 99 int32_t n; 100 int32_t count; 101 102 count = 16; 103 n = 32; 104 do { 105 alt = val >> count; 106 if (alt != 0) { 107 n = n - count; 108 val = alt; 109 } 110 count >>= 1; 111 } while (count); 112 return n - val; 113} 114 115/* 116 * Determine whether value can be encoded as a Thumb2 modified 117 * immediate. If not, return -1. If so, return i:imm3:a:bcdefgh form. 118 */ 119int ArmMir2Lir::ModifiedImmediate(uint32_t value) { 120 int32_t z_leading; 121 int32_t z_trailing; 122 uint32_t b0 = value & 0xff; 123 124 /* Note: case of value==0 must use 0:000:0:0000000 encoding */ 125 if (value <= 0xFF) 126 return b0; // 0:000:a:bcdefgh 127 if (value == ((b0 << 16) | b0)) 128 return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */ 129 if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0)) 130 return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */ 131 b0 = (value >> 8) & 0xff; 132 if (value == ((b0 << 24) | (b0 << 8))) 133 return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */ 134 /* Can we do it with rotation? */ 135 z_leading = LeadingZeros(value); 136 z_trailing = 32 - LeadingZeros(~value & (value - 1)); 137 /* A run of eight or fewer active bits? */ 138 if ((z_leading + z_trailing) < 24) 139 return -1; /* No - bail */ 140 /* left-justify the constant, discarding msb (known to be 1) */ 141 value <<= z_leading + 1; 142 /* Create bcdefgh */ 143 value >>= 25; 144 /* Put it all together */ 145 return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */ 146} 147 148bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) { 149 return (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); 150} 151 152bool ArmMir2Lir::InexpensiveConstantFloat(int32_t value) { 153 return EncodeImmSingle(value) >= 0; 154} 155 156bool ArmMir2Lir::InexpensiveConstantLong(int64_t value) { 157 return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); 158} 159 160bool ArmMir2Lir::InexpensiveConstantDouble(int64_t value) { 161 return EncodeImmDouble(value) >= 0; 162} 163 164/* 165 * Load a immediate using a shortcut if possible; otherwise 166 * grab from the per-translation literal pool. 167 * 168 * No additional register clobbering operation performed. Use this version when 169 * 1) r_dest is freshly returned from AllocTemp or 170 * 2) The codegen is under fixed register usage 171 */ 172LIR* ArmMir2Lir::LoadConstantNoClobber(int r_dest, int value) { 173 LIR* res; 174 int mod_imm; 175 176 if (ARM_FPREG(r_dest)) { 177 return LoadFPConstantValue(r_dest, value); 178 } 179 180 /* See if the value can be constructed cheaply */ 181 if (ARM_LOWREG(r_dest) && (value >= 0) && (value <= 255)) { 182 return NewLIR2(kThumbMovImm, r_dest, value); 183 } 184 /* Check Modified immediate special cases */ 185 mod_imm = ModifiedImmediate(value); 186 if (mod_imm >= 0) { 187 res = NewLIR2(kThumb2MovI8M, r_dest, mod_imm); 188 return res; 189 } 190 mod_imm = ModifiedImmediate(~value); 191 if (mod_imm >= 0) { 192 res = NewLIR2(kThumb2MvnI8M, r_dest, mod_imm); 193 return res; 194 } 195 /* 16-bit immediate? */ 196 if ((value & 0xffff) == value) { 197 res = NewLIR2(kThumb2MovImm16, r_dest, value); 198 return res; 199 } 200 /* Do a low/high pair */ 201 res = NewLIR2(kThumb2MovImm16, r_dest, Low16Bits(value)); 202 NewLIR2(kThumb2MovImm16H, r_dest, High16Bits(value)); 203 return res; 204} 205 206LIR* ArmMir2Lir::OpUnconditionalBranch(LIR* target) { 207 LIR* res = NewLIR1(kThumbBUncond, 0 /* offset to be patched during assembly*/); 208 res->target = target; 209 return res; 210} 211 212LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 213 // This is kThumb2BCond instead of kThumbBCond for performance reasons. The assembly 214 // time required for a new pass after kThumbBCond is fixed up to kThumb2BCond is 215 // substantial. 216 LIR* branch = NewLIR2(kThumb2BCond, 0 /* offset to be patched */, 217 ArmConditionEncoding(cc)); 218 branch->target = target; 219 return branch; 220} 221 222LIR* ArmMir2Lir::OpReg(OpKind op, int r_dest_src) { 223 ArmOpcode opcode = kThumbBkpt; 224 switch (op) { 225 case kOpBlx: 226 opcode = kThumbBlxR; 227 break; 228 case kOpBx: 229 opcode = kThumbBx; 230 break; 231 default: 232 LOG(FATAL) << "Bad opcode " << op; 233 } 234 return NewLIR1(opcode, r_dest_src); 235} 236 237LIR* ArmMir2Lir::OpRegRegShift(OpKind op, int r_dest_src1, int r_src2, 238 int shift) { 239 bool thumb_form = ((shift == 0) && ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)); 240 ArmOpcode opcode = kThumbBkpt; 241 switch (op) { 242 case kOpAdc: 243 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; 244 break; 245 case kOpAnd: 246 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; 247 break; 248 case kOpBic: 249 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; 250 break; 251 case kOpCmn: 252 DCHECK_EQ(shift, 0); 253 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR; 254 break; 255 case kOpCmp: 256 if (thumb_form) 257 opcode = kThumbCmpRR; 258 else if ((shift == 0) && !ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 259 opcode = kThumbCmpHH; 260 else if ((shift == 0) && ARM_LOWREG(r_dest_src1)) 261 opcode = kThumbCmpLH; 262 else if (shift == 0) 263 opcode = kThumbCmpHL; 264 else 265 opcode = kThumb2CmpRR; 266 break; 267 case kOpXor: 268 opcode = (thumb_form) ? kThumbEorRR : kThumb2EorRRR; 269 break; 270 case kOpMov: 271 DCHECK_EQ(shift, 0); 272 if (ARM_LOWREG(r_dest_src1) && ARM_LOWREG(r_src2)) 273 opcode = kThumbMovRR; 274 else if (!ARM_LOWREG(r_dest_src1) && !ARM_LOWREG(r_src2)) 275 opcode = kThumbMovRR_H2H; 276 else if (ARM_LOWREG(r_dest_src1)) 277 opcode = kThumbMovRR_H2L; 278 else 279 opcode = kThumbMovRR_L2H; 280 break; 281 case kOpMul: 282 DCHECK_EQ(shift, 0); 283 opcode = (thumb_form) ? kThumbMul : kThumb2MulRRR; 284 break; 285 case kOpMvn: 286 opcode = (thumb_form) ? kThumbMvn : kThumb2MnvRR; 287 break; 288 case kOpNeg: 289 DCHECK_EQ(shift, 0); 290 opcode = (thumb_form) ? kThumbNeg : kThumb2NegRR; 291 break; 292 case kOpOr: 293 opcode = (thumb_form) ? kThumbOrr : kThumb2OrrRRR; 294 break; 295 case kOpSbc: 296 opcode = (thumb_form) ? kThumbSbc : kThumb2SbcRRR; 297 break; 298 case kOpTst: 299 opcode = (thumb_form) ? kThumbTst : kThumb2TstRR; 300 break; 301 case kOpLsl: 302 DCHECK_EQ(shift, 0); 303 opcode = (thumb_form) ? kThumbLslRR : kThumb2LslRRR; 304 break; 305 case kOpLsr: 306 DCHECK_EQ(shift, 0); 307 opcode = (thumb_form) ? kThumbLsrRR : kThumb2LsrRRR; 308 break; 309 case kOpAsr: 310 DCHECK_EQ(shift, 0); 311 opcode = (thumb_form) ? kThumbAsrRR : kThumb2AsrRRR; 312 break; 313 case kOpRor: 314 DCHECK_EQ(shift, 0); 315 opcode = (thumb_form) ? kThumbRorRR : kThumb2RorRRR; 316 break; 317 case kOpAdd: 318 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 319 break; 320 case kOpSub: 321 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 322 break; 323 case kOpRev: 324 DCHECK_EQ(shift, 0); 325 if (!thumb_form) { 326 // Binary, but rm is encoded twice. 327 return NewLIR3(kThumb2RevRR, r_dest_src1, r_src2, r_src2); 328 } 329 opcode = kThumbRev; 330 break; 331 case kOpRevsh: 332 DCHECK_EQ(shift, 0); 333 if (!thumb_form) { 334 // Binary, but rm is encoded twice. 335 return NewLIR3(kThumb2RevshRR, r_dest_src1, r_src2, r_src2); 336 } 337 opcode = kThumbRevsh; 338 break; 339 case kOp2Byte: 340 DCHECK_EQ(shift, 0); 341 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 8); 342 case kOp2Short: 343 DCHECK_EQ(shift, 0); 344 return NewLIR4(kThumb2Sbfx, r_dest_src1, r_src2, 0, 16); 345 case kOp2Char: 346 DCHECK_EQ(shift, 0); 347 return NewLIR4(kThumb2Ubfx, r_dest_src1, r_src2, 0, 16); 348 default: 349 LOG(FATAL) << "Bad opcode: " << op; 350 break; 351 } 352 DCHECK(!IsPseudoLirOp(opcode)); 353 if (EncodingMap[opcode].flags & IS_BINARY_OP) { 354 return NewLIR2(opcode, r_dest_src1, r_src2); 355 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { 356 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) { 357 return NewLIR3(opcode, r_dest_src1, r_src2, shift); 358 } else { 359 return NewLIR3(opcode, r_dest_src1, r_dest_src1, r_src2); 360 } 361 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { 362 return NewLIR4(opcode, r_dest_src1, r_dest_src1, r_src2, shift); 363 } else { 364 LOG(FATAL) << "Unexpected encoding operand count"; 365 return NULL; 366 } 367} 368 369LIR* ArmMir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) { 370 return OpRegRegShift(op, r_dest_src1, r_src2, 0); 371} 372 373LIR* ArmMir2Lir::OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) { 374 UNIMPLEMENTED(FATAL); 375 return nullptr; 376} 377 378LIR* ArmMir2Lir::OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) { 379 UNIMPLEMENTED(FATAL); 380 return nullptr; 381} 382 383LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) { 384 LOG(FATAL) << "Unexpected use of OpCondRegReg for Arm"; 385 return NULL; 386} 387 388LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1, 389 int r_src2, int shift) { 390 ArmOpcode opcode = kThumbBkpt; 391 bool thumb_form = (shift == 0) && ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1) && 392 ARM_LOWREG(r_src2); 393 switch (op) { 394 case kOpAdd: 395 opcode = (thumb_form) ? kThumbAddRRR : kThumb2AddRRR; 396 break; 397 case kOpSub: 398 opcode = (thumb_form) ? kThumbSubRRR : kThumb2SubRRR; 399 break; 400 case kOpRsub: 401 opcode = kThumb2RsubRRR; 402 break; 403 case kOpAdc: 404 opcode = kThumb2AdcRRR; 405 break; 406 case kOpAnd: 407 opcode = kThumb2AndRRR; 408 break; 409 case kOpBic: 410 opcode = kThumb2BicRRR; 411 break; 412 case kOpXor: 413 opcode = kThumb2EorRRR; 414 break; 415 case kOpMul: 416 DCHECK_EQ(shift, 0); 417 opcode = kThumb2MulRRR; 418 break; 419 case kOpDiv: 420 DCHECK_EQ(shift, 0); 421 opcode = kThumb2SdivRRR; 422 break; 423 case kOpOr: 424 opcode = kThumb2OrrRRR; 425 break; 426 case kOpSbc: 427 opcode = kThumb2SbcRRR; 428 break; 429 case kOpLsl: 430 DCHECK_EQ(shift, 0); 431 opcode = kThumb2LslRRR; 432 break; 433 case kOpLsr: 434 DCHECK_EQ(shift, 0); 435 opcode = kThumb2LsrRRR; 436 break; 437 case kOpAsr: 438 DCHECK_EQ(shift, 0); 439 opcode = kThumb2AsrRRR; 440 break; 441 case kOpRor: 442 DCHECK_EQ(shift, 0); 443 opcode = kThumb2RorRRR; 444 break; 445 default: 446 LOG(FATAL) << "Bad opcode: " << op; 447 break; 448 } 449 DCHECK(!IsPseudoLirOp(opcode)); 450 if (EncodingMap[opcode].flags & IS_QUAD_OP) { 451 return NewLIR4(opcode, r_dest, r_src1, r_src2, shift); 452 } else { 453 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); 454 return NewLIR3(opcode, r_dest, r_src1, r_src2); 455 } 456} 457 458LIR* ArmMir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2) { 459 return OpRegRegRegShift(op, r_dest, r_src1, r_src2, 0); 460} 461 462LIR* ArmMir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src1, int value) { 463 LIR* res; 464 bool neg = (value < 0); 465 int32_t abs_value = (neg) ? -value : value; 466 ArmOpcode opcode = kThumbBkpt; 467 ArmOpcode alt_opcode = kThumbBkpt; 468 bool all_low_regs = (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src1)); 469 int32_t mod_imm = ModifiedImmediate(value); 470 471 switch (op) { 472 case kOpLsl: 473 if (all_low_regs) 474 return NewLIR3(kThumbLslRRI5, r_dest, r_src1, value); 475 else 476 return NewLIR3(kThumb2LslRRI5, r_dest, r_src1, value); 477 case kOpLsr: 478 if (all_low_regs) 479 return NewLIR3(kThumbLsrRRI5, r_dest, r_src1, value); 480 else 481 return NewLIR3(kThumb2LsrRRI5, r_dest, r_src1, value); 482 case kOpAsr: 483 if (all_low_regs) 484 return NewLIR3(kThumbAsrRRI5, r_dest, r_src1, value); 485 else 486 return NewLIR3(kThumb2AsrRRI5, r_dest, r_src1, value); 487 case kOpRor: 488 return NewLIR3(kThumb2RorRRI5, r_dest, r_src1, value); 489 case kOpAdd: 490 if (ARM_LOWREG(r_dest) && (r_src1 == r13sp) && 491 (value <= 1020) && ((value & 0x3) == 0)) { 492 return NewLIR3(kThumbAddSpRel, r_dest, r_src1, value >> 2); 493 } else if (ARM_LOWREG(r_dest) && (r_src1 == r15pc) && 494 (value <= 1020) && ((value & 0x3) == 0)) { 495 return NewLIR3(kThumbAddPcRel, r_dest, r_src1, value >> 2); 496 } 497 // Note: intentional fallthrough 498 case kOpSub: 499 if (all_low_regs && ((abs_value & 0x7) == abs_value)) { 500 if (op == kOpAdd) 501 opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; 502 else 503 opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; 504 return NewLIR3(opcode, r_dest, r_src1, abs_value); 505 } 506 if (mod_imm < 0) { 507 mod_imm = ModifiedImmediate(-value); 508 if (mod_imm >= 0) { 509 op = (op == kOpAdd) ? kOpSub : kOpAdd; 510 } 511 } 512 if (mod_imm < 0 && (abs_value & 0x3ff) == abs_value) { 513 // This is deliberately used only if modified immediate encoding is inadequate since 514 // we sometimes actually use the flags for small values but not necessarily low regs. 515 if (op == kOpAdd) 516 opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; 517 else 518 opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; 519 return NewLIR3(opcode, r_dest, r_src1, abs_value); 520 } 521 if (op == kOpSub) { 522 opcode = kThumb2SubRRI8M; 523 alt_opcode = kThumb2SubRRR; 524 } else { 525 opcode = kThumb2AddRRI8M; 526 alt_opcode = kThumb2AddRRR; 527 } 528 break; 529 case kOpRsub: 530 opcode = kThumb2RsubRRI8M; 531 alt_opcode = kThumb2RsubRRR; 532 break; 533 case kOpAdc: 534 opcode = kThumb2AdcRRI8M; 535 alt_opcode = kThumb2AdcRRR; 536 break; 537 case kOpSbc: 538 opcode = kThumb2SbcRRI8M; 539 alt_opcode = kThumb2SbcRRR; 540 break; 541 case kOpOr: 542 opcode = kThumb2OrrRRI8M; 543 alt_opcode = kThumb2OrrRRR; 544 break; 545 case kOpAnd: 546 if (mod_imm < 0) { 547 mod_imm = ModifiedImmediate(~value); 548 if (mod_imm >= 0) { 549 return NewLIR3(kThumb2BicRRI8M, r_dest, r_src1, mod_imm); 550 } 551 } 552 opcode = kThumb2AndRRI8M; 553 alt_opcode = kThumb2AndRRR; 554 break; 555 case kOpXor: 556 opcode = kThumb2EorRRI8M; 557 alt_opcode = kThumb2EorRRR; 558 break; 559 case kOpMul: 560 // TUNING: power of 2, shift & add 561 mod_imm = -1; 562 alt_opcode = kThumb2MulRRR; 563 break; 564 case kOpCmp: { 565 LIR* res; 566 if (mod_imm >= 0) { 567 res = NewLIR2(kThumb2CmpRI8M, r_src1, mod_imm); 568 } else { 569 mod_imm = ModifiedImmediate(-value); 570 if (mod_imm >= 0) { 571 res = NewLIR2(kThumb2CmnRI8M, r_src1, mod_imm); 572 } else { 573 int r_tmp = AllocTemp(); 574 res = LoadConstant(r_tmp, value); 575 OpRegReg(kOpCmp, r_src1, r_tmp); 576 FreeTemp(r_tmp); 577 } 578 } 579 return res; 580 } 581 default: 582 LOG(FATAL) << "Bad opcode: " << op; 583 } 584 585 if (mod_imm >= 0) { 586 return NewLIR3(opcode, r_dest, r_src1, mod_imm); 587 } else { 588 int r_scratch = AllocTemp(); 589 LoadConstant(r_scratch, value); 590 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) 591 res = NewLIR4(alt_opcode, r_dest, r_src1, r_scratch, 0); 592 else 593 res = NewLIR3(alt_opcode, r_dest, r_src1, r_scratch); 594 FreeTemp(r_scratch); 595 return res; 596 } 597} 598 599/* Handle Thumb-only variants here - otherwise punt to OpRegRegImm */ 600LIR* ArmMir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) { 601 bool neg = (value < 0); 602 int32_t abs_value = (neg) ? -value : value; 603 bool short_form = (((abs_value & 0xff) == abs_value) && ARM_LOWREG(r_dest_src1)); 604 ArmOpcode opcode = kThumbBkpt; 605 switch (op) { 606 case kOpAdd: 607 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 608 DCHECK_EQ((value & 0x3), 0); 609 return NewLIR1(kThumbAddSpI7, value >> 2); 610 } else if (short_form) { 611 opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; 612 } 613 break; 614 case kOpSub: 615 if (!neg && (r_dest_src1 == r13sp) && (value <= 508)) { /* sp */ 616 DCHECK_EQ((value & 0x3), 0); 617 return NewLIR1(kThumbSubSpI7, value >> 2); 618 } else if (short_form) { 619 opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; 620 } 621 break; 622 case kOpCmp: 623 if (!neg && short_form) { 624 opcode = kThumbCmpRI8; 625 } else { 626 short_form = false; 627 } 628 break; 629 default: 630 /* Punt to OpRegRegImm - if bad case catch it there */ 631 short_form = false; 632 break; 633 } 634 if (short_form) { 635 return NewLIR2(opcode, r_dest_src1, abs_value); 636 } else { 637 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); 638 } 639} 640 641LIR* ArmMir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) { 642 LIR* res = NULL; 643 int32_t val_lo = Low32Bits(value); 644 int32_t val_hi = High32Bits(value); 645 int target_reg = S2d(r_dest_lo, r_dest_hi); 646 if (ARM_FPREG(r_dest_lo)) { 647 if ((val_lo == 0) && (val_hi == 0)) { 648 // TODO: we need better info about the target CPU. a vector exclusive or 649 // would probably be better here if we could rely on its existance. 650 // Load an immediate +2.0 (which encodes to 0) 651 NewLIR2(kThumb2Vmovd_IMM8, target_reg, 0); 652 // +0.0 = +2.0 - +2.0 653 res = NewLIR3(kThumb2Vsubd, target_reg, target_reg, target_reg); 654 } else { 655 int encoded_imm = EncodeImmDouble(value); 656 if (encoded_imm >= 0) { 657 res = NewLIR2(kThumb2Vmovd_IMM8, target_reg, encoded_imm); 658 } 659 } 660 } else { 661 if ((InexpensiveConstantInt(val_lo) && (InexpensiveConstantInt(val_hi)))) { 662 res = LoadConstantNoClobber(r_dest_lo, val_lo); 663 LoadConstantNoClobber(r_dest_hi, val_hi); 664 } 665 } 666 if (res == NULL) { 667 // No short form - load from the literal pool. 668 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 669 if (data_target == NULL) { 670 data_target = AddWideData(&literal_list_, val_lo, val_hi); 671 } 672 if (ARM_FPREG(r_dest_lo)) { 673 res = RawLIR(current_dalvik_offset_, kThumb2Vldrd, 674 target_reg, r15pc, 0, 0, 0, data_target); 675 } else { 676 res = RawLIR(current_dalvik_offset_, kThumb2LdrdPcRel8, 677 r_dest_lo, r_dest_hi, r15pc, 0, 0, data_target); 678 } 679 SetMemRefType(res, true, kLiteral); 680 AppendLIR(res); 681 } 682 return res; 683} 684 685int ArmMir2Lir::EncodeShift(int code, int amount) { 686 return ((amount & 0x1f) << 2) | code; 687} 688 689LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, 690 int scale, OpSize size) { 691 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest); 692 LIR* load; 693 ArmOpcode opcode = kThumbBkpt; 694 bool thumb_form = (all_low_regs && (scale == 0)); 695 int reg_ptr; 696 697 if (ARM_FPREG(r_dest)) { 698 if (ARM_SINGLEREG(r_dest)) { 699 DCHECK((size == kWord) || (size == kSingle)); 700 opcode = kThumb2Vldrs; 701 size = kSingle; 702 } else { 703 DCHECK(ARM_DOUBLEREG(r_dest)); 704 DCHECK((size == kLong) || (size == kDouble)); 705 DCHECK_EQ((r_dest & 0x1), 0); 706 opcode = kThumb2Vldrd; 707 size = kDouble; 708 } 709 } else { 710 if (size == kSingle) 711 size = kWord; 712 } 713 714 switch (size) { 715 case kDouble: // fall-through 716 case kSingle: 717 reg_ptr = AllocTemp(); 718 if (scale) { 719 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 720 EncodeShift(kArmLsl, scale)); 721 } else { 722 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 723 } 724 load = NewLIR3(opcode, r_dest, reg_ptr, 0); 725 FreeTemp(reg_ptr); 726 return load; 727 case kWord: 728 opcode = (thumb_form) ? kThumbLdrRRR : kThumb2LdrRRR; 729 break; 730 case kUnsignedHalf: 731 opcode = (thumb_form) ? kThumbLdrhRRR : kThumb2LdrhRRR; 732 break; 733 case kSignedHalf: 734 opcode = (thumb_form) ? kThumbLdrshRRR : kThumb2LdrshRRR; 735 break; 736 case kUnsignedByte: 737 opcode = (thumb_form) ? kThumbLdrbRRR : kThumb2LdrbRRR; 738 break; 739 case kSignedByte: 740 opcode = (thumb_form) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; 741 break; 742 default: 743 LOG(FATAL) << "Bad size: " << size; 744 } 745 if (thumb_form) 746 load = NewLIR3(opcode, r_dest, rBase, r_index); 747 else 748 load = NewLIR4(opcode, r_dest, rBase, r_index, scale); 749 750 return load; 751} 752 753LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, 754 int scale, OpSize size) { 755 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 756 LIR* store = NULL; 757 ArmOpcode opcode = kThumbBkpt; 758 bool thumb_form = (all_low_regs && (scale == 0)); 759 int reg_ptr; 760 761 if (ARM_FPREG(r_src)) { 762 if (ARM_SINGLEREG(r_src)) { 763 DCHECK((size == kWord) || (size == kSingle)); 764 opcode = kThumb2Vstrs; 765 size = kSingle; 766 } else { 767 DCHECK(ARM_DOUBLEREG(r_src)); 768 DCHECK((size == kLong) || (size == kDouble)); 769 DCHECK_EQ((r_src & 0x1), 0); 770 opcode = kThumb2Vstrd; 771 size = kDouble; 772 } 773 } else { 774 if (size == kSingle) 775 size = kWord; 776 } 777 778 switch (size) { 779 case kDouble: // fall-through 780 case kSingle: 781 reg_ptr = AllocTemp(); 782 if (scale) { 783 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 784 EncodeShift(kArmLsl, scale)); 785 } else { 786 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 787 } 788 store = NewLIR3(opcode, r_src, reg_ptr, 0); 789 FreeTemp(reg_ptr); 790 return store; 791 case kWord: 792 opcode = (thumb_form) ? kThumbStrRRR : kThumb2StrRRR; 793 break; 794 case kUnsignedHalf: 795 case kSignedHalf: 796 opcode = (thumb_form) ? kThumbStrhRRR : kThumb2StrhRRR; 797 break; 798 case kUnsignedByte: 799 case kSignedByte: 800 opcode = (thumb_form) ? kThumbStrbRRR : kThumb2StrbRRR; 801 break; 802 default: 803 LOG(FATAL) << "Bad size: " << size; 804 } 805 if (thumb_form) 806 store = NewLIR3(opcode, r_src, rBase, r_index); 807 else 808 store = NewLIR4(opcode, r_src, rBase, r_index, scale); 809 810 return store; 811} 812 813/* 814 * Load value from base + displacement. Optionally perform null check 815 * on base (which must have an associated s_reg and MIR). If not 816 * performing null check, incoming MIR can be null. 817 */ 818LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, 819 int r_dest_hi, OpSize size, int s_reg) { 820 LIR* load = NULL; 821 ArmOpcode opcode = kThumbBkpt; 822 bool short_form = false; 823 bool thumb2Form = (displacement < 4092 && displacement >= 0); 824 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_dest)); 825 int encoded_disp = displacement; 826 bool is64bit = false; 827 bool already_generated = false; 828 switch (size) { 829 case kDouble: 830 case kLong: 831 is64bit = true; 832 if (ARM_FPREG(r_dest)) { 833 if (ARM_SINGLEREG(r_dest)) { 834 DCHECK(ARM_FPREG(r_dest_hi)); 835 r_dest = S2d(r_dest, r_dest_hi); 836 } 837 opcode = kThumb2Vldrd; 838 if (displacement <= 1020) { 839 short_form = true; 840 encoded_disp >>= 2; 841 } 842 break; 843 } else { 844 if (displacement <= 1020) { 845 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2); 846 } else { 847 load = LoadBaseDispBody(rBase, displacement, r_dest, 848 -1, kWord, s_reg); 849 LoadBaseDispBody(rBase, displacement + 4, r_dest_hi, 850 -1, kWord, INVALID_SREG); 851 } 852 already_generated = true; 853 } 854 case kSingle: 855 case kWord: 856 if (ARM_FPREG(r_dest)) { 857 opcode = kThumb2Vldrs; 858 if (displacement <= 1020) { 859 short_form = true; 860 encoded_disp >>= 2; 861 } 862 break; 863 } 864 if (ARM_LOWREG(r_dest) && (rBase == r15pc) && 865 (displacement <= 1020) && (displacement >= 0)) { 866 short_form = true; 867 encoded_disp >>= 2; 868 opcode = kThumbLdrPcRel; 869 } else if (ARM_LOWREG(r_dest) && (rBase == r13sp) && 870 (displacement <= 1020) && (displacement >= 0)) { 871 short_form = true; 872 encoded_disp >>= 2; 873 opcode = kThumbLdrSpRel; 874 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 875 DCHECK_EQ((displacement & 0x3), 0); 876 short_form = true; 877 encoded_disp >>= 2; 878 opcode = kThumbLdrRRI5; 879 } else if (thumb2Form) { 880 short_form = true; 881 opcode = kThumb2LdrRRI12; 882 } 883 break; 884 case kUnsignedHalf: 885 if (all_low_regs && displacement < 64 && displacement >= 0) { 886 DCHECK_EQ((displacement & 0x1), 0); 887 short_form = true; 888 encoded_disp >>= 1; 889 opcode = kThumbLdrhRRI5; 890 } else if (displacement < 4092 && displacement >= 0) { 891 short_form = true; 892 opcode = kThumb2LdrhRRI12; 893 } 894 break; 895 case kSignedHalf: 896 if (thumb2Form) { 897 short_form = true; 898 opcode = kThumb2LdrshRRI12; 899 } 900 break; 901 case kUnsignedByte: 902 if (all_low_regs && displacement < 32 && displacement >= 0) { 903 short_form = true; 904 opcode = kThumbLdrbRRI5; 905 } else if (thumb2Form) { 906 short_form = true; 907 opcode = kThumb2LdrbRRI12; 908 } 909 break; 910 case kSignedByte: 911 if (thumb2Form) { 912 short_form = true; 913 opcode = kThumb2LdrsbRRI12; 914 } 915 break; 916 default: 917 LOG(FATAL) << "Bad size: " << size; 918 } 919 920 if (!already_generated) { 921 if (short_form) { 922 load = NewLIR3(opcode, r_dest, rBase, encoded_disp); 923 } else { 924 int reg_offset = AllocTemp(); 925 LoadConstant(reg_offset, encoded_disp); 926 load = LoadBaseIndexed(rBase, reg_offset, r_dest, 0, size); 927 FreeTemp(reg_offset); 928 } 929 } 930 931 // TODO: in future may need to differentiate Dalvik accesses w/ spills 932 if (rBase == rARM_SP) { 933 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, is64bit); 934 } 935 return load; 936} 937 938LIR* ArmMir2Lir::LoadBaseDisp(int rBase, int displacement, int r_dest, 939 OpSize size, int s_reg) { 940 return LoadBaseDispBody(rBase, displacement, r_dest, -1, size, s_reg); 941} 942 943LIR* ArmMir2Lir::LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, 944 int r_dest_hi, int s_reg) { 945 return LoadBaseDispBody(rBase, displacement, r_dest_lo, r_dest_hi, kLong, s_reg); 946} 947 948 949LIR* ArmMir2Lir::StoreBaseDispBody(int rBase, int displacement, 950 int r_src, int r_src_hi, OpSize size) { 951 LIR* store = NULL; 952 ArmOpcode opcode = kThumbBkpt; 953 bool short_form = false; 954 bool thumb2Form = (displacement < 4092 && displacement >= 0); 955 bool all_low_regs = (ARM_LOWREG(rBase) && ARM_LOWREG(r_src)); 956 int encoded_disp = displacement; 957 bool is64bit = false; 958 bool already_generated = false; 959 switch (size) { 960 case kLong: 961 case kDouble: 962 is64bit = true; 963 if (!ARM_FPREG(r_src)) { 964 if (displacement <= 1020) { 965 store = NewLIR4(kThumb2StrdI8, r_src, r_src_hi, rBase, displacement >> 2); 966 } else { 967 store = StoreBaseDispBody(rBase, displacement, r_src, -1, kWord); 968 StoreBaseDispBody(rBase, displacement + 4, r_src_hi, -1, kWord); 969 } 970 already_generated = true; 971 } else { 972 if (ARM_SINGLEREG(r_src)) { 973 DCHECK(ARM_FPREG(r_src_hi)); 974 r_src = S2d(r_src, r_src_hi); 975 } 976 opcode = kThumb2Vstrd; 977 if (displacement <= 1020) { 978 short_form = true; 979 encoded_disp >>= 2; 980 } 981 } 982 break; 983 case kSingle: 984 case kWord: 985 if (ARM_FPREG(r_src)) { 986 DCHECK(ARM_SINGLEREG(r_src)); 987 opcode = kThumb2Vstrs; 988 if (displacement <= 1020) { 989 short_form = true; 990 encoded_disp >>= 2; 991 } 992 break; 993 } 994 if (ARM_LOWREG(r_src) && (rBase == r13sp) && 995 (displacement <= 1020) && (displacement >= 0)) { 996 short_form = true; 997 encoded_disp >>= 2; 998 opcode = kThumbStrSpRel; 999 } else if (all_low_regs && displacement < 128 && displacement >= 0) { 1000 DCHECK_EQ((displacement & 0x3), 0); 1001 short_form = true; 1002 encoded_disp >>= 2; 1003 opcode = kThumbStrRRI5; 1004 } else if (thumb2Form) { 1005 short_form = true; 1006 opcode = kThumb2StrRRI12; 1007 } 1008 break; 1009 case kUnsignedHalf: 1010 case kSignedHalf: 1011 if (all_low_regs && displacement < 64 && displacement >= 0) { 1012 DCHECK_EQ((displacement & 0x1), 0); 1013 short_form = true; 1014 encoded_disp >>= 1; 1015 opcode = kThumbStrhRRI5; 1016 } else if (thumb2Form) { 1017 short_form = true; 1018 opcode = kThumb2StrhRRI12; 1019 } 1020 break; 1021 case kUnsignedByte: 1022 case kSignedByte: 1023 if (all_low_regs && displacement < 32 && displacement >= 0) { 1024 short_form = true; 1025 opcode = kThumbStrbRRI5; 1026 } else if (thumb2Form) { 1027 short_form = true; 1028 opcode = kThumb2StrbRRI12; 1029 } 1030 break; 1031 default: 1032 LOG(FATAL) << "Bad size: " << size; 1033 } 1034 if (!already_generated) { 1035 if (short_form) { 1036 store = NewLIR3(opcode, r_src, rBase, encoded_disp); 1037 } else { 1038 int r_scratch = AllocTemp(); 1039 LoadConstant(r_scratch, encoded_disp); 1040 store = StoreBaseIndexed(rBase, r_scratch, r_src, 0, size); 1041 FreeTemp(r_scratch); 1042 } 1043 } 1044 1045 // TODO: In future, may need to differentiate Dalvik & spill accesses 1046 if (rBase == rARM_SP) { 1047 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, is64bit); 1048 } 1049 return store; 1050} 1051 1052LIR* ArmMir2Lir::StoreBaseDisp(int rBase, int displacement, int r_src, 1053 OpSize size) { 1054 return StoreBaseDispBody(rBase, displacement, r_src, -1, size); 1055} 1056 1057LIR* ArmMir2Lir::StoreBaseDispWide(int rBase, int displacement, 1058 int r_src_lo, int r_src_hi) { 1059 return StoreBaseDispBody(rBase, displacement, r_src_lo, r_src_hi, kLong); 1060} 1061 1062LIR* ArmMir2Lir::OpFpRegCopy(int r_dest, int r_src) { 1063 int opcode; 1064 DCHECK_EQ(ARM_DOUBLEREG(r_dest), ARM_DOUBLEREG(r_src)); 1065 if (ARM_DOUBLEREG(r_dest)) { 1066 opcode = kThumb2Vmovd; 1067 } else { 1068 if (ARM_SINGLEREG(r_dest)) { 1069 opcode = ARM_SINGLEREG(r_src) ? kThumb2Vmovs : kThumb2Fmsr; 1070 } else { 1071 DCHECK(ARM_SINGLEREG(r_src)); 1072 opcode = kThumb2Fmrs; 1073 } 1074 } 1075 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); 1076 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 1077 res->flags.is_nop = true; 1078 } 1079 return res; 1080} 1081 1082LIR* ArmMir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) { 1083 LOG(FATAL) << "Unexpected use of OpThreadMem for Arm"; 1084 return NULL; 1085} 1086 1087LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) { 1088 LOG(FATAL) << "Unexpected use of OpMem for Arm"; 1089 return NULL; 1090} 1091 1092LIR* ArmMir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale, 1093 int displacement, int r_src, int r_src_hi, OpSize size, 1094 int s_reg) { 1095 LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm"; 1096 return NULL; 1097} 1098 1099LIR* ArmMir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, int offset) { 1100 LOG(FATAL) << "Unexpected use of OpRegMem for Arm"; 1101 return NULL; 1102} 1103 1104LIR* ArmMir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, 1105 int displacement, int r_dest, int r_dest_hi, OpSize size, 1106 int s_reg) { 1107 LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm"; 1108 return NULL; 1109} 1110 1111} // namespace art 1112