codegen_arm64.h revision 7c1c263f3227169e055200cc481c022f1cf37213
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 18#define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 19 20#include "arm64_lir.h" 21#include "dex/compiler_internals.h" 22 23#include <map> 24 25namespace art { 26 27class Arm64Mir2Lir : public Mir2Lir { 28 protected: 29 // TODO: consolidate 64-bit target support. 30 class InToRegStorageMapper { 31 public: 32 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide) = 0; 33 virtual ~InToRegStorageMapper() {} 34 }; 35 36 class InToRegStorageArm64Mapper : public InToRegStorageMapper { 37 public: 38 InToRegStorageArm64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} 39 virtual ~InToRegStorageArm64Mapper() {} 40 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide); 41 private: 42 int cur_core_reg_; 43 int cur_fp_reg_; 44 }; 45 46 class InToRegStorageMapping { 47 public: 48 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 49 initialized_(false) {} 50 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 51 int GetMaxMappedIn() { return max_mapped_in_; } 52 bool IsThereStackMapped() { return is_there_stack_mapped_; } 53 RegStorage Get(int in_position); 54 bool IsInitialized() { return initialized_; } 55 private: 56 std::map<int, RegStorage> mapping_; 57 int max_mapped_in_; 58 bool is_there_stack_mapped_; 59 bool initialized_; 60 }; 61 62 public: 63 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 64 65 // Required for target - codegen helpers. 66 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 67 RegLocation rl_dest, int lit); 68 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 69 LIR* CheckSuspendUsingLoad() OVERRIDE; 70 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 71 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 72 LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 73 OpSize size) OVERRIDE; 74 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 75 OpSize size) OVERRIDE; 76 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 77 OpSize size) OVERRIDE; 78 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 79 RegStorage r_dest, OpSize size) OVERRIDE; 80 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 81 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 82 LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 83 OpSize size) OVERRIDE; 84 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 85 OpSize size) OVERRIDE; 86 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 87 OpSize size) OVERRIDE; 88 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 89 RegStorage r_src, OpSize size) OVERRIDE; 90 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 91 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 92 int offset, int check_value, LIR* target) OVERRIDE; 93 94 // Required for target - register utilities. 95 RegStorage TargetReg(SpecialTargetRegister reg); 96 RegStorage GetArgMappingToPhysicalReg(int arg_num); 97 RegLocation GetReturnAlt(); 98 RegLocation GetReturnWideAlt(); 99 RegLocation LocCReturn(); 100 RegLocation LocCReturnRef(); 101 RegLocation LocCReturnDouble(); 102 RegLocation LocCReturnFloat(); 103 RegLocation LocCReturnWide(); 104 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 105 void AdjustSpillMask(); 106 void ClobberCallerSave(); 107 void FreeCallTemps(); 108 void LockCallTemps(); 109 void MarkPreservedSingle(int v_reg, RegStorage reg); 110 void MarkPreservedDouble(int v_reg, RegStorage reg); 111 void CompilerInitializeRegAlloc(); 112 113 // Required for target - miscellaneous. 114 void AssembleLIR(); 115 uint32_t LinkFixupInsns(LIR* head_lir, LIR* tail_lir, CodeOffset offset); 116 int AssignInsnOffsets(); 117 void AssignOffsets(); 118 uint8_t* EncodeLIRs(uint8_t* write_pos, LIR* lir); 119 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 120 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 121 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 122 const char* GetTargetInstFmt(int opcode); 123 const char* GetTargetInstName(int opcode); 124 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 125 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 126 uint64_t GetTargetInstFlags(int opcode); 127 size_t GetInsnSize(LIR* lir) OVERRIDE; 128 bool IsUnconditionalBranch(LIR* lir); 129 130 // Check support for volatile load/store of a given size. 131 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 132 // Get the register class for load/store of a field. 133 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 134 135 // Required for target - Dalvik-level generators. 136 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 137 RegLocation lr_shift); 138 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 139 RegLocation rl_src1, RegLocation rl_src2); 140 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 141 RegLocation rl_index, RegLocation rl_dest, int scale); 142 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 143 RegLocation rl_src, int scale, bool card_mark); 144 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 145 RegLocation rl_src1, RegLocation rl_shift); 146 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 147 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 148 RegLocation rl_src2); 149 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 150 RegLocation rl_src2); 151 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 152 RegLocation rl_src2); 153 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 154 RegLocation rl_src2); 155 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 156 RegLocation rl_src2); 157 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 158 RegLocation rl_src2); 159 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 160 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 161 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 162 bool GenInlinedSqrt(CallInfo* info); 163 bool GenInlinedPeek(CallInfo* info, OpSize size); 164 bool GenInlinedPoke(CallInfo* info, OpSize size); 165 bool GenInlinedAbsLong(CallInfo* info); 166 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 167 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 168 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 169 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 170 RegLocation rl_src2); 171 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 172 RegLocation rl_src2); 173 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 174 RegLocation rl_src2); 175 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 176 RegLocation rl_src2, bool is_div); 177 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 178 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 179 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 180 void GenDivZeroCheckWide(RegStorage reg); 181 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 182 void GenExitSequence(); 183 void GenSpecialExitSequence(); 184 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 185 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 186 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 187 void GenSelect(BasicBlock* bb, MIR* mir); 188 bool GenMemBarrier(MemBarrierKind barrier_kind); 189 void GenMonitorEnter(int opt_flags, RegLocation rl_src); 190 void GenMonitorExit(int opt_flags, RegLocation rl_src); 191 void GenMoveException(RegLocation rl_dest); 192 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 193 int first_bit, int second_bit); 194 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 195 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 196 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 197 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 198 bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 199 200 uint32_t GenPairWise(uint32_t reg_mask, int* reg1, int* reg2); 201 void UnSpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 202 void SpillCoreRegs(RegStorage base, int offset, uint32_t reg_mask); 203 void UnSpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 204 void SpillFPRegs(RegStorage base, int offset, uint32_t reg_mask); 205 206 // Required for target - single operation generators. 207 LIR* OpUnconditionalBranch(LIR* target); 208 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 209 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 210 LIR* OpCondBranch(ConditionCode cc, LIR* target); 211 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 212 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 213 LIR* OpIT(ConditionCode cond, const char* guide); 214 void OpEndIT(LIR* it); 215 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 216 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 217 LIR* OpReg(OpKind op, RegStorage r_dest_src); 218 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 219 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 220 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value); 221 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 222 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 223 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 224 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 225 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 226 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 227 LIR* OpRegRegImm64(OpKind op, RegStorage r_dest, RegStorage r_src1, int64_t value); 228 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 229 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 230 LIR* OpTestSuspend(LIR* target); 231 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 232 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 233 LIR* OpVldm(RegStorage r_base, int count); 234 LIR* OpVstm(RegStorage r_base, int count); 235 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 236 void OpRegCopyWide(RegStorage dest, RegStorage src); 237 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 238 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 239 240 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size); 241 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 242 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2, 243 int shift); 244 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 245 LIR* OpRegRegExtend(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift); 246 static const ArmEncodingMap EncodingMap[kA64Last]; 247 int EncodeShift(int code, int amount); 248 int EncodeExtend(int extend_type, int amount); 249 bool IsExtendEncoding(int encoded_value); 250 int EncodeLogicalImmediate(bool is_wide, uint64_t value); 251 uint64_t DecodeLogicalImmediate(bool is_wide, int value); 252 253 ArmConditionCode ArmConditionEncoding(ConditionCode code); 254 bool InexpensiveConstantInt(int32_t value); 255 bool InexpensiveConstantFloat(int32_t value); 256 bool InexpensiveConstantLong(int64_t value); 257 bool InexpensiveConstantDouble(int64_t value); 258 259 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 260 261 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 262 NextCallInsn next_call_insn, 263 const MethodReference& target_method, 264 uint32_t vtable_idx, 265 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 266 bool skip_this); 267 268 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 269 NextCallInsn next_call_insn, 270 const MethodReference& target_method, 271 uint32_t vtable_idx, 272 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 273 bool skip_this); 274 InToRegStorageMapping in_to_reg_storage_mapping_; 275 276 private: 277 /** 278 * @brief Given register xNN (dNN), returns register wNN (sNN). 279 * @param reg #RegStorage containing a Solo64 input register (e.g. @c x1 or @c d2). 280 * @return A Solo32 with the same register number as the @p reg (e.g. @c w1 or @c s2). 281 * @see As64BitReg 282 */ 283 RegStorage As32BitReg(RegStorage reg) { 284 DCHECK(reg.Is64Bit()); 285 DCHECK(!reg.IsPair()); 286 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 287 reg.GetRawBits() & RegStorage::kRegTypeMask); 288 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 289 ->GetReg().GetReg(), 290 ret_val.GetReg()); 291 return ret_val; 292 } 293 294 /** 295 * @brief Given register wNN (sNN), returns register xNN (dNN). 296 * @param reg #RegStorage containing a Solo32 input register (e.g. @c w1 or @c s2). 297 * @return A Solo64 with the same register number as the @p reg (e.g. @c x1 or @c d2). 298 * @see As32BitReg 299 */ 300 RegStorage As64BitReg(RegStorage reg) { 301 DCHECK(reg.Is32Bit()); 302 DCHECK(!reg.IsPair()); 303 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 304 reg.GetRawBits() & RegStorage::kRegTypeMask); 305 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 306 ->GetReg().GetReg(), 307 ret_val.GetReg()); 308 return ret_val; 309 } 310 311 LIR* LoadFPConstantValue(RegStorage r_dest, int32_t value); 312 LIR* LoadFPConstantValueWide(RegStorage r_dest, int64_t value); 313 void ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 314 void InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir); 315 void AssignDataOffsets(); 316 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 317 bool is_div, bool check_zero); 318 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div); 319}; 320 321} // namespace art 322 323#endif // ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ 324