target_arm64.cc revision 69dfe51b684dd9d510dbcb63295fe180f998efde
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_arm64.h" 18 19#include <inttypes.h> 20 21#include <string> 22 23#include "dex/compiler_internals.h" 24#include "dex/quick/mir_to_lir-inl.h" 25#include "dex/reg_storage_eq.h" 26 27namespace art { 28 29static constexpr RegStorage core_regs_arr[] = 30 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 31 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, 32 rs_w16, rs_w17, rs_w18, rs_w19, rs_w20, rs_w21, rs_w22, rs_w23, 33 rs_w24, rs_w25, rs_w26, rs_w27, rs_w28, rs_w29, rs_w30, rs_w31, 34 rs_wzr}; 35static constexpr RegStorage core64_regs_arr[] = 36 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 37 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, 38 rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, 39 rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31, 40 rs_xzr}; 41static constexpr RegStorage sp_regs_arr[] = 42 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 43 rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, 44 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 45 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 46static constexpr RegStorage dp_regs_arr[] = 47 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 48 rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15, 49 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 50 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 51static constexpr RegStorage reserved_regs_arr[] = 52 {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr}; 53static constexpr RegStorage reserved64_regs_arr[] = 54 {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr}; 55// TUNING: Are there too many temp registers and too less promote target? 56// This definition need to be matched with runtime.cc, quick entry assembly and JNI compiler 57// Note: we are not able to call to C function directly if it un-match C ABI. 58// Currently, rs_rA64_SELF is not a callee save register which does not match C ABI. 59static constexpr RegStorage core_temps_arr[] = 60 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 61 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16, 62 rs_w17}; 63static constexpr RegStorage core64_temps_arr[] = 64 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 65 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16, 66 rs_x17}; 67static constexpr RegStorage sp_temps_arr[] = 68 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 69 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 70 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 71static constexpr RegStorage dp_temps_arr[] = 72 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 73 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 74 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 75 76static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr); 77static constexpr ArrayRef<const RegStorage> core64_regs(core64_regs_arr); 78static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr); 79static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr); 80static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr); 81static constexpr ArrayRef<const RegStorage> reserved64_regs(reserved64_regs_arr); 82static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr); 83static constexpr ArrayRef<const RegStorage> core64_temps(core64_temps_arr); 84static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr); 85static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr); 86 87RegLocation Arm64Mir2Lir::LocCReturn() { 88 return arm_loc_c_return; 89} 90 91RegLocation Arm64Mir2Lir::LocCReturnRef() { 92 return arm_loc_c_return_ref; 93} 94 95RegLocation Arm64Mir2Lir::LocCReturnWide() { 96 return arm_loc_c_return_wide; 97} 98 99RegLocation Arm64Mir2Lir::LocCReturnFloat() { 100 return arm_loc_c_return_float; 101} 102 103RegLocation Arm64Mir2Lir::LocCReturnDouble() { 104 return arm_loc_c_return_double; 105} 106 107// Return a target-dependent special register. 108RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { 109 RegStorage res_reg = RegStorage::InvalidReg(); 110 switch (reg) { 111 case kSelf: res_reg = rs_wSELF; break; 112 case kSuspend: res_reg = rs_wSUSPEND; break; 113 case kLr: res_reg = rs_wLR; break; 114 case kPc: res_reg = RegStorage::InvalidReg(); break; 115 case kSp: res_reg = rs_wsp; break; 116 case kArg0: res_reg = rs_w0; break; 117 case kArg1: res_reg = rs_w1; break; 118 case kArg2: res_reg = rs_w2; break; 119 case kArg3: res_reg = rs_w3; break; 120 case kArg4: res_reg = rs_w4; break; 121 case kArg5: res_reg = rs_w5; break; 122 case kArg6: res_reg = rs_w6; break; 123 case kArg7: res_reg = rs_w7; break; 124 case kFArg0: res_reg = rs_f0; break; 125 case kFArg1: res_reg = rs_f1; break; 126 case kFArg2: res_reg = rs_f2; break; 127 case kFArg3: res_reg = rs_f3; break; 128 case kFArg4: res_reg = rs_f4; break; 129 case kFArg5: res_reg = rs_f5; break; 130 case kFArg6: res_reg = rs_f6; break; 131 case kFArg7: res_reg = rs_f7; break; 132 case kRet0: res_reg = rs_w0; break; 133 case kRet1: res_reg = rs_w1; break; 134 case kInvokeTgt: res_reg = rs_wLR; break; 135 case kHiddenArg: res_reg = rs_w12; break; 136 case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; 137 case kCount: res_reg = RegStorage::InvalidReg(); break; 138 default: res_reg = RegStorage::InvalidReg(); 139 } 140 return res_reg; 141} 142 143/* 144 * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. 145 */ 146ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 147 // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. 148 149 // Check if the shape mask is zero (i.e. invalid). 150 if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { 151 // The zero register is not a true register. It is just an immediate zero. 152 return kEncodeNone; 153 } 154 155 return ResourceMask::Bit( 156 // FP register starts at bit position 32. 157 (reg.IsFloat() ? kArm64FPReg0 : 0) + reg.GetRegNum()); 158} 159 160ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { 161 // Note: On arm64, we are not able to set pc except branch instructions, which is regarded as a 162 // kind of barrier. All other instructions only use pc, which has no dependency between any 163 // of them. So it is fine to just return kEncodeNone here. 164 return kEncodeNone; 165} 166 167// Arm64 specific setup. TODO: inline?: 168void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 169 ResourceMask* use_mask, ResourceMask* def_mask) { 170 DCHECK_EQ(cu_->instruction_set, kArm64); 171 DCHECK(!lir->flags.use_def_invalid); 172 173 // Note: REG_USE_PC is ignored, the reason is the same with what we do in GetPCUseDefEncoding(). 174 // These flags are somewhat uncommon - bypass if we can. 175 if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { 176 if (flags & REG_DEF_SP) { 177 def_mask->SetBit(kArm64RegSP); 178 } 179 180 if (flags & REG_USE_SP) { 181 use_mask->SetBit(kArm64RegSP); 182 } 183 184 if (flags & REG_DEF_LR) { 185 def_mask->SetBit(kArm64RegLR); 186 } 187 } 188} 189 190ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { 191 ArmConditionCode res; 192 switch (ccode) { 193 case kCondEq: res = kArmCondEq; break; 194 case kCondNe: res = kArmCondNe; break; 195 case kCondCs: res = kArmCondCs; break; 196 case kCondCc: res = kArmCondCc; break; 197 case kCondUlt: res = kArmCondCc; break; 198 case kCondUge: res = kArmCondCs; break; 199 case kCondMi: res = kArmCondMi; break; 200 case kCondPl: res = kArmCondPl; break; 201 case kCondVs: res = kArmCondVs; break; 202 case kCondVc: res = kArmCondVc; break; 203 case kCondHi: res = kArmCondHi; break; 204 case kCondLs: res = kArmCondLs; break; 205 case kCondGe: res = kArmCondGe; break; 206 case kCondLt: res = kArmCondLt; break; 207 case kCondGt: res = kArmCondGt; break; 208 case kCondLe: res = kArmCondLe; break; 209 case kCondAl: res = kArmCondAl; break; 210 case kCondNv: res = kArmCondNv; break; 211 default: 212 LOG(FATAL) << "Bad condition code " << ccode; 213 res = static_cast<ArmConditionCode>(0); // Quiet gcc 214 } 215 return res; 216} 217 218static const char *shift_names[4] = { 219 "lsl", 220 "lsr", 221 "asr", 222 "ror" 223}; 224 225static const char* extend_names[8] = { 226 "uxtb", 227 "uxth", 228 "uxtw", 229 "uxtx", 230 "sxtb", 231 "sxth", 232 "sxtw", 233 "sxtx", 234}; 235 236/* Decode and print a register extension (e.g. ", uxtb #1") */ 237static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { 238 if ((operand & (1 << 6)) == 0) { 239 const char *shift_name = shift_names[(operand >> 7) & 0x3]; 240 int amount = operand & 0x3f; 241 snprintf(buf, buf_size, ", %s #%d", shift_name, amount); 242 } else { 243 const char *extend_name = extend_names[(operand >> 3) & 0x7]; 244 int amount = operand & 0x7; 245 if (amount == 0) { 246 snprintf(buf, buf_size, ", %s", extend_name); 247 } else { 248 snprintf(buf, buf_size, ", %s #%d", extend_name, amount); 249 } 250 } 251} 252 253#define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1)) 254 255static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { 256 DCHECK_LE(width, 64U); 257 rotate &= 63; 258 value = value & BIT_MASK(width); 259 return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate); 260} 261 262static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { 263 unsigned i; 264 unsigned reg_size = (is_wide) ? 64 : 32; 265 uint64_t result = value & BIT_MASK(width); 266 for (i = width; i < reg_size; i *= 2) { 267 result |= (result << i); 268 } 269 DCHECK_EQ(i, reg_size); 270 return result; 271} 272 273/** 274 * @brief Decode an immediate in the form required by logical instructions. 275 * 276 * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. 277 * @param value The encoded logical immediates that is to be decoded. 278 * @return The decoded logical immediate. 279 * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). 280 */ 281uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { 282 unsigned n = (value >> 12) & 0x01; 283 unsigned imm_r = (value >> 6) & 0x3f; 284 unsigned imm_s = (value >> 0) & 0x3f; 285 286 // An integer is constructed from the n, imm_s and imm_r bits according to 287 // the following table: 288 // 289 // N imms immr size S R 290 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) 291 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) 292 // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) 293 // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) 294 // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) 295 // 0 11110s xxxxxr 2 UInt(s) UInt(r) 296 // (s bits must not be all set) 297 // 298 // A pattern is constructed of size bits, where the least significant S+1 299 // bits are set. The pattern is rotated right by R, and repeated across a 300 // 32 or 64-bit value, depending on destination register width. 301 302 if (n == 1) { 303 DCHECK_NE(imm_s, 0x3fU); 304 uint64_t bits = BIT_MASK(imm_s + 1); 305 return RotateRight(bits, imm_r, 64); 306 } else { 307 DCHECK_NE((imm_s >> 1), 0x1fU); 308 for (unsigned width = 0x20; width >= 0x2; width >>= 1) { 309 if ((imm_s & width) == 0) { 310 unsigned mask = (unsigned)(width - 1); 311 DCHECK_NE((imm_s & mask), mask); 312 uint64_t bits = BIT_MASK((imm_s & mask) + 1); 313 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); 314 } 315 } 316 } 317 return 0; 318} 319 320/** 321 * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). 322 */ 323static float DecodeImmSingle(uint8_t small_float) { 324 int mantissa = (small_float & 0x0f) + 0x10; 325 int sign = ((small_float & 0x80) == 0) ? 1 : -1; 326 float signed_mantissa = static_cast<float>(sign*mantissa); 327 int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; 328 return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; 329} 330 331static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 332 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; 333/* 334 * Interpret a format string and build a string no longer than size 335 * See format key in assemble_arm64.cc. 336 */ 337std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { 338 std::string buf; 339 const char* fmt_end = &fmt[strlen(fmt)]; 340 char tbuf[256]; 341 const char* name; 342 char nc; 343 while (fmt < fmt_end) { 344 int operand; 345 if (*fmt == '!') { 346 fmt++; 347 DCHECK_LT(fmt, fmt_end); 348 nc = *fmt++; 349 if (nc == '!') { 350 strcpy(tbuf, "!"); 351 } else { 352 DCHECK_LT(fmt, fmt_end); 353 DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); 354 operand = lir->operands[nc-'0']; 355 switch (*fmt++) { 356 case 'e': { 357 // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and 358 // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" 359 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : 360 EncodeExtend(kA64Uxtw, 0)); 361 if (LIKELY(operand == omittable)) { 362 strcpy(tbuf, ""); 363 } else { 364 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 365 } 366 } 367 break; 368 case 'o': 369 // Omit ", lsl #0" 370 if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { 371 strcpy(tbuf, ""); 372 } else { 373 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 374 } 375 break; 376 case 'B': 377 switch (operand) { 378 case kSY: 379 name = "sy"; 380 break; 381 case kST: 382 name = "st"; 383 break; 384 case kISH: 385 name = "ish"; 386 break; 387 case kISHST: 388 name = "ishst"; 389 break; 390 case kNSH: 391 name = "nsh"; 392 break; 393 case kNSHST: 394 name = "shst"; 395 break; 396 default: 397 name = "DecodeError2"; 398 break; 399 } 400 strcpy(tbuf, name); 401 break; 402 case 's': 403 snprintf(tbuf, arraysize(tbuf), "s%d", operand & RegStorage::kRegNumMask); 404 break; 405 case 'S': 406 snprintf(tbuf, arraysize(tbuf), "d%d", operand & RegStorage::kRegNumMask); 407 break; 408 case 'f': 409 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', 410 operand & RegStorage::kRegNumMask); 411 break; 412 case 'l': { 413 bool is_wide = IS_WIDE(lir->opcode); 414 uint64_t imm = DecodeLogicalImmediate(is_wide, operand); 415 snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); 416 } 417 break; 418 case 'I': 419 snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); 420 break; 421 case 'M': 422 if (LIKELY(operand == 0)) 423 strcpy(tbuf, ""); 424 else 425 snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); 426 break; 427 case 'd': 428 snprintf(tbuf, arraysize(tbuf), "%d", operand); 429 break; 430 case 'w': 431 if (LIKELY(operand != rwzr)) 432 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 433 else 434 strcpy(tbuf, "wzr"); 435 break; 436 case 'W': 437 if (LIKELY(operand != rwsp)) 438 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 439 else 440 strcpy(tbuf, "wsp"); 441 break; 442 case 'x': 443 if (LIKELY(operand != rxzr)) 444 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 445 else 446 strcpy(tbuf, "xzr"); 447 break; 448 case 'X': 449 if (LIKELY(operand != rsp)) 450 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 451 else 452 strcpy(tbuf, "sp"); 453 break; 454 case 'D': 455 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); 456 break; 457 case 'E': 458 snprintf(tbuf, arraysize(tbuf), "%d", operand*4); 459 break; 460 case 'F': 461 snprintf(tbuf, arraysize(tbuf), "%d", operand*2); 462 break; 463 case 'G': 464 if (LIKELY(operand == 0)) 465 strcpy(tbuf, ""); 466 else 467 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); 468 break; 469 case 'c': 470 strcpy(tbuf, cc_names[operand]); 471 break; 472 case 't': 473 snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", 474 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), 475 lir->target); 476 break; 477 case 'r': { 478 bool is_wide = IS_WIDE(lir->opcode); 479 if (LIKELY(operand != rwzr && operand != rxzr)) { 480 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 481 operand & RegStorage::kRegNumMask); 482 } else { 483 strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); 484 } 485 } 486 break; 487 case 'R': { 488 bool is_wide = IS_WIDE(lir->opcode); 489 if (LIKELY(operand != rwsp && operand != rsp)) { 490 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 491 operand & RegStorage::kRegNumMask); 492 } else { 493 strcpy(tbuf, (is_wide) ? "sp" : "wsp"); 494 } 495 } 496 break; 497 case 'p': 498 snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, 499 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); 500 break; 501 case 'T': 502 if (LIKELY(operand == 0)) 503 strcpy(tbuf, ""); 504 else if (operand == 1) 505 strcpy(tbuf, ", lsl #12"); 506 else 507 strcpy(tbuf, ", DecodeError3"); 508 break; 509 default: 510 strcpy(tbuf, "DecodeError1"); 511 break; 512 } 513 buf += tbuf; 514 } 515 } else { 516 buf += *fmt++; 517 } 518 } 519 return buf; 520} 521 522void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { 523 char buf[256]; 524 buf[0] = 0; 525 526 if (mask.Equals(kEncodeAll)) { 527 strcpy(buf, "all"); 528 } else { 529 char num[8]; 530 int i; 531 532 for (i = 0; i < kArm64RegEnd; i++) { 533 if (mask.HasBit(i)) { 534 snprintf(num, arraysize(num), "%d ", i); 535 strcat(buf, num); 536 } 537 } 538 539 if (mask.HasBit(ResourceMask::kCCode)) { 540 strcat(buf, "cc "); 541 } 542 if (mask.HasBit(ResourceMask::kFPStatus)) { 543 strcat(buf, "fpcc "); 544 } 545 546 /* Memory bits */ 547 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { 548 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 549 DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), 550 DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); 551 } 552 if (mask.HasBit(ResourceMask::kLiteral)) { 553 strcat(buf, "lit "); 554 } 555 556 if (mask.HasBit(ResourceMask::kHeapRef)) { 557 strcat(buf, "heap "); 558 } 559 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 560 strcat(buf, "noalias "); 561 } 562 } 563 if (buf[0]) { 564 LOG(INFO) << prefix << ": " << buf; 565 } 566} 567 568bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { 569 return (lir->opcode == kA64B1t); 570} 571 572bool Arm64Mir2Lir::SupportsVolatileLoadStore(OpSize size) { 573 return true; 574} 575 576RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 577 if (UNLIKELY(is_volatile)) { 578 // On arm64, fp register load/store is atomic only for single bytes. 579 if (size != kSignedByte && size != kUnsignedByte) { 580 return (size == kReference) ? kRefReg : kCoreReg; 581 } 582 } 583 return RegClassBySize(size); 584} 585 586Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 587 : Mir2Lir(cu, mir_graph, arena) { 588 // Sanity check - make sure encoding map lines up. 589 for (int i = 0; i < kA64Last; i++) { 590 if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { 591 LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name 592 << " is wrong: expecting " << i << ", seeing " 593 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); 594 } 595 } 596} 597 598Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 599 ArenaAllocator* const arena) { 600 return new Arm64Mir2Lir(cu, mir_graph, arena); 601} 602 603void Arm64Mir2Lir::CompilerInitializeRegAlloc() { 604 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs, 605 reserved_regs, reserved64_regs, core_temps, core64_temps, 606 sp_temps, dp_temps); 607 608 // Target-specific adjustments. 609 // Alias single precision float registers to corresponding double registers. 610 GrowableArray<RegisterInfo*>::Iterator fp_it(®_pool_->sp_regs_); 611 for (RegisterInfo* info = fp_it.Next(); info != nullptr; info = fp_it.Next()) { 612 int fp_reg_num = info->GetReg().GetRegNum(); 613 RegStorage dp_reg = RegStorage::FloatSolo64(fp_reg_num); 614 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 615 // Double precision register's master storage should refer to itself. 616 DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); 617 // Redirect single precision's master storage to master. 618 info->SetMaster(dp_reg_info); 619 // Singles should show a single 32-bit mask bit, at first referring to the low half. 620 DCHECK_EQ(info->StorageMask(), 0x1U); 621 } 622 623 // Alias 32bit W registers to corresponding 64bit X registers. 624 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 625 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 626 int x_reg_num = info->GetReg().GetRegNum(); 627 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 628 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 629 // 64bit X register's master storage should refer to itself. 630 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 631 // Redirect 32bit W master storage to 64bit X. 632 info->SetMaster(x_reg_info); 633 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 634 DCHECK_EQ(info->StorageMask(), 0x1U); 635 } 636 637 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 638 // TODO: adjust when we roll to hard float calling convention. 639 reg_pool_->next_core_reg_ = 2; 640 reg_pool_->next_sp_reg_ = 0; 641 reg_pool_->next_dp_reg_ = 0; 642} 643 644/* 645 * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some 646 * instructions might call out to C/assembly helper functions. Until 647 * machinery is in place, always spill lr. 648 */ 649 650void Arm64Mir2Lir::AdjustSpillMask() { 651 core_spill_mask_ |= (1 << rs_xLR.GetRegNum()); 652 num_core_spills_++; 653} 654 655/* Clobber all regs that might be used by an external C call */ 656void Arm64Mir2Lir::ClobberCallerSave() { 657 Clobber(rs_x0); 658 Clobber(rs_x1); 659 Clobber(rs_x2); 660 Clobber(rs_x3); 661 Clobber(rs_x4); 662 Clobber(rs_x5); 663 Clobber(rs_x6); 664 Clobber(rs_x7); 665 Clobber(rs_x8); 666 Clobber(rs_x9); 667 Clobber(rs_x10); 668 Clobber(rs_x11); 669 Clobber(rs_x12); 670 Clobber(rs_x13); 671 Clobber(rs_x14); 672 Clobber(rs_x15); 673 Clobber(rs_x16); 674 Clobber(rs_x17); 675 Clobber(rs_x30); 676 677 Clobber(rs_f0); 678 Clobber(rs_f1); 679 Clobber(rs_f2); 680 Clobber(rs_f3); 681 Clobber(rs_f4); 682 Clobber(rs_f5); 683 Clobber(rs_f6); 684 Clobber(rs_f7); 685 Clobber(rs_f16); 686 Clobber(rs_f17); 687 Clobber(rs_f18); 688 Clobber(rs_f19); 689 Clobber(rs_f20); 690 Clobber(rs_f21); 691 Clobber(rs_f22); 692 Clobber(rs_f23); 693 Clobber(rs_f24); 694 Clobber(rs_f25); 695 Clobber(rs_f26); 696 Clobber(rs_f27); 697 Clobber(rs_f28); 698 Clobber(rs_f29); 699 Clobber(rs_f30); 700 Clobber(rs_f31); 701} 702 703RegLocation Arm64Mir2Lir::GetReturnWideAlt() { 704 RegLocation res = LocCReturnWide(); 705 res.reg.SetReg(rx2); 706 res.reg.SetHighReg(rx3); 707 Clobber(rs_x2); 708 Clobber(rs_x3); 709 MarkInUse(rs_x2); 710 MarkInUse(rs_x3); 711 MarkWide(res.reg); 712 return res; 713} 714 715RegLocation Arm64Mir2Lir::GetReturnAlt() { 716 RegLocation res = LocCReturn(); 717 res.reg.SetReg(rx1); 718 Clobber(rs_x1); 719 MarkInUse(rs_x1); 720 return res; 721} 722 723/* To be used when explicitly managing register use */ 724void Arm64Mir2Lir::LockCallTemps() { 725 // TODO: needs cleanup. 726 LockTemp(rs_x0); 727 LockTemp(rs_x1); 728 LockTemp(rs_x2); 729 LockTemp(rs_x3); 730 LockTemp(rs_x4); 731 LockTemp(rs_x5); 732 LockTemp(rs_x6); 733 LockTemp(rs_x7); 734 LockTemp(rs_f0); 735 LockTemp(rs_f1); 736 LockTemp(rs_f2); 737 LockTemp(rs_f3); 738 LockTemp(rs_f4); 739 LockTemp(rs_f5); 740 LockTemp(rs_f6); 741 LockTemp(rs_f7); 742} 743 744/* To be used when explicitly managing register use */ 745void Arm64Mir2Lir::FreeCallTemps() { 746 // TODO: needs cleanup. 747 FreeTemp(rs_x0); 748 FreeTemp(rs_x1); 749 FreeTemp(rs_x2); 750 FreeTemp(rs_x3); 751 FreeTemp(rs_x4); 752 FreeTemp(rs_x5); 753 FreeTemp(rs_x6); 754 FreeTemp(rs_x7); 755 FreeTemp(rs_f0); 756 FreeTemp(rs_f1); 757 FreeTemp(rs_f2); 758 FreeTemp(rs_f3); 759 FreeTemp(rs_f4); 760 FreeTemp(rs_f5); 761 FreeTemp(rs_f6); 762 FreeTemp(rs_f7); 763} 764 765RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 766 UNIMPLEMENTED(FATAL) << "Should not be called."; 767 return RegStorage::InvalidReg(); 768} 769 770RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<8> offset) { 771 // TODO(Arm64): use LoadWordDisp instead. 772 // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); 773 LoadBaseDisp(rs_xSELF, offset.Int32Value(), rs_xLR, k64, kNotVolatile); 774 return rs_xLR; 775} 776 777LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { 778 RegStorage tmp = rs_x0; 779 LoadWordDisp(rs_xSELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); 780 LIR* load2 = LoadWordDisp(tmp, 0, tmp); 781 return load2; 782} 783 784uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { 785 DCHECK(!IsPseudoLirOp(opcode)); 786 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; 787} 788 789const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { 790 DCHECK(!IsPseudoLirOp(opcode)); 791 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; 792} 793 794const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { 795 DCHECK(!IsPseudoLirOp(opcode)); 796 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; 797} 798 799RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(bool is_double_or_float, 800 bool is_wide, 801 bool is_ref) { 802 const RegStorage coreArgMappingToPhysicalReg[] = 803 {rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7}; 804 const int coreArgMappingToPhysicalRegSize = 805 sizeof(coreArgMappingToPhysicalReg) / sizeof(RegStorage); 806 const RegStorage fpArgMappingToPhysicalReg[] = 807 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7}; 808 const int fpArgMappingToPhysicalRegSize = 809 sizeof(fpArgMappingToPhysicalReg) / sizeof(RegStorage); 810 811 RegStorage result = RegStorage::InvalidReg(); 812 if (is_double_or_float) { 813 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 814 DCHECK(!is_ref); 815 result = fpArgMappingToPhysicalReg[cur_fp_reg_++]; 816 if (result.Valid()) { 817 // TODO: switching between widths remains a bit ugly. Better way? 818 int res_reg = result.GetReg(); 819 result = is_wide ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg); 820 } 821 } 822 } else { 823 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 824 result = coreArgMappingToPhysicalReg[cur_core_reg_++]; 825 if (result.Valid()) { 826 // TODO: switching between widths remains a bit ugly. Better way? 827 int res_reg = result.GetReg(); 828 DCHECK(!(is_wide && is_ref)); 829 result = (is_wide || is_ref) ? RegStorage::Solo64(res_reg) : RegStorage::Solo32(res_reg); 830 } 831 } 832 } 833 return result; 834} 835 836RegStorage Arm64Mir2Lir::InToRegStorageMapping::Get(int in_position) { 837 DCHECK(IsInitialized()); 838 auto res = mapping_.find(in_position); 839 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 840} 841 842void Arm64Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, 843 InToRegStorageMapper* mapper) { 844 DCHECK(mapper != nullptr); 845 max_mapped_in_ = -1; 846 is_there_stack_mapped_ = false; 847 for (int in_position = 0; in_position < count; in_position++) { 848 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, 849 arg_locs[in_position].wide, 850 arg_locs[in_position].ref); 851 if (reg.Valid()) { 852 mapping_[in_position] = reg; 853 if (arg_locs[in_position].wide) { 854 // We covered 2 args, so skip the next one 855 in_position++; 856 } 857 max_mapped_in_ = std::max(max_mapped_in_, in_position); 858 } else { 859 is_there_stack_mapped_ = true; 860 } 861 } 862 initialized_ = true; 863} 864 865 866// Deprecate. Use the new mechanism. 867// TODO(Arm64): reuse info in QuickArgumentVisitor? 868static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used, 869 OpSize* op_size) { 870 if (loc->fp) { 871 int n = *num_fpr_used; 872 if (n < 8) { 873 *num_fpr_used = n + 1; 874 RegStorage::RegStorageKind reg_kind; 875 if (loc->wide) { 876 *op_size = kDouble; 877 reg_kind = RegStorage::k64BitSolo; 878 } else { 879 *op_size = kSingle; 880 reg_kind = RegStorage::k32BitSolo; 881 } 882 return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n); 883 } 884 } else { 885 int n = *num_gpr_used; 886 if (n < 8) { 887 *num_gpr_used = n + 1; 888 if (loc->wide || loc->ref) { 889 *op_size = k64; 890 return RegStorage::Solo64(n); 891 } else { 892 *op_size = k32; 893 return RegStorage::Solo32(n); 894 } 895 } 896 } 897 *op_size = kWord; 898 return RegStorage::InvalidReg(); 899} 900 901RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 902 if (!in_to_reg_storage_mapping_.IsInitialized()) { 903 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 904 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 905 906 InToRegStorageArm64Mapper mapper; 907 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 908 } 909 return in_to_reg_storage_mapping_.Get(arg_num); 910} 911 912 913/* 914 * If there are any ins passed in registers that have not been promoted 915 * to a callee-save register, flush them to the frame. Perform initial 916 * assignment of promoted arguments. 917 * 918 * ArgLocs is an array of location records describing the incoming arguments 919 * with one location record per word of argument. 920 */ 921void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 922 int num_gpr_used = 1; 923 int num_fpr_used = 0; 924 925 /* 926 * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod> 927 * It will attempt to keep kArg0 live (or copy it to home location 928 * if promoted). 929 */ 930 RegLocation rl_src = rl_method; 931 rl_src.location = kLocPhysReg; 932 rl_src.reg = TargetReg(kArg0, kRef); 933 rl_src.home = false; 934 MarkLive(rl_src); 935 StoreValue(rl_method, rl_src); 936 // If Method* has been promoted, explicitly flush 937 if (rl_method.location == kLocPhysReg) { 938 StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile); 939 } 940 941 if (cu_->num_ins == 0) { 942 return; 943 } 944 945 // Handle dalvik registers. 946 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 947 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 948 for (int i = 0; i < cu_->num_ins; i++) { 949 RegLocation* t_loc = &ArgLocs[i]; 950 OpSize op_size; 951 RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size); 952 953 if (reg.Valid()) { 954 // If arriving in register. 955 956 // We have already updated the arg location with promoted info 957 // so we can be based on it. 958 if (t_loc->location == kLocPhysReg) { 959 // Just copy it. 960 OpRegCopy(t_loc->reg, reg); 961 } else { 962 // Needs flush. 963 if (t_loc->ref) { 964 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, kNotVolatile); 965 } else { 966 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 967 kNotVolatile); 968 } 969 } 970 } else { 971 // If arriving in frame & promoted. 972 if (t_loc->location == kLocPhysReg) { 973 if (t_loc->ref) { 974 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 975 } else { 976 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, 977 t_loc->wide ? k64 : k32, kNotVolatile); 978 } 979 } 980 } 981 if (t_loc->wide) { 982 // Increment i to skip the next one. 983 i++; 984 } 985 // if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 986 // OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); 987 // } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 988 // OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg); 989 // } else { 990 // StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size, kNotVolatile); 991 // if (reg.Is64Bit()) { 992 // if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) { 993 // LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots"; 994 // } 995 // i += 1; 996 // } 997 // } 998 // } else { 999 // // If arriving in frame & promoted 1000 // if (v_map->core_location == kLocPhysReg) { 1001 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 1002 // RegStorage::Solo32(v_map->core_reg)); 1003 // } 1004 // if (v_map->fp_location == kLocPhysReg) { 1005 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->fp_reg)); 1006 // } 1007 } 1008} 1009 1010/* 1011 * Load up to 5 arguments, the first three of which will be in 1012 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 1013 * and as part of the load sequence, it must be replaced with 1014 * the target method pointer. 1015 */ 1016int Arm64Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 1017 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 1018 const MethodReference& target_method, 1019 uint32_t vtable_idx, uintptr_t direct_code, 1020 uintptr_t direct_method, InvokeType type, bool skip_this) { 1021 return GenDalvikArgsRange(info, 1022 call_state, pcrLabel, next_call_insn, 1023 target_method, 1024 vtable_idx, direct_code, 1025 direct_method, type, skip_this); 1026} 1027 1028/* 1029 * May have 0+ arguments (also used for jumbo). Note that 1030 * source virtual registers may be in physical registers, so may 1031 * need to be flushed to home location before copying. This 1032 * applies to arg3 and above (see below). 1033 * 1034 * FIXME: update comments. 1035 * 1036 * Two general strategies: 1037 * If < 20 arguments 1038 * Pass args 3-18 using vldm/vstm block copy 1039 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1040 * If 20+ arguments 1041 * Pass args arg19+ using memcpy block copy 1042 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1043 * 1044 */ 1045int Arm64Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 1046 LIR** pcrLabel, NextCallInsn next_call_insn, 1047 const MethodReference& target_method, 1048 uint32_t vtable_idx, uintptr_t direct_code, 1049 uintptr_t direct_method, InvokeType type, bool skip_this) { 1050 /* If no arguments, just return */ 1051 if (info->num_arg_words == 0) 1052 return call_state; 1053 1054 const int start_index = skip_this ? 1 : 0; 1055 1056 InToRegStorageArm64Mapper mapper; 1057 InToRegStorageMapping in_to_reg_storage_mapping; 1058 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 1059 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 1060 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + 1); 1061 1062 // First of all, check whether it makes sense to use bulk copying. 1063 // Bulk copying is done only for the range case. 1064 // TODO: make a constant instead of 2 1065 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 1066 // Scan the rest of the args - if in phys_reg flush to memory 1067 for (int next_arg = last_mapped_in + 1; next_arg < info->num_arg_words;) { 1068 RegLocation loc = info->args[next_arg]; 1069 if (loc.wide) { 1070 loc = UpdateLocWide(loc); 1071 if (loc.location == kLocPhysReg) { 1072 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1073 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 1074 } 1075 next_arg += 2; 1076 } else { 1077 loc = UpdateLoc(loc); 1078 if (loc.location == kLocPhysReg) { 1079 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1080 if (loc.ref) { 1081 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); 1082 } else { 1083 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32, 1084 kNotVolatile); 1085 } 1086 } 1087 next_arg++; 1088 } 1089 } 1090 1091 // Logic below assumes that Method pointer is at offset zero from SP. 1092 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 1093 1094 // The rest can be copied together 1095 int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low); 1096 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + 1, 1097 cu_->instruction_set); 1098 1099 int current_src_offset = start_offset; 1100 int current_dest_offset = outs_offset; 1101 1102 // Only davik regs are accessed in this loop; no next_call_insn() calls. 1103 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1104 while (regs_left_to_pass_via_stack > 0) { 1105 /* 1106 * TODO: Improve by adding block copy for large number of arguments. This 1107 * should be done, if possible, as a target-depending helper. For now, just 1108 * copy a Dalvik vreg at a time. 1109 */ 1110 // Moving 32-bits via general purpose register. 1111 size_t bytes_to_move = sizeof(uint32_t); 1112 1113 // Instead of allocating a new temp, simply reuse one of the registers being used 1114 // for argument passing. 1115 RegStorage temp = TargetReg(kArg3, kNotWide); 1116 1117 // Now load the argument VR and store to the outs. 1118 Load32Disp(TargetPtrReg(kSp), current_src_offset, temp); 1119 Store32Disp(TargetPtrReg(kSp), current_dest_offset, temp); 1120 1121 current_src_offset += bytes_to_move; 1122 current_dest_offset += bytes_to_move; 1123 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 1124 } 1125 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 1126 } 1127 1128 // Now handle rest not registers if they are 1129 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 1130 RegStorage regWide = TargetReg(kArg3, kWide); 1131 for (int i = start_index; i <= last_mapped_in + regs_left_to_pass_via_stack; i++) { 1132 RegLocation rl_arg = info->args[i]; 1133 rl_arg = UpdateRawLoc(rl_arg); 1134 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1135 if (!reg.Valid()) { 1136 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 1137 1138 { 1139 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1140 if (rl_arg.wide) { 1141 if (rl_arg.location == kLocPhysReg) { 1142 StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k64, kNotVolatile); 1143 } else { 1144 LoadValueDirectWideFixed(rl_arg, regWide); 1145 StoreBaseDisp(TargetPtrReg(kSp), out_offset, regWide, k64, kNotVolatile); 1146 } 1147 } else { 1148 if (rl_arg.location == kLocPhysReg) { 1149 if (rl_arg.ref) { 1150 StoreRefDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, kNotVolatile); 1151 } else { 1152 StoreBaseDisp(TargetPtrReg(kSp), out_offset, rl_arg.reg, k32, kNotVolatile); 1153 } 1154 } else { 1155 if (rl_arg.ref) { 1156 RegStorage regSingle = TargetReg(kArg2, kRef); 1157 LoadValueDirectFixed(rl_arg, regSingle); 1158 StoreRefDisp(TargetPtrReg(kSp), out_offset, regSingle, kNotVolatile); 1159 } else { 1160 RegStorage regSingle = TargetReg(kArg2, kNotWide); 1161 LoadValueDirectFixed(rl_arg, regSingle); 1162 StoreBaseDisp(TargetPtrReg(kSp), out_offset, regSingle, k32, kNotVolatile); 1163 } 1164 } 1165 } 1166 } 1167 call_state = next_call_insn(cu_, info, call_state, target_method, 1168 vtable_idx, direct_code, direct_method, type); 1169 } 1170 if (rl_arg.wide) { 1171 i++; 1172 } 1173 } 1174 } 1175 1176 // Finish with mapped registers 1177 for (int i = start_index; i <= last_mapped_in; i++) { 1178 RegLocation rl_arg = info->args[i]; 1179 rl_arg = UpdateRawLoc(rl_arg); 1180 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1181 if (reg.Valid()) { 1182 if (rl_arg.wide) { 1183 LoadValueDirectWideFixed(rl_arg, reg); 1184 } else { 1185 LoadValueDirectFixed(rl_arg, reg); 1186 } 1187 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1188 direct_code, direct_method, type); 1189 } 1190 if (rl_arg.wide) { 1191 i++; 1192 } 1193 } 1194 1195 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1196 direct_code, direct_method, type); 1197 if (pcrLabel) { 1198 if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { 1199 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); 1200 } else { 1201 *pcrLabel = nullptr; 1202 // In lieu of generating a check for kArg1 being null, we need to 1203 // perform a load when doing implicit checks. 1204 RegStorage tmp = AllocTemp(); 1205 Load32Disp(TargetReg(kArg1, kRef), 0, tmp); 1206 MarkPossibleNullPointerException(info->opt_flags); 1207 FreeTemp(tmp); 1208 } 1209 } 1210 return call_state; 1211} 1212 1213} // namespace art 1214