target_arm64.cc revision b5860fb459f1ed71f39d8a87b45bee6727d79fe8
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_arm64.h" 18 19#include <inttypes.h> 20 21#include <string> 22 23#include "dex/compiler_internals.h" 24#include "dex/quick/mir_to_lir-inl.h" 25#include "dex/reg_storage_eq.h" 26 27namespace art { 28 29static constexpr RegStorage core_regs_arr[] = 30 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 31 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, 32 rs_w16, rs_w17, rs_w18, rs_w19, rs_w20, rs_w21, rs_w22, rs_w23, 33 rs_w24, rs_w25, rs_w26, rs_w27, rs_w28, rs_w29, rs_w30, rs_w31, 34 rs_wzr}; 35static constexpr RegStorage core64_regs_arr[] = 36 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 37 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, 38 rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, 39 rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31, 40 rs_xzr}; 41static constexpr RegStorage sp_regs_arr[] = 42 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 43 rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, 44 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 45 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 46static constexpr RegStorage dp_regs_arr[] = 47 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 48 rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15, 49 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 50 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 51static constexpr RegStorage reserved_regs_arr[] = 52 {rs_wSUSPEND, rs_wSELF, rs_wsp, rs_wLR, rs_wzr}; 53static constexpr RegStorage reserved64_regs_arr[] = 54 {rs_xSUSPEND, rs_xSELF, rs_sp, rs_xLR, rs_xzr}; 55// TUNING: Are there too many temp registers and too less promote target? 56// This definition need to be matched with runtime.cc, quick entry assembly and JNI compiler 57// Note: we are not able to call to C function directly if it un-match C ABI. 58// Currently, rs_rA64_SELF is not a callee save register which does not match C ABI. 59static constexpr RegStorage core_temps_arr[] = 60 {rs_w0, rs_w1, rs_w2, rs_w3, rs_w4, rs_w5, rs_w6, rs_w7, 61 rs_w8, rs_w9, rs_w10, rs_w11, rs_w12, rs_w13, rs_w14, rs_w15, rs_w16, 62 rs_w17}; 63static constexpr RegStorage core64_temps_arr[] = 64 {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, 65 rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16, 66 rs_x17}; 67static constexpr RegStorage sp_temps_arr[] = 68 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, 69 rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, 70 rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; 71static constexpr RegStorage dp_temps_arr[] = 72 {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, 73 rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, 74 rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; 75 76static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr); 77static constexpr ArrayRef<const RegStorage> core64_regs(core64_regs_arr); 78static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr); 79static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr); 80static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr); 81static constexpr ArrayRef<const RegStorage> reserved64_regs(reserved64_regs_arr); 82static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr); 83static constexpr ArrayRef<const RegStorage> core64_temps(core64_temps_arr); 84static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr); 85static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr); 86 87RegLocation Arm64Mir2Lir::LocCReturn() { 88 return arm_loc_c_return; 89} 90 91RegLocation Arm64Mir2Lir::LocCReturnRef() { 92 return arm_loc_c_return_ref; 93} 94 95RegLocation Arm64Mir2Lir::LocCReturnWide() { 96 return arm_loc_c_return_wide; 97} 98 99RegLocation Arm64Mir2Lir::LocCReturnFloat() { 100 return arm_loc_c_return_float; 101} 102 103RegLocation Arm64Mir2Lir::LocCReturnDouble() { 104 return arm_loc_c_return_double; 105} 106 107// Return a target-dependent special register. 108RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { 109 RegStorage res_reg = RegStorage::InvalidReg(); 110 switch (reg) { 111 case kSelf: res_reg = rs_xSELF; break; 112 case kSuspend: res_reg = rs_xSUSPEND; break; 113 case kLr: res_reg = rs_xLR; break; 114 case kPc: res_reg = RegStorage::InvalidReg(); break; 115 case kSp: res_reg = rs_sp; break; 116 case kArg0: res_reg = rs_x0; break; 117 case kArg1: res_reg = rs_x1; break; 118 case kArg2: res_reg = rs_x2; break; 119 case kArg3: res_reg = rs_x3; break; 120 case kArg4: res_reg = rs_x4; break; 121 case kArg5: res_reg = rs_x5; break; 122 case kArg6: res_reg = rs_x6; break; 123 case kArg7: res_reg = rs_x7; break; 124 case kFArg0: res_reg = rs_f0; break; 125 case kFArg1: res_reg = rs_f1; break; 126 case kFArg2: res_reg = rs_f2; break; 127 case kFArg3: res_reg = rs_f3; break; 128 case kFArg4: res_reg = rs_f4; break; 129 case kFArg5: res_reg = rs_f5; break; 130 case kFArg6: res_reg = rs_f6; break; 131 case kFArg7: res_reg = rs_f7; break; 132 case kRet0: res_reg = rs_x0; break; 133 case kRet1: res_reg = rs_x1; break; 134 case kInvokeTgt: res_reg = rs_xLR; break; 135 case kHiddenArg: res_reg = rs_x12; break; 136 case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; 137 case kCount: res_reg = RegStorage::InvalidReg(); break; 138 default: res_reg = RegStorage::InvalidReg(); 139 } 140 return res_reg; 141} 142 143/* 144 * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. 145 */ 146ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { 147 // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. 148 149 // Check if the shape mask is zero (i.e. invalid). 150 if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { 151 // The zero register is not a true register. It is just an immediate zero. 152 return kEncodeNone; 153 } 154 155 return ResourceMask::Bit( 156 // FP register starts at bit position 32. 157 (reg.IsFloat() ? kArm64FPReg0 : 0) + reg.GetRegNum()); 158} 159 160ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { 161 LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for Arm64"; 162 return kEncodeNone; 163} 164 165// Arm64 specific setup. TODO: inline?: 166void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, 167 ResourceMask* use_mask, ResourceMask* def_mask) { 168 DCHECK_EQ(cu_->instruction_set, kArm64); 169 DCHECK(!lir->flags.use_def_invalid); 170 171 // These flags are somewhat uncommon - bypass if we can. 172 if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { 173 if (flags & REG_DEF_SP) { 174 def_mask->SetBit(kArm64RegSP); 175 } 176 177 if (flags & REG_USE_SP) { 178 use_mask->SetBit(kArm64RegSP); 179 } 180 181 if (flags & REG_DEF_LR) { 182 def_mask->SetBit(kArm64RegLR); 183 } 184 } 185} 186 187ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { 188 ArmConditionCode res; 189 switch (ccode) { 190 case kCondEq: res = kArmCondEq; break; 191 case kCondNe: res = kArmCondNe; break; 192 case kCondCs: res = kArmCondCs; break; 193 case kCondCc: res = kArmCondCc; break; 194 case kCondUlt: res = kArmCondCc; break; 195 case kCondUge: res = kArmCondCs; break; 196 case kCondMi: res = kArmCondMi; break; 197 case kCondPl: res = kArmCondPl; break; 198 case kCondVs: res = kArmCondVs; break; 199 case kCondVc: res = kArmCondVc; break; 200 case kCondHi: res = kArmCondHi; break; 201 case kCondLs: res = kArmCondLs; break; 202 case kCondGe: res = kArmCondGe; break; 203 case kCondLt: res = kArmCondLt; break; 204 case kCondGt: res = kArmCondGt; break; 205 case kCondLe: res = kArmCondLe; break; 206 case kCondAl: res = kArmCondAl; break; 207 case kCondNv: res = kArmCondNv; break; 208 default: 209 LOG(FATAL) << "Bad condition code " << ccode; 210 res = static_cast<ArmConditionCode>(0); // Quiet gcc 211 } 212 return res; 213} 214 215static const char *shift_names[4] = { 216 "lsl", 217 "lsr", 218 "asr", 219 "ror" 220}; 221 222static const char* extend_names[8] = { 223 "uxtb", 224 "uxth", 225 "uxtw", 226 "uxtx", 227 "sxtb", 228 "sxth", 229 "sxtw", 230 "sxtx", 231}; 232 233/* Decode and print a register extension (e.g. ", uxtb #1") */ 234static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { 235 if ((operand & (1 << 6)) == 0) { 236 const char *shift_name = shift_names[(operand >> 7) & 0x3]; 237 int amount = operand & 0x3f; 238 snprintf(buf, buf_size, ", %s #%d", shift_name, amount); 239 } else { 240 const char *extend_name = extend_names[(operand >> 3) & 0x7]; 241 int amount = operand & 0x7; 242 if (amount == 0) { 243 snprintf(buf, buf_size, ", %s", extend_name); 244 } else { 245 snprintf(buf, buf_size, ", %s #%d", extend_name, amount); 246 } 247 } 248} 249 250#define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1)) 251 252static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { 253 DCHECK_LE(width, 64U); 254 rotate &= 63; 255 value = value & BIT_MASK(width); 256 return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate); 257} 258 259static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { 260 unsigned i; 261 unsigned reg_size = (is_wide) ? 64 : 32; 262 uint64_t result = value & BIT_MASK(width); 263 for (i = width; i < reg_size; i *= 2) { 264 result |= (result << i); 265 } 266 DCHECK_EQ(i, reg_size); 267 return result; 268} 269 270/** 271 * @brief Decode an immediate in the form required by logical instructions. 272 * 273 * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. 274 * @param value The encoded logical immediates that is to be decoded. 275 * @return The decoded logical immediate. 276 * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). 277 */ 278uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { 279 unsigned n = (value >> 12) & 0x01; 280 unsigned imm_r = (value >> 6) & 0x3f; 281 unsigned imm_s = (value >> 0) & 0x3f; 282 283 // An integer is constructed from the n, imm_s and imm_r bits according to 284 // the following table: 285 // 286 // N imms immr size S R 287 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) 288 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) 289 // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) 290 // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) 291 // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) 292 // 0 11110s xxxxxr 2 UInt(s) UInt(r) 293 // (s bits must not be all set) 294 // 295 // A pattern is constructed of size bits, where the least significant S+1 296 // bits are set. The pattern is rotated right by R, and repeated across a 297 // 32 or 64-bit value, depending on destination register width. 298 299 if (n == 1) { 300 DCHECK_NE(imm_s, 0x3fU); 301 uint64_t bits = BIT_MASK(imm_s + 1); 302 return RotateRight(bits, imm_r, 64); 303 } else { 304 DCHECK_NE((imm_s >> 1), 0x1fU); 305 for (unsigned width = 0x20; width >= 0x2; width >>= 1) { 306 if ((imm_s & width) == 0) { 307 unsigned mask = (unsigned)(width - 1); 308 DCHECK_NE((imm_s & mask), mask); 309 uint64_t bits = BIT_MASK((imm_s & mask) + 1); 310 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); 311 } 312 } 313 } 314 return 0; 315} 316 317/** 318 * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). 319 */ 320static float DecodeImmSingle(uint8_t small_float) { 321 int mantissa = (small_float & 0x0f) + 0x10; 322 int sign = ((small_float & 0x80) == 0) ? 1 : -1; 323 float signed_mantissa = static_cast<float>(sign*mantissa); 324 int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; 325 return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; 326} 327 328static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 329 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; 330/* 331 * Interpret a format string and build a string no longer than size 332 * See format key in assemble_arm64.cc. 333 */ 334std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { 335 std::string buf; 336 const char* fmt_end = &fmt[strlen(fmt)]; 337 char tbuf[256]; 338 const char* name; 339 char nc; 340 while (fmt < fmt_end) { 341 int operand; 342 if (*fmt == '!') { 343 fmt++; 344 DCHECK_LT(fmt, fmt_end); 345 nc = *fmt++; 346 if (nc == '!') { 347 strcpy(tbuf, "!"); 348 } else { 349 DCHECK_LT(fmt, fmt_end); 350 DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); 351 operand = lir->operands[nc-'0']; 352 switch (*fmt++) { 353 case 'e': { 354 // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and 355 // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" 356 int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : 357 EncodeExtend(kA64Uxtw, 0)); 358 if (LIKELY(operand == omittable)) { 359 strcpy(tbuf, ""); 360 } else { 361 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 362 } 363 } 364 break; 365 case 'o': 366 // Omit ", lsl #0" 367 if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { 368 strcpy(tbuf, ""); 369 } else { 370 DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); 371 } 372 break; 373 case 'B': 374 switch (operand) { 375 case kSY: 376 name = "sy"; 377 break; 378 case kST: 379 name = "st"; 380 break; 381 case kISH: 382 name = "ish"; 383 break; 384 case kISHST: 385 name = "ishst"; 386 break; 387 case kNSH: 388 name = "nsh"; 389 break; 390 case kNSHST: 391 name = "shst"; 392 break; 393 default: 394 name = "DecodeError2"; 395 break; 396 } 397 strcpy(tbuf, name); 398 break; 399 case 's': 400 snprintf(tbuf, arraysize(tbuf), "s%d", operand & RegStorage::kRegNumMask); 401 break; 402 case 'S': 403 snprintf(tbuf, arraysize(tbuf), "d%d", operand & RegStorage::kRegNumMask); 404 break; 405 case 'f': 406 snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', 407 operand & RegStorage::kRegNumMask); 408 break; 409 case 'l': { 410 bool is_wide = IS_WIDE(lir->opcode); 411 uint64_t imm = DecodeLogicalImmediate(is_wide, operand); 412 snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); 413 } 414 break; 415 case 'I': 416 snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); 417 break; 418 case 'M': 419 if (LIKELY(operand == 0)) 420 strcpy(tbuf, ""); 421 else 422 snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); 423 break; 424 case 'd': 425 snprintf(tbuf, arraysize(tbuf), "%d", operand); 426 break; 427 case 'w': 428 if (LIKELY(operand != rwzr)) 429 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 430 else 431 strcpy(tbuf, "wzr"); 432 break; 433 case 'W': 434 if (LIKELY(operand != rwsp)) 435 snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); 436 else 437 strcpy(tbuf, "wsp"); 438 break; 439 case 'x': 440 if (LIKELY(operand != rxzr)) 441 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 442 else 443 strcpy(tbuf, "xzr"); 444 break; 445 case 'X': 446 if (LIKELY(operand != rsp)) 447 snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); 448 else 449 strcpy(tbuf, "sp"); 450 break; 451 case 'D': 452 snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); 453 break; 454 case 'E': 455 snprintf(tbuf, arraysize(tbuf), "%d", operand*4); 456 break; 457 case 'F': 458 snprintf(tbuf, arraysize(tbuf), "%d", operand*2); 459 break; 460 case 'G': 461 if (LIKELY(operand == 0)) 462 strcpy(tbuf, ""); 463 else 464 strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); 465 break; 466 case 'c': 467 strcpy(tbuf, cc_names[operand]); 468 break; 469 case 't': 470 snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", 471 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), 472 lir->target); 473 break; 474 case 'r': { 475 bool is_wide = IS_WIDE(lir->opcode); 476 if (LIKELY(operand != rwzr && operand != rxzr)) { 477 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 478 operand & RegStorage::kRegNumMask); 479 } else { 480 strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); 481 } 482 } 483 break; 484 case 'R': { 485 bool is_wide = IS_WIDE(lir->opcode); 486 if (LIKELY(operand != rwsp && operand != rsp)) { 487 snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', 488 operand & RegStorage::kRegNumMask); 489 } else { 490 strcpy(tbuf, (is_wide) ? "sp" : "wsp"); 491 } 492 } 493 break; 494 case 'p': 495 snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, 496 reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); 497 break; 498 case 'T': 499 if (LIKELY(operand == 0)) 500 strcpy(tbuf, ""); 501 else if (operand == 1) 502 strcpy(tbuf, ", lsl #12"); 503 else 504 strcpy(tbuf, ", DecodeError3"); 505 break; 506 default: 507 strcpy(tbuf, "DecodeError1"); 508 break; 509 } 510 buf += tbuf; 511 } 512 } else { 513 buf += *fmt++; 514 } 515 } 516 return buf; 517} 518 519void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { 520 char buf[256]; 521 buf[0] = 0; 522 523 if (mask.Equals(kEncodeAll)) { 524 strcpy(buf, "all"); 525 } else { 526 char num[8]; 527 int i; 528 529 for (i = 0; i < kArm64RegEnd; i++) { 530 if (mask.HasBit(i)) { 531 snprintf(num, arraysize(num), "%d ", i); 532 strcat(buf, num); 533 } 534 } 535 536 if (mask.HasBit(ResourceMask::kCCode)) { 537 strcat(buf, "cc "); 538 } 539 if (mask.HasBit(ResourceMask::kFPStatus)) { 540 strcat(buf, "fpcc "); 541 } 542 543 /* Memory bits */ 544 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { 545 snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", 546 DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), 547 DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); 548 } 549 if (mask.HasBit(ResourceMask::kLiteral)) { 550 strcat(buf, "lit "); 551 } 552 553 if (mask.HasBit(ResourceMask::kHeapRef)) { 554 strcat(buf, "heap "); 555 } 556 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 557 strcat(buf, "noalias "); 558 } 559 } 560 if (buf[0]) { 561 LOG(INFO) << prefix << ": " << buf; 562 } 563} 564 565bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { 566 return (lir->opcode == kA64B1t); 567} 568 569bool Arm64Mir2Lir::SupportsVolatileLoadStore(OpSize size) { 570 return true; 571} 572 573RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { 574 if (UNLIKELY(is_volatile)) { 575 // On arm64, fp register load/store is atomic only for single bytes. 576 if (size != kSignedByte && size != kUnsignedByte) { 577 return (size == kReference) ? kRefReg : kCoreReg; 578 } 579 } 580 return RegClassBySize(size); 581} 582 583Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) 584 : Mir2Lir(cu, mir_graph, arena) { 585 // Sanity check - make sure encoding map lines up. 586 for (int i = 0; i < kA64Last; i++) { 587 if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { 588 LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name 589 << " is wrong: expecting " << i << ", seeing " 590 << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); 591 } 592 } 593} 594 595Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 596 ArenaAllocator* const arena) { 597 return new Arm64Mir2Lir(cu, mir_graph, arena); 598} 599 600void Arm64Mir2Lir::CompilerInitializeRegAlloc() { 601 reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs, 602 reserved_regs, reserved64_regs, core_temps, core64_temps, 603 sp_temps, dp_temps); 604 605 // Target-specific adjustments. 606 // Alias single precision float registers to corresponding double registers. 607 GrowableArray<RegisterInfo*>::Iterator fp_it(®_pool_->sp_regs_); 608 for (RegisterInfo* info = fp_it.Next(); info != nullptr; info = fp_it.Next()) { 609 int fp_reg_num = info->GetReg().GetRegNum(); 610 RegStorage dp_reg = RegStorage::FloatSolo64(fp_reg_num); 611 RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); 612 // Double precision register's master storage should refer to itself. 613 DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); 614 // Redirect single precision's master storage to master. 615 info->SetMaster(dp_reg_info); 616 // Singles should show a single 32-bit mask bit, at first referring to the low half. 617 DCHECK_EQ(info->StorageMask(), 0x1U); 618 } 619 620 // Alias 32bit W registers to corresponding 64bit X registers. 621 GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); 622 for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { 623 int x_reg_num = info->GetReg().GetRegNum(); 624 RegStorage x_reg = RegStorage::Solo64(x_reg_num); 625 RegisterInfo* x_reg_info = GetRegInfo(x_reg); 626 // 64bit X register's master storage should refer to itself. 627 DCHECK_EQ(x_reg_info, x_reg_info->Master()); 628 // Redirect 32bit W master storage to 64bit X. 629 info->SetMaster(x_reg_info); 630 // 32bit W should show a single 32-bit mask bit, at first referring to the low half. 631 DCHECK_EQ(info->StorageMask(), 0x1U); 632 } 633 634 // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. 635 // TODO: adjust when we roll to hard float calling convention. 636 reg_pool_->next_core_reg_ = 2; 637 reg_pool_->next_sp_reg_ = 0; 638 reg_pool_->next_dp_reg_ = 0; 639} 640 641/* 642 * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some 643 * instructions might call out to C/assembly helper functions. Until 644 * machinery is in place, always spill lr. 645 */ 646 647void Arm64Mir2Lir::AdjustSpillMask() { 648 core_spill_mask_ |= (1 << rs_xLR.GetRegNum()); 649 num_core_spills_++; 650} 651 652/* Clobber all regs that might be used by an external C call */ 653void Arm64Mir2Lir::ClobberCallerSave() { 654 Clobber(rs_x0); 655 Clobber(rs_x1); 656 Clobber(rs_x2); 657 Clobber(rs_x3); 658 Clobber(rs_x4); 659 Clobber(rs_x5); 660 Clobber(rs_x6); 661 Clobber(rs_x7); 662 Clobber(rs_x8); 663 Clobber(rs_x9); 664 Clobber(rs_x10); 665 Clobber(rs_x11); 666 Clobber(rs_x12); 667 Clobber(rs_x13); 668 Clobber(rs_x14); 669 Clobber(rs_x15); 670 Clobber(rs_x16); 671 Clobber(rs_x17); 672 Clobber(rs_x30); 673 674 Clobber(rs_f0); 675 Clobber(rs_f1); 676 Clobber(rs_f2); 677 Clobber(rs_f3); 678 Clobber(rs_f4); 679 Clobber(rs_f5); 680 Clobber(rs_f6); 681 Clobber(rs_f7); 682 Clobber(rs_f16); 683 Clobber(rs_f17); 684 Clobber(rs_f18); 685 Clobber(rs_f19); 686 Clobber(rs_f20); 687 Clobber(rs_f21); 688 Clobber(rs_f22); 689 Clobber(rs_f23); 690 Clobber(rs_f24); 691 Clobber(rs_f25); 692 Clobber(rs_f26); 693 Clobber(rs_f27); 694 Clobber(rs_f28); 695 Clobber(rs_f29); 696 Clobber(rs_f30); 697 Clobber(rs_f31); 698} 699 700RegLocation Arm64Mir2Lir::GetReturnWideAlt() { 701 RegLocation res = LocCReturnWide(); 702 res.reg.SetReg(rx2); 703 res.reg.SetHighReg(rx3); 704 Clobber(rs_x2); 705 Clobber(rs_x3); 706 MarkInUse(rs_x2); 707 MarkInUse(rs_x3); 708 MarkWide(res.reg); 709 return res; 710} 711 712RegLocation Arm64Mir2Lir::GetReturnAlt() { 713 RegLocation res = LocCReturn(); 714 res.reg.SetReg(rx1); 715 Clobber(rs_x1); 716 MarkInUse(rs_x1); 717 return res; 718} 719 720/* To be used when explicitly managing register use */ 721void Arm64Mir2Lir::LockCallTemps() { 722 // TODO: needs cleanup. 723 LockTemp(rs_x0); 724 LockTemp(rs_x1); 725 LockTemp(rs_x2); 726 LockTemp(rs_x3); 727 LockTemp(rs_x4); 728 LockTemp(rs_x5); 729 LockTemp(rs_x6); 730 LockTemp(rs_x7); 731 LockTemp(rs_f0); 732 LockTemp(rs_f1); 733 LockTemp(rs_f2); 734 LockTemp(rs_f3); 735 LockTemp(rs_f4); 736 LockTemp(rs_f5); 737 LockTemp(rs_f6); 738 LockTemp(rs_f7); 739} 740 741/* To be used when explicitly managing register use */ 742void Arm64Mir2Lir::FreeCallTemps() { 743 // TODO: needs cleanup. 744 FreeTemp(rs_x0); 745 FreeTemp(rs_x1); 746 FreeTemp(rs_x2); 747 FreeTemp(rs_x3); 748 FreeTemp(rs_x4); 749 FreeTemp(rs_x5); 750 FreeTemp(rs_x6); 751 FreeTemp(rs_x7); 752 FreeTemp(rs_f0); 753 FreeTemp(rs_f1); 754 FreeTemp(rs_f2); 755 FreeTemp(rs_f3); 756 FreeTemp(rs_f4); 757 FreeTemp(rs_f5); 758 FreeTemp(rs_f6); 759 FreeTemp(rs_f7); 760} 761 762RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<4> offset) { 763 UNIMPLEMENTED(FATAL) << "Should not be called."; 764 return RegStorage::InvalidReg(); 765} 766 767RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<8> offset) { 768 // TODO(Arm64): use LoadWordDisp instead. 769 // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); 770 LoadBaseDisp(rs_xSELF, offset.Int32Value(), rs_xLR, k64, kNotVolatile); 771 return rs_xLR; 772} 773 774LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { 775 RegStorage tmp = rs_x0; 776 LoadWordDisp(rs_xSELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); 777 LIR* load2 = LoadWordDisp(tmp, 0, tmp); 778 return load2; 779} 780 781uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { 782 DCHECK(!IsPseudoLirOp(opcode)); 783 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; 784} 785 786const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { 787 DCHECK(!IsPseudoLirOp(opcode)); 788 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; 789} 790 791const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { 792 DCHECK(!IsPseudoLirOp(opcode)); 793 return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; 794} 795 796RegStorage Arm64Mir2Lir::InToRegStorageArm64Mapper::GetNextReg(bool is_double_or_float, 797 bool is_wide, 798 bool is_ref) { 799 const RegStorage coreArgMappingToPhysicalReg[] = 800 {rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7}; 801 const int coreArgMappingToPhysicalRegSize = 802 sizeof(coreArgMappingToPhysicalReg) / sizeof(RegStorage); 803 const RegStorage fpArgMappingToPhysicalReg[] = 804 {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7}; 805 const int fpArgMappingToPhysicalRegSize = 806 sizeof(fpArgMappingToPhysicalReg) / sizeof(RegStorage); 807 808 RegStorage result = RegStorage::InvalidReg(); 809 if (is_double_or_float) { 810 if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { 811 DCHECK(!is_ref); 812 result = fpArgMappingToPhysicalReg[cur_fp_reg_++]; 813 if (result.Valid()) { 814 // TODO: switching between widths remains a bit ugly. Better way? 815 int res_reg = result.GetReg(); 816 result = is_wide ? RegStorage::FloatSolo64(res_reg) : RegStorage::FloatSolo32(res_reg); 817 } 818 } 819 } else { 820 if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { 821 result = coreArgMappingToPhysicalReg[cur_core_reg_++]; 822 if (result.Valid()) { 823 // TODO: switching between widths remains a bit ugly. Better way? 824 int res_reg = result.GetReg(); 825 DCHECK(!(is_wide && is_ref)); 826 result = (is_wide || is_ref) ? RegStorage::Solo64(res_reg) : RegStorage::Solo32(res_reg); 827 } 828 } 829 } 830 return result; 831} 832 833RegStorage Arm64Mir2Lir::InToRegStorageMapping::Get(int in_position) { 834 DCHECK(IsInitialized()); 835 auto res = mapping_.find(in_position); 836 return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); 837} 838 839void Arm64Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, 840 InToRegStorageMapper* mapper) { 841 DCHECK(mapper != nullptr); 842 max_mapped_in_ = -1; 843 is_there_stack_mapped_ = false; 844 for (int in_position = 0; in_position < count; in_position++) { 845 RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, 846 arg_locs[in_position].wide, 847 arg_locs[in_position].ref); 848 if (reg.Valid()) { 849 mapping_[in_position] = reg; 850 if (arg_locs[in_position].wide) { 851 // We covered 2 args, so skip the next one 852 in_position++; 853 } 854 max_mapped_in_ = std::max(max_mapped_in_, in_position); 855 } else { 856 is_there_stack_mapped_ = true; 857 } 858 } 859 initialized_ = true; 860} 861 862 863// Deprecate. Use the new mechanism. 864// TODO(Arm64): reuse info in QuickArgumentVisitor? 865static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used, 866 OpSize* op_size) { 867 if (loc->fp) { 868 int n = *num_fpr_used; 869 if (n < 8) { 870 *num_fpr_used = n + 1; 871 RegStorage::RegStorageKind reg_kind; 872 if (loc->wide) { 873 *op_size = kDouble; 874 reg_kind = RegStorage::k64BitSolo; 875 } else { 876 *op_size = kSingle; 877 reg_kind = RegStorage::k32BitSolo; 878 } 879 return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n); 880 } 881 } else { 882 int n = *num_gpr_used; 883 if (n < 8) { 884 *num_gpr_used = n + 1; 885 if (loc->wide || loc->ref) { 886 *op_size = k64; 887 return RegStorage::Solo64(n); 888 } else { 889 *op_size = k32; 890 return RegStorage::Solo32(n); 891 } 892 } 893 } 894 *op_size = kWord; 895 return RegStorage::InvalidReg(); 896} 897 898RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { 899 if (!in_to_reg_storage_mapping_.IsInitialized()) { 900 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 901 RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; 902 903 InToRegStorageArm64Mapper mapper; 904 in_to_reg_storage_mapping_.Initialize(arg_locs, cu_->num_ins, &mapper); 905 } 906 return in_to_reg_storage_mapping_.Get(arg_num); 907} 908 909 910/* 911 * If there are any ins passed in registers that have not been promoted 912 * to a callee-save register, flush them to the frame. Perform initial 913 * assignment of promoted arguments. 914 * 915 * ArgLocs is an array of location records describing the incoming arguments 916 * with one location record per word of argument. 917 */ 918void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 919 int num_gpr_used = 1; 920 int num_fpr_used = 0; 921 922 /* 923 * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod> 924 * It will attempt to keep kArg0 live (or copy it to home location 925 * if promoted). 926 */ 927 RegLocation rl_src = rl_method; 928 rl_src.location = kLocPhysReg; 929 rl_src.reg = TargetReg(kArg0); 930 rl_src.home = false; 931 MarkLive(rl_src); 932 StoreValue(rl_method, rl_src); 933 // If Method* has been promoted, explicitly flush 934 if (rl_method.location == kLocPhysReg) { 935 StoreRefDisp(TargetReg(kSp), 0, TargetReg(kArg0), kNotVolatile); 936 } 937 938 if (cu_->num_ins == 0) { 939 return; 940 } 941 942 // Handle dalvik registers. 943 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 944 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 945 for (int i = 0; i < cu_->num_ins; i++) { 946 RegLocation* t_loc = &ArgLocs[i]; 947 OpSize op_size; 948 RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size); 949 950 if (reg.Valid()) { 951 // If arriving in register. 952 953 // We have already updated the arg location with promoted info 954 // so we can be based on it. 955 if (t_loc->location == kLocPhysReg) { 956 // Just copy it. 957 OpRegCopy(t_loc->reg, reg); 958 } else { 959 // Needs flush. 960 if (t_loc->ref) { 961 StoreRefDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, kNotVolatile); 962 } else { 963 StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, 964 kNotVolatile); 965 } 966 } 967 } else { 968 // If arriving in frame & promoted. 969 if (t_loc->location == kLocPhysReg) { 970 if (t_loc->ref) { 971 LoadRefDisp(TargetReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); 972 } else { 973 LoadBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), t_loc->reg, 974 t_loc->wide ? k64 : k32, kNotVolatile); 975 } 976 } 977 } 978 if (t_loc->wide) { 979 // Increment i to skip the next one. 980 i++; 981 } 982 // if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 983 // OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); 984 // } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 985 // OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg); 986 // } else { 987 // StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size, kNotVolatile); 988 // if (reg.Is64Bit()) { 989 // if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) { 990 // LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots"; 991 // } 992 // i += 1; 993 // } 994 // } 995 // } else { 996 // // If arriving in frame & promoted 997 // if (v_map->core_location == kLocPhysReg) { 998 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 999 // RegStorage::Solo32(v_map->core_reg)); 1000 // } 1001 // if (v_map->fp_location == kLocPhysReg) { 1002 // LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->fp_reg)); 1003 // } 1004 } 1005} 1006 1007/* 1008 * Load up to 5 arguments, the first three of which will be in 1009 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 1010 * and as part of the load sequence, it must be replaced with 1011 * the target method pointer. 1012 */ 1013int Arm64Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 1014 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 1015 const MethodReference& target_method, 1016 uint32_t vtable_idx, uintptr_t direct_code, 1017 uintptr_t direct_method, InvokeType type, bool skip_this) { 1018 return GenDalvikArgsRange(info, 1019 call_state, pcrLabel, next_call_insn, 1020 target_method, 1021 vtable_idx, direct_code, 1022 direct_method, type, skip_this); 1023} 1024 1025/* 1026 * May have 0+ arguments (also used for jumbo). Note that 1027 * source virtual registers may be in physical registers, so may 1028 * need to be flushed to home location before copying. This 1029 * applies to arg3 and above (see below). 1030 * 1031 * FIXME: update comments. 1032 * 1033 * Two general strategies: 1034 * If < 20 arguments 1035 * Pass args 3-18 using vldm/vstm block copy 1036 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1037 * If 20+ arguments 1038 * Pass args arg19+ using memcpy block copy 1039 * Pass arg0, arg1 & arg2 in kArg1-kArg3 1040 * 1041 */ 1042int Arm64Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 1043 LIR** pcrLabel, NextCallInsn next_call_insn, 1044 const MethodReference& target_method, 1045 uint32_t vtable_idx, uintptr_t direct_code, 1046 uintptr_t direct_method, InvokeType type, bool skip_this) { 1047 /* If no arguments, just return */ 1048 if (info->num_arg_words == 0) 1049 return call_state; 1050 1051 const int start_index = skip_this ? 1 : 0; 1052 1053 InToRegStorageArm64Mapper mapper; 1054 InToRegStorageMapping in_to_reg_storage_mapping; 1055 in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); 1056 const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); 1057 int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + 1); 1058 1059 // Fisrt of all, check whether it make sense to use bulk copying 1060 // Optimization is aplicable only for range case 1061 // TODO: make a constant instead of 2 1062 if (info->is_range && regs_left_to_pass_via_stack >= 2) { 1063 // Scan the rest of the args - if in phys_reg flush to memory 1064 for (int next_arg = last_mapped_in + 1; next_arg < info->num_arg_words;) { 1065 RegLocation loc = info->args[next_arg]; 1066 if (loc.wide) { 1067 loc = UpdateLocWide(loc); 1068 if (loc.location == kLocPhysReg) { 1069 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1070 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); 1071 } 1072 next_arg += 2; 1073 } else { 1074 loc = UpdateLoc(loc); 1075 if (loc.location == kLocPhysReg) { 1076 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1077 if (loc.ref) { 1078 StoreRefDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); 1079 } else { 1080 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); 1081 } 1082 } 1083 next_arg++; 1084 } 1085 } 1086 1087 // Logic below assumes that Method pointer is at offset zero from SP. 1088 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 1089 1090 // The rest can be copied together 1091 int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low); 1092 int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + 1, 1093 cu_->instruction_set); 1094 1095 int current_src_offset = start_offset; 1096 int current_dest_offset = outs_offset; 1097 1098 // Only davik regs are accessed in this loop; no next_call_insn() calls. 1099 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1100 while (regs_left_to_pass_via_stack > 0) { 1101 /* 1102 * TODO: Improve by adding block copy for large number of arguments. This 1103 * should be done, if possible, as a target-depending helper. For now, just 1104 * copy a Dalvik vreg at a time. 1105 */ 1106 // Moving 32-bits via general purpose register. 1107 size_t bytes_to_move = sizeof(uint32_t); 1108 1109 // Instead of allocating a new temp, simply reuse one of the registers being used 1110 // for argument passing. 1111 RegStorage temp = TargetReg(kArg3, false); 1112 1113 // Now load the argument VR and store to the outs. 1114 Load32Disp(TargetReg(kSp), current_src_offset, temp); 1115 Store32Disp(TargetReg(kSp), current_dest_offset, temp); 1116 1117 current_src_offset += bytes_to_move; 1118 current_dest_offset += bytes_to_move; 1119 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 1120 } 1121 DCHECK_EQ(regs_left_to_pass_via_stack, 0); 1122 } 1123 1124 // Now handle rest not registers if they are 1125 if (in_to_reg_storage_mapping.IsThereStackMapped()) { 1126 RegStorage regSingle = TargetReg(kArg2); 1127 RegStorage regWide = RegStorage::Solo64(TargetReg(kArg3).GetReg()); 1128 for (int i = start_index; i <= last_mapped_in + regs_left_to_pass_via_stack; i++) { 1129 RegLocation rl_arg = info->args[i]; 1130 rl_arg = UpdateRawLoc(rl_arg); 1131 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1132 if (!reg.Valid()) { 1133 int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); 1134 1135 { 1136 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1137 if (rl_arg.wide) { 1138 if (rl_arg.location == kLocPhysReg) { 1139 StoreBaseDisp(TargetReg(kSp), out_offset, rl_arg.reg, k64, kNotVolatile); 1140 } else { 1141 LoadValueDirectWideFixed(rl_arg, regWide); 1142 StoreBaseDisp(TargetReg(kSp), out_offset, regWide, k64, kNotVolatile); 1143 } 1144 i++; 1145 } else { 1146 if (rl_arg.location == kLocPhysReg) { 1147 if (rl_arg.ref) { 1148 StoreRefDisp(TargetReg(kSp), out_offset, rl_arg.reg, kNotVolatile); 1149 } else { 1150 StoreBaseDisp(TargetReg(kSp), out_offset, rl_arg.reg, k32, kNotVolatile); 1151 } 1152 } else { 1153 if (rl_arg.ref) { 1154 LoadValueDirectFixed(rl_arg, regSingle); 1155 StoreRefDisp(TargetReg(kSp), out_offset, regSingle, kNotVolatile); 1156 } else { 1157 LoadValueDirectFixed(rl_arg, As32BitReg(regSingle)); 1158 StoreBaseDisp(TargetReg(kSp), out_offset, As32BitReg(regSingle), k32, kNotVolatile); 1159 } 1160 } 1161 } 1162 } 1163 call_state = next_call_insn(cu_, info, call_state, target_method, 1164 vtable_idx, direct_code, direct_method, type); 1165 } 1166 } 1167 } 1168 1169 // Finish with mapped registers 1170 for (int i = start_index; i <= last_mapped_in; i++) { 1171 RegLocation rl_arg = info->args[i]; 1172 rl_arg = UpdateRawLoc(rl_arg); 1173 RegStorage reg = in_to_reg_storage_mapping.Get(i); 1174 if (reg.Valid()) { 1175 if (rl_arg.wide) { 1176 LoadValueDirectWideFixed(rl_arg, reg); 1177 i++; 1178 } else { 1179 LoadValueDirectFixed(rl_arg, reg); 1180 } 1181 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1182 direct_code, direct_method, type); 1183 } 1184 } 1185 1186 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1187 direct_code, direct_method, type); 1188 if (pcrLabel) { 1189 if (cu_->compiler_driver->GetCompilerOptions().GetExplicitNullChecks()) { 1190 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1), info->opt_flags); 1191 } else { 1192 *pcrLabel = nullptr; 1193 // In lieu of generating a check for kArg1 being null, we need to 1194 // perform a load when doing implicit checks. 1195 RegStorage tmp = AllocTemp(); 1196 Load32Disp(TargetReg(kArg1), 0, tmp); 1197 MarkPossibleNullPointerException(info->opt_flags); 1198 FreeTemp(tmp); 1199 } 1200 } 1201 return call_state; 1202} 1203 1204} // namespace art 1205