call_mips.cc revision 0d82948094d9a198e01aa95f64012bdedd5b6fc9
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the Mips ISA */ 18 19#include "codegen_mips.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "entrypoints/quick/quick_entrypoints.h" 22#include "mips_lir.h" 23 24namespace art { 25 26void MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, 27 SpecialCaseHandler special_case) { 28 // TODO 29} 30 31/* 32 * The lack of pc-relative loads on Mips presents somewhat of a challenge 33 * for our PIC switch table strategy. To materialize the current location 34 * we'll do a dummy JAL and reference our tables using r_RA as the 35 * base register. Note that r_RA will be used both as the base to 36 * locate the switch table data and as the reference base for the switch 37 * target offsets stored in the table. We'll use a special pseudo-instruction 38 * to represent the jal and trigger the construction of the 39 * switch table offsets (which will happen after final assembly and all 40 * labels are fixed). 41 * 42 * The test loop will look something like: 43 * 44 * ori rEnd, r_ZERO, #table_size ; size in bytes 45 * jal BaseLabel ; stores "return address" (BaseLabel) in r_RA 46 * nop ; opportunistically fill 47 * BaseLabel: 48 * addiu rBase, r_RA, <table> - <BaseLabel> ; table relative to BaseLabel 49 addu rEnd, rEnd, rBase ; end of table 50 * lw r_val, [rSP, v_reg_off] ; Test Value 51 * loop: 52 * beq rBase, rEnd, done 53 * lw r_key, 0(rBase) 54 * addu rBase, 8 55 * bne r_val, r_key, loop 56 * lw r_disp, -4(rBase) 57 * addu r_RA, r_disp 58 * jr r_RA 59 * done: 60 * 61 */ 62void MipsMir2Lir::GenSparseSwitch(MIR* mir, DexOffset table_offset, 63 RegLocation rl_src) { 64 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 65 if (cu_->verbose) { 66 DumpSparseSwitchTable(table); 67 } 68 // Add the table to the list - we'll process it later 69 SwitchTable* tab_rec = 70 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); 71 tab_rec->table = table; 72 tab_rec->vaddr = current_dalvik_offset_; 73 int elements = table[1]; 74 tab_rec->targets = 75 static_cast<LIR**>(arena_->Alloc(elements * sizeof(LIR*), ArenaAllocator::kAllocLIR)); 76 switch_tables_.Insert(tab_rec); 77 78 // The table is composed of 8-byte key/disp pairs 79 int byte_size = elements * 8; 80 81 int size_hi = byte_size >> 16; 82 int size_lo = byte_size & 0xffff; 83 84 int rEnd = AllocTemp(); 85 if (size_hi) { 86 NewLIR2(kMipsLui, rEnd, size_hi); 87 } 88 // Must prevent code motion for the curr pc pair 89 GenBarrier(); // Scheduling barrier 90 NewLIR0(kMipsCurrPC); // Really a jal to .+8 91 // Now, fill the branch delay slot 92 if (size_hi) { 93 NewLIR3(kMipsOri, rEnd, rEnd, size_lo); 94 } else { 95 NewLIR3(kMipsOri, rEnd, r_ZERO, size_lo); 96 } 97 GenBarrier(); // Scheduling barrier 98 99 // Construct BaseLabel and set up table base register 100 LIR* base_label = NewLIR0(kPseudoTargetLabel); 101 // Remember base label so offsets can be computed later 102 tab_rec->anchor = base_label; 103 int rBase = AllocTemp(); 104 NewLIR4(kMipsDelta, rBase, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 105 OpRegRegReg(kOpAdd, rEnd, rEnd, rBase); 106 107 // Grab switch test value 108 rl_src = LoadValue(rl_src, kCoreReg); 109 110 // Test loop 111 int r_key = AllocTemp(); 112 LIR* loop_label = NewLIR0(kPseudoTargetLabel); 113 LIR* exit_branch = OpCmpBranch(kCondEq, rBase, rEnd, NULL); 114 LoadWordDisp(rBase, 0, r_key); 115 OpRegImm(kOpAdd, rBase, 8); 116 OpCmpBranch(kCondNe, rl_src.low_reg, r_key, loop_label); 117 int r_disp = AllocTemp(); 118 LoadWordDisp(rBase, -4, r_disp); 119 OpRegRegReg(kOpAdd, r_RA, r_RA, r_disp); 120 OpReg(kOpBx, r_RA); 121 122 // Loop exit 123 LIR* exit_label = NewLIR0(kPseudoTargetLabel); 124 exit_branch->target = exit_label; 125} 126 127/* 128 * Code pattern will look something like: 129 * 130 * lw r_val 131 * jal BaseLabel ; stores "return address" (BaseLabel) in r_RA 132 * nop ; opportunistically fill 133 * [subiu r_val, bias] ; Remove bias if low_val != 0 134 * bound check -> done 135 * lw r_disp, [r_RA, r_val] 136 * addu r_RA, r_disp 137 * jr r_RA 138 * done: 139 */ 140void MipsMir2Lir::GenPackedSwitch(MIR* mir, DexOffset table_offset, 141 RegLocation rl_src) { 142 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 143 if (cu_->verbose) { 144 DumpPackedSwitchTable(table); 145 } 146 // Add the table to the list - we'll process it later 147 SwitchTable* tab_rec = 148 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); 149 tab_rec->table = table; 150 tab_rec->vaddr = current_dalvik_offset_; 151 int size = table[1]; 152 tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), 153 ArenaAllocator::kAllocLIR)); 154 switch_tables_.Insert(tab_rec); 155 156 // Get the switch value 157 rl_src = LoadValue(rl_src, kCoreReg); 158 159 // Prepare the bias. If too big, handle 1st stage here 160 int low_key = s4FromSwitchData(&table[2]); 161 bool large_bias = false; 162 int r_key; 163 if (low_key == 0) { 164 r_key = rl_src.low_reg; 165 } else if ((low_key & 0xffff) != low_key) { 166 r_key = AllocTemp(); 167 LoadConstant(r_key, low_key); 168 large_bias = true; 169 } else { 170 r_key = AllocTemp(); 171 } 172 173 // Must prevent code motion for the curr pc pair 174 GenBarrier(); 175 NewLIR0(kMipsCurrPC); // Really a jal to .+8 176 // Now, fill the branch delay slot with bias strip 177 if (low_key == 0) { 178 NewLIR0(kMipsNop); 179 } else { 180 if (large_bias) { 181 OpRegRegReg(kOpSub, r_key, rl_src.low_reg, r_key); 182 } else { 183 OpRegRegImm(kOpSub, r_key, rl_src.low_reg, low_key); 184 } 185 } 186 GenBarrier(); // Scheduling barrier 187 188 // Construct BaseLabel and set up table base register 189 LIR* base_label = NewLIR0(kPseudoTargetLabel); 190 // Remember base label so offsets can be computed later 191 tab_rec->anchor = base_label; 192 193 // Bounds check - if < 0 or >= size continue following switch 194 LIR* branch_over = OpCmpImmBranch(kCondHi, r_key, size-1, NULL); 195 196 // Materialize the table base pointer 197 int rBase = AllocTemp(); 198 NewLIR4(kMipsDelta, rBase, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 199 200 // Load the displacement from the switch table 201 int r_disp = AllocTemp(); 202 LoadBaseIndexed(rBase, r_key, r_disp, 2, kWord); 203 204 // Add to r_AP and go 205 OpRegRegReg(kOpAdd, r_RA, r_RA, r_disp); 206 OpReg(kOpBx, r_RA); 207 208 /* branch_over target here */ 209 LIR* target = NewLIR0(kPseudoTargetLabel); 210 branch_over->target = target; 211} 212 213/* 214 * Array data table format: 215 * ushort ident = 0x0300 magic value 216 * ushort width width of each element in the table 217 * uint size number of elements in the table 218 * ubyte data[size*width] table of data values (may contain a single-byte 219 * padding at the end) 220 * 221 * Total size is 4+(width * size + 1)/2 16-bit code units. 222 */ 223void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { 224 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 225 // Add the table to the list - we'll process it later 226 FillArrayData* tab_rec = 227 reinterpret_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), 228 ArenaAllocator::kAllocData)); 229 tab_rec->table = table; 230 tab_rec->vaddr = current_dalvik_offset_; 231 uint16_t width = tab_rec->table[1]; 232 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); 233 tab_rec->size = (size * width) + 8; 234 235 fill_array_data_.Insert(tab_rec); 236 237 // Making a call - use explicit registers 238 FlushAllRegs(); /* Everything to home location */ 239 LockCallTemps(); 240 LoadValueDirectFixed(rl_src, rMIPS_ARG0); 241 242 // Must prevent code motion for the curr pc pair 243 GenBarrier(); 244 NewLIR0(kMipsCurrPC); // Really a jal to .+8 245 // Now, fill the branch delay slot with the helper load 246 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData)); 247 GenBarrier(); // Scheduling barrier 248 249 // Construct BaseLabel and set up table base register 250 LIR* base_label = NewLIR0(kPseudoTargetLabel); 251 252 // Materialize a pointer to the fill data image 253 NewLIR4(kMipsDelta, rMIPS_ARG1, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 254 255 // And go... 256 ClobberCalleeSave(); 257 LIR* call_inst = OpReg(kOpBlx, r_tgt); // ( array*, fill_data* ) 258 MarkSafepointPC(call_inst); 259} 260 261void MipsMir2Lir::GenMoveException(RegLocation rl_dest) { 262 int ex_offset = Thread::ExceptionOffset().Int32Value(); 263 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 264 int reset_reg = AllocTemp(); 265 LoadWordDisp(rMIPS_SELF, ex_offset, rl_result.low_reg); 266 LoadConstant(reset_reg, 0); 267 StoreWordDisp(rMIPS_SELF, ex_offset, reset_reg); 268 FreeTemp(reset_reg); 269 StoreValue(rl_dest, rl_result); 270} 271 272/* 273 * Mark garbage collection card. Skip if the value we're storing is null. 274 */ 275void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) { 276 int reg_card_base = AllocTemp(); 277 int reg_card_no = AllocTemp(); 278 LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); 279 LoadWordDisp(rMIPS_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base); 280 OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); 281 StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, 282 kUnsignedByte); 283 LIR* target = NewLIR0(kPseudoTargetLabel); 284 branch_over->target = target; 285 FreeTemp(reg_card_base); 286 FreeTemp(reg_card_no); 287} 288 289void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 290 int spill_count = num_core_spills_ + num_fp_spills_; 291 /* 292 * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register 293 * allocation mechanism know so it doesn't try to use any of them when 294 * expanding the frame or flushing. This leaves the utility 295 * code with a single temp: r12. This should be enough. 296 */ 297 LockTemp(rMIPS_ARG0); 298 LockTemp(rMIPS_ARG1); 299 LockTemp(rMIPS_ARG2); 300 LockTemp(rMIPS_ARG3); 301 302 /* 303 * We can safely skip the stack overflow check if we're 304 * a leaf *and* our frame size < fudge factor. 305 */ 306 bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && 307 (static_cast<size_t>(frame_size_) < Thread::kStackOverflowReservedBytes)); 308 NewLIR0(kPseudoMethodEntry); 309 int check_reg = AllocTemp(); 310 int new_sp = AllocTemp(); 311 if (!skip_overflow_check) { 312 /* Load stack limit */ 313 LoadWordDisp(rMIPS_SELF, Thread::StackEndOffset().Int32Value(), check_reg); 314 } 315 /* Spill core callee saves */ 316 SpillCoreRegs(); 317 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */ 318 DCHECK_EQ(num_fp_spills_, 0); 319 if (!skip_overflow_check) { 320 OpRegRegImm(kOpSub, new_sp, rMIPS_SP, frame_size_ - (spill_count * 4)); 321 GenRegRegCheck(kCondCc, new_sp, check_reg, kThrowStackOverflow); 322 OpRegCopy(rMIPS_SP, new_sp); // Establish stack 323 } else { 324 OpRegImm(kOpSub, rMIPS_SP, frame_size_ - (spill_count * 4)); 325 } 326 327 FlushIns(ArgLocs, rl_method); 328 329 FreeTemp(rMIPS_ARG0); 330 FreeTemp(rMIPS_ARG1); 331 FreeTemp(rMIPS_ARG2); 332 FreeTemp(rMIPS_ARG3); 333} 334 335void MipsMir2Lir::GenExitSequence() { 336 /* 337 * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't 338 * allocated by the register utilities as temps. 339 */ 340 LockTemp(rMIPS_RET0); 341 LockTemp(rMIPS_RET1); 342 343 NewLIR0(kPseudoMethodExit); 344 UnSpillCoreRegs(); 345 OpReg(kOpBx, r_RA); 346} 347 348} // namespace art 349