call_mips.cc revision 3bc01748ef1c3e43361bdf520947a9d656658bf8
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the Mips ISA */ 18 19#include "codegen_mips.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "entrypoints/quick/quick_entrypoints.h" 22#include "mips_lir.h" 23 24namespace art { 25 26bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, 27 const InlineMethod& special) { 28 // TODO 29 return false; 30} 31 32/* 33 * The lack of pc-relative loads on Mips presents somewhat of a challenge 34 * for our PIC switch table strategy. To materialize the current location 35 * we'll do a dummy JAL and reference our tables using r_RA as the 36 * base register. Note that r_RA will be used both as the base to 37 * locate the switch table data and as the reference base for the switch 38 * target offsets stored in the table. We'll use a special pseudo-instruction 39 * to represent the jal and trigger the construction of the 40 * switch table offsets (which will happen after final assembly and all 41 * labels are fixed). 42 * 43 * The test loop will look something like: 44 * 45 * ori rEnd, r_ZERO, #table_size ; size in bytes 46 * jal BaseLabel ; stores "return address" (BaseLabel) in r_RA 47 * nop ; opportunistically fill 48 * BaseLabel: 49 * addiu rBase, r_RA, <table> - <BaseLabel> ; table relative to BaseLabel 50 addu rEnd, rEnd, rBase ; end of table 51 * lw r_val, [rSP, v_reg_off] ; Test Value 52 * loop: 53 * beq rBase, rEnd, done 54 * lw r_key, 0(rBase) 55 * addu rBase, 8 56 * bne r_val, r_key, loop 57 * lw r_disp, -4(rBase) 58 * addu r_RA, r_disp 59 * jr r_RA 60 * done: 61 * 62 */ 63void MipsMir2Lir::GenSparseSwitch(MIR* mir, DexOffset table_offset, 64 RegLocation rl_src) { 65 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 66 if (cu_->verbose) { 67 DumpSparseSwitchTable(table); 68 } 69 // Add the table to the list - we'll process it later 70 SwitchTable* tab_rec = 71 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); 72 tab_rec->table = table; 73 tab_rec->vaddr = current_dalvik_offset_; 74 int elements = table[1]; 75 tab_rec->targets = 76 static_cast<LIR**>(arena_->Alloc(elements * sizeof(LIR*), ArenaAllocator::kAllocLIR)); 77 switch_tables_.Insert(tab_rec); 78 79 // The table is composed of 8-byte key/disp pairs 80 int byte_size = elements * 8; 81 82 int size_hi = byte_size >> 16; 83 int size_lo = byte_size & 0xffff; 84 85 int rEnd = AllocTemp(); 86 if (size_hi) { 87 NewLIR2(kMipsLui, rEnd, size_hi); 88 } 89 // Must prevent code motion for the curr pc pair 90 GenBarrier(); // Scheduling barrier 91 NewLIR0(kMipsCurrPC); // Really a jal to .+8 92 // Now, fill the branch delay slot 93 if (size_hi) { 94 NewLIR3(kMipsOri, rEnd, rEnd, size_lo); 95 } else { 96 NewLIR3(kMipsOri, rEnd, r_ZERO, size_lo); 97 } 98 GenBarrier(); // Scheduling barrier 99 100 // Construct BaseLabel and set up table base register 101 LIR* base_label = NewLIR0(kPseudoTargetLabel); 102 // Remember base label so offsets can be computed later 103 tab_rec->anchor = base_label; 104 int rBase = AllocTemp(); 105 NewLIR4(kMipsDelta, rBase, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 106 OpRegRegReg(kOpAdd, rEnd, rEnd, rBase); 107 108 // Grab switch test value 109 rl_src = LoadValue(rl_src, kCoreReg); 110 111 // Test loop 112 int r_key = AllocTemp(); 113 LIR* loop_label = NewLIR0(kPseudoTargetLabel); 114 LIR* exit_branch = OpCmpBranch(kCondEq, rBase, rEnd, NULL); 115 LoadWordDisp(rBase, 0, r_key); 116 OpRegImm(kOpAdd, rBase, 8); 117 OpCmpBranch(kCondNe, rl_src.low_reg, r_key, loop_label); 118 int r_disp = AllocTemp(); 119 LoadWordDisp(rBase, -4, r_disp); 120 OpRegRegReg(kOpAdd, r_RA, r_RA, r_disp); 121 OpReg(kOpBx, r_RA); 122 123 // Loop exit 124 LIR* exit_label = NewLIR0(kPseudoTargetLabel); 125 exit_branch->target = exit_label; 126} 127 128/* 129 * Code pattern will look something like: 130 * 131 * lw r_val 132 * jal BaseLabel ; stores "return address" (BaseLabel) in r_RA 133 * nop ; opportunistically fill 134 * [subiu r_val, bias] ; Remove bias if low_val != 0 135 * bound check -> done 136 * lw r_disp, [r_RA, r_val] 137 * addu r_RA, r_disp 138 * jr r_RA 139 * done: 140 */ 141void MipsMir2Lir::GenPackedSwitch(MIR* mir, DexOffset table_offset, 142 RegLocation rl_src) { 143 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 144 if (cu_->verbose) { 145 DumpPackedSwitchTable(table); 146 } 147 // Add the table to the list - we'll process it later 148 SwitchTable* tab_rec = 149 static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); 150 tab_rec->table = table; 151 tab_rec->vaddr = current_dalvik_offset_; 152 int size = table[1]; 153 tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), 154 ArenaAllocator::kAllocLIR)); 155 switch_tables_.Insert(tab_rec); 156 157 // Get the switch value 158 rl_src = LoadValue(rl_src, kCoreReg); 159 160 // Prepare the bias. If too big, handle 1st stage here 161 int low_key = s4FromSwitchData(&table[2]); 162 bool large_bias = false; 163 int r_key; 164 if (low_key == 0) { 165 r_key = rl_src.low_reg; 166 } else if ((low_key & 0xffff) != low_key) { 167 r_key = AllocTemp(); 168 LoadConstant(r_key, low_key); 169 large_bias = true; 170 } else { 171 r_key = AllocTemp(); 172 } 173 174 // Must prevent code motion for the curr pc pair 175 GenBarrier(); 176 NewLIR0(kMipsCurrPC); // Really a jal to .+8 177 // Now, fill the branch delay slot with bias strip 178 if (low_key == 0) { 179 NewLIR0(kMipsNop); 180 } else { 181 if (large_bias) { 182 OpRegRegReg(kOpSub, r_key, rl_src.low_reg, r_key); 183 } else { 184 OpRegRegImm(kOpSub, r_key, rl_src.low_reg, low_key); 185 } 186 } 187 GenBarrier(); // Scheduling barrier 188 189 // Construct BaseLabel and set up table base register 190 LIR* base_label = NewLIR0(kPseudoTargetLabel); 191 // Remember base label so offsets can be computed later 192 tab_rec->anchor = base_label; 193 194 // Bounds check - if < 0 or >= size continue following switch 195 LIR* branch_over = OpCmpImmBranch(kCondHi, r_key, size-1, NULL); 196 197 // Materialize the table base pointer 198 int rBase = AllocTemp(); 199 NewLIR4(kMipsDelta, rBase, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 200 201 // Load the displacement from the switch table 202 int r_disp = AllocTemp(); 203 LoadBaseIndexed(rBase, r_key, r_disp, 2, kWord); 204 205 // Add to r_AP and go 206 OpRegRegReg(kOpAdd, r_RA, r_RA, r_disp); 207 OpReg(kOpBx, r_RA); 208 209 /* branch_over target here */ 210 LIR* target = NewLIR0(kPseudoTargetLabel); 211 branch_over->target = target; 212} 213 214/* 215 * Array data table format: 216 * ushort ident = 0x0300 magic value 217 * ushort width width of each element in the table 218 * uint size number of elements in the table 219 * ubyte data[size*width] table of data values (may contain a single-byte 220 * padding at the end) 221 * 222 * Total size is 4+(width * size + 1)/2 16-bit code units. 223 */ 224void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { 225 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 226 // Add the table to the list - we'll process it later 227 FillArrayData* tab_rec = 228 reinterpret_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), 229 ArenaAllocator::kAllocData)); 230 tab_rec->table = table; 231 tab_rec->vaddr = current_dalvik_offset_; 232 uint16_t width = tab_rec->table[1]; 233 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); 234 tab_rec->size = (size * width) + 8; 235 236 fill_array_data_.Insert(tab_rec); 237 238 // Making a call - use explicit registers 239 FlushAllRegs(); /* Everything to home location */ 240 LockCallTemps(); 241 LoadValueDirectFixed(rl_src, rMIPS_ARG0); 242 243 // Must prevent code motion for the curr pc pair 244 GenBarrier(); 245 NewLIR0(kMipsCurrPC); // Really a jal to .+8 246 // Now, fill the branch delay slot with the helper load 247 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData)); 248 GenBarrier(); // Scheduling barrier 249 250 // Construct BaseLabel and set up table base register 251 LIR* base_label = NewLIR0(kPseudoTargetLabel); 252 253 // Materialize a pointer to the fill data image 254 NewLIR4(kMipsDelta, rMIPS_ARG1, 0, WrapPointer(base_label), WrapPointer(tab_rec)); 255 256 // And go... 257 ClobberCallerSave(); 258 LIR* call_inst = OpReg(kOpBlx, r_tgt); // ( array*, fill_data* ) 259 MarkSafepointPC(call_inst); 260} 261 262void MipsMir2Lir::GenMoveException(RegLocation rl_dest) { 263 int ex_offset = Thread::ExceptionOffset().Int32Value(); 264 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 265 int reset_reg = AllocTemp(); 266 LoadWordDisp(rMIPS_SELF, ex_offset, rl_result.low_reg); 267 LoadConstant(reset_reg, 0); 268 StoreWordDisp(rMIPS_SELF, ex_offset, reset_reg); 269 FreeTemp(reset_reg); 270 StoreValue(rl_dest, rl_result); 271} 272 273/* 274 * Mark garbage collection card. Skip if the value we're storing is null. 275 */ 276void MipsMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) { 277 int reg_card_base = AllocTemp(); 278 int reg_card_no = AllocTemp(); 279 LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); 280 LoadWordDisp(rMIPS_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base); 281 OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); 282 StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, 283 kUnsignedByte); 284 LIR* target = NewLIR0(kPseudoTargetLabel); 285 branch_over->target = target; 286 FreeTemp(reg_card_base); 287 FreeTemp(reg_card_no); 288} 289 290void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 291 int spill_count = num_core_spills_ + num_fp_spills_; 292 /* 293 * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register 294 * allocation mechanism know so it doesn't try to use any of them when 295 * expanding the frame or flushing. This leaves the utility 296 * code with a single temp: r12. This should be enough. 297 */ 298 LockTemp(rMIPS_ARG0); 299 LockTemp(rMIPS_ARG1); 300 LockTemp(rMIPS_ARG2); 301 LockTemp(rMIPS_ARG3); 302 303 /* 304 * We can safely skip the stack overflow check if we're 305 * a leaf *and* our frame size < fudge factor. 306 */ 307 bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && 308 (static_cast<size_t>(frame_size_) < Thread::kStackOverflowReservedBytes)); 309 NewLIR0(kPseudoMethodEntry); 310 int check_reg = AllocTemp(); 311 int new_sp = AllocTemp(); 312 if (!skip_overflow_check) { 313 /* Load stack limit */ 314 LoadWordDisp(rMIPS_SELF, Thread::StackEndOffset().Int32Value(), check_reg); 315 } 316 /* Spill core callee saves */ 317 SpillCoreRegs(); 318 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */ 319 DCHECK_EQ(num_fp_spills_, 0); 320 if (!skip_overflow_check) { 321 OpRegRegImm(kOpSub, new_sp, rMIPS_SP, frame_size_ - (spill_count * 4)); 322 GenRegRegCheck(kCondUlt, new_sp, check_reg, kThrowStackOverflow); 323 OpRegCopy(rMIPS_SP, new_sp); // Establish stack 324 } else { 325 OpRegImm(kOpSub, rMIPS_SP, frame_size_ - (spill_count * 4)); 326 } 327 328 FlushIns(ArgLocs, rl_method); 329 330 FreeTemp(rMIPS_ARG0); 331 FreeTemp(rMIPS_ARG1); 332 FreeTemp(rMIPS_ARG2); 333 FreeTemp(rMIPS_ARG3); 334} 335 336void MipsMir2Lir::GenExitSequence() { 337 /* 338 * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't 339 * allocated by the register utilities as temps. 340 */ 341 LockTemp(rMIPS_RET0); 342 LockTemp(rMIPS_RET1); 343 344 NewLIR0(kPseudoMethodExit); 345 UnSpillCoreRegs(); 346 OpReg(kOpBx, r_RA); 347} 348 349void MipsMir2Lir::GenSpecialExitSequence() { 350 OpReg(kOpBx, r_RA); 351} 352 353} // namespace art 354