codegen_mips.h revision 5aa6e04061ced68cca8111af1e9c19781b8a9c5d 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir FINAL : public Mir2Lir {
26  public:
27    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen utilities.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE;
35    RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE;
36    LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest,
37                              OpSize size) OVERRIDE;
38    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
39                      OpSize size) OVERRIDE;
40    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
41                         OpSize size) OVERRIDE;
42    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
43                             RegStorage r_dest, OpSize size) OVERRIDE;
44    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
45    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
46    LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src,
47                               OpSize size) OVERRIDE;
48    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
49                       OpSize size) OVERRIDE;
50    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
51                          OpSize size) OVERRIDE;
52    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
53                              RegStorage r_src, OpSize size) OVERRIDE;
54    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
55
56    // Required for target - register utilities.
57    RegStorage TargetReg(SpecialTargetRegister reg);
58    RegStorage GetArgMappingToPhysicalReg(int arg_num);
59    RegLocation GetReturnAlt();
60    RegLocation GetReturnWideAlt();
61    RegLocation LocCReturn();
62    RegLocation LocCReturnRef();
63    RegLocation LocCReturnDouble();
64    RegLocation LocCReturnFloat();
65    RegLocation LocCReturnWide();
66    ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE;
67    void AdjustSpillMask();
68    void ClobberCallerSave();
69    void FreeCallTemps();
70    void LockCallTemps();
71    void MarkPreservedSingle(int v_reg, RegStorage reg);
72    void MarkPreservedDouble(int v_reg, RegStorage reg);
73    void CompilerInitializeRegAlloc();
74
75    // Required for target - miscellaneous.
76    void AssembleLIR();
77    int AssignInsnOffsets();
78    void AssignOffsets();
79    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
80    void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
81    void SetupTargetResourceMasks(LIR* lir, uint64_t flags,
82                                  ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE;
83    const char* GetTargetInstFmt(int opcode);
84    const char* GetTargetInstName(int opcode);
85    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
86    ResourceMask GetPCUseDefEncoding() const OVERRIDE;
87    uint64_t GetTargetInstFlags(int opcode);
88    size_t GetInsnSize(LIR* lir) OVERRIDE;
89    bool IsUnconditionalBranch(LIR* lir);
90
91    // Check support for volatile load/store of a given size.
92    bool SupportsVolatileLoadStore(OpSize size) OVERRIDE;
93    // Get the register class for load/store of a field.
94    RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE;
95
96    // Required for target - Dalvik-level generators.
97    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
98                           RegLocation rl_src1, RegLocation rl_src2);
99    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
100                     RegLocation rl_index, RegLocation rl_dest, int scale);
101    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
102                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
103    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
104                           RegLocation rl_shift);
105    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
106                    RegLocation rl_src2);
107    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
108                    RegLocation rl_src2);
109    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
110                    RegLocation rl_src2);
111    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
112                          RegLocation rl_src2);
113    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
114                         RegLocation rl_src2);
115    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
116                  RegLocation rl_src2);
117    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
118    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
119    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
120    bool GenInlinedSqrt(CallInfo* info);
121    bool GenInlinedPeek(CallInfo* info, OpSize size);
122    bool GenInlinedPoke(CallInfo* info, OpSize size);
123    void GenNotLong(RegLocation rl_dest, RegLocation rl_src);
124    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
125    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
126                   RegLocation rl_src2);
127    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
128                    RegLocation rl_src2);
129    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
130                    RegLocation rl_src2);
131    void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1,
132                       RegLocation rl_src2, bool is_div);
133    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
134    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
135    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
136    void GenDivZeroCheckWide(RegStorage reg);
137    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
138    void GenExitSequence();
139    void GenSpecialExitSequence();
140    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
141    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
142    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
143    void GenSelect(BasicBlock* bb, MIR* mir);
144    bool GenMemBarrier(MemBarrierKind barrier_kind);
145    void GenMoveException(RegLocation rl_dest);
146    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
147                                       int first_bit, int second_bit);
148    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
149    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
150    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
151    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
152    bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
153
154    // Required for target - single operation generators.
155    LIR* OpUnconditionalBranch(LIR* target);
156    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
157    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
158    LIR* OpCondBranch(ConditionCode cc, LIR* target);
159    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
160    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
161    LIR* OpIT(ConditionCode cond, const char* guide);
162    void OpEndIT(LIR* it);
163    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
164    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
165    LIR* OpReg(OpKind op, RegStorage r_dest_src);
166    void OpRegCopy(RegStorage r_dest, RegStorage r_src);
167    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
168    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
169    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
170    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
171    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
172    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
173    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
174    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
175    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
176    LIR* OpTestSuspend(LIR* target);
177    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE;
178    LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE;
179    LIR* OpVldm(RegStorage r_base, int count);
180    LIR* OpVstm(RegStorage r_base, int count);
181    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
182    void OpRegCopyWide(RegStorage dest, RegStorage src);
183    void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE;
184    void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE;
185
186    // TODO: collapse r_dest.
187    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
188                          RegStorage r_dest_hi, OpSize size);
189    // TODO: collapse r_src.
190    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
191                           RegStorage r_src_hi, OpSize size);
192    void SpillCoreRegs();
193    void UnSpillCoreRegs();
194    static const MipsEncodingMap EncodingMap[kMipsLast];
195    bool InexpensiveConstantInt(int32_t value);
196    bool InexpensiveConstantFloat(int32_t value);
197    bool InexpensiveConstantLong(int64_t value);
198    bool InexpensiveConstantDouble(int64_t value);
199
200  private:
201    void ConvertShortToLongBranch(LIR* lir);
202    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
203                          RegLocation rl_src2, bool is_div, bool check_zero);
204    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
205};
206
207}  // namespace art
208
209#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
210