codegen_mips.h revision e643a179cf5585ba6bafdd4fa51730d9f50c06f6 
1/*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
18#define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
19
20#include "dex/compiler_internals.h"
21#include "mips_lir.h"
22
23namespace art {
24
25class MipsMir2Lir FINAL : public Mir2Lir {
26  public:
27    MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
28
29    // Required for target - codegen utilities.
30    bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
31                            RegLocation rl_dest, int lit);
32    bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE;
33    LIR* CheckSuspendUsingLoad() OVERRIDE;
34    RegStorage LoadHelper(ThreadOffset<4> offset);
35    LIR* LoadBaseDisp(int r_base, int displacement, int r_dest, OpSize size, int s_reg);
36    LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
37                      int s_reg);
38    LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg);
39    LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
40                         OpSize size);
41    LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
42                             RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg);
43    LIR* LoadConstantNoClobber(RegStorage r_dest, int value);
44    LIR* LoadConstantWide(RegStorage r_dest, int64_t value);
45    LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
46    LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src);
47    LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
48                          OpSize size);
49    LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
50                              RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg);
51    void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg);
52
53    // Required for target - register utilities.
54    bool IsFpReg(int reg);
55    bool IsFpReg(RegStorage reg);
56    bool SameRegType(int reg1, int reg2);
57    RegStorage AllocTypedTemp(bool fp_hint, int reg_class);
58    RegStorage AllocTypedTempWide(bool fp_hint, int reg_class);
59    int S2d(int low_reg, int high_reg);
60    RegStorage TargetReg(SpecialTargetRegister reg);
61    RegStorage GetArgMappingToPhysicalReg(int arg_num);
62    RegLocation GetReturnAlt();
63    RegLocation GetReturnWideAlt();
64    RegLocation LocCReturn();
65    RegLocation LocCReturnDouble();
66    RegLocation LocCReturnFloat();
67    RegLocation LocCReturnWide();
68    uint32_t FpRegMask();
69    uint64_t GetRegMaskCommon(int reg);
70    void AdjustSpillMask();
71    void ClobberCallerSave();
72    void FlushReg(RegStorage reg);
73    void FlushRegWide(RegStorage reg);
74    void FreeCallTemps();
75    void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free);
76    void LockCallTemps();
77    void MarkPreservedSingle(int v_reg, int reg);
78    void CompilerInitializeRegAlloc();
79
80    // Required for target - miscellaneous.
81    void AssembleLIR();
82    int AssignInsnOffsets();
83    void AssignOffsets();
84    AssemblerStatus AssembleInstructions(CodeOffset start_addr);
85    void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
86    void SetupTargetResourceMasks(LIR* lir, uint64_t flags);
87    const char* GetTargetInstFmt(int opcode);
88    const char* GetTargetInstName(int opcode);
89    std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr);
90    uint64_t GetPCUseDefEncoding();
91    uint64_t GetTargetInstFlags(int opcode);
92    int GetInsnSize(LIR* lir);
93    bool IsUnconditionalBranch(LIR* lir);
94
95    // Required for target - Dalvik-level generators.
96    void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
97                           RegLocation rl_src1, RegLocation rl_src2);
98    void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
99                     RegLocation rl_index, RegLocation rl_dest, int scale);
100    void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
101                     RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark);
102    void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
103                           RegLocation rl_shift);
104    void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
105                    RegLocation rl_src2);
106    void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
107                    RegLocation rl_src2);
108    void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
109                    RegLocation rl_src2);
110    void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
111                          RegLocation rl_src2);
112    void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
113                         RegLocation rl_src2);
114    void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
115                  RegLocation rl_src2);
116    void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
117    bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object);
118    bool GenInlinedMinMaxInt(CallInfo* info, bool is_min);
119    bool GenInlinedSqrt(CallInfo* info);
120    bool GenInlinedPeek(CallInfo* info, OpSize size);
121    bool GenInlinedPoke(CallInfo* info, OpSize size);
122    void GenNegLong(RegLocation rl_dest, RegLocation rl_src);
123    void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
124                   RegLocation rl_src2);
125    void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
126                    RegLocation rl_src2);
127    void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
128                    RegLocation rl_src2);
129    LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset,
130                        ThrowKind kind);
131    RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div);
132    RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div);
133    void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
134    void GenDivZeroCheckWide(RegStorage reg);
135    void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method);
136    void GenExitSequence();
137    void GenSpecialExitSequence();
138    void GenFillArrayData(uint32_t table_offset, RegLocation rl_src);
139    void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
140    void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
141    void GenSelect(BasicBlock* bb, MIR* mir);
142    void GenMemBarrier(MemBarrierKind barrier_kind);
143    void GenMoveException(RegLocation rl_dest);
144    void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit,
145                                       int first_bit, int second_bit);
146    void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
147    void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
148    void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
149    void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
150    bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special);
151
152    // Required for target - single operation generators.
153    LIR* OpUnconditionalBranch(LIR* target);
154    LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
155    LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
156    LIR* OpCondBranch(ConditionCode cc, LIR* target);
157    LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
158    LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src);
159    LIR* OpIT(ConditionCode cond, const char* guide);
160    void OpEndIT(LIR* it);
161    LIR* OpMem(OpKind op, RegStorage r_base, int disp);
162    LIR* OpPcRelLoad(RegStorage reg, LIR* target);
163    LIR* OpReg(OpKind op, RegStorage r_dest_src);
164    LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src);
165    LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src);
166    LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
167    LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset);
168    LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
169    LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
170    LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
171    LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
172    LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
173    LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
174    LIR* OpTestSuspend(LIR* target);
175    LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset);
176    LIR* OpVldm(RegStorage r_base, int count);
177    LIR* OpVstm(RegStorage r_base, int count);
178    void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset);
179    void OpRegCopyWide(RegStorage dest, RegStorage src);
180    void OpTlsCmp(ThreadOffset<4> offset, int val);
181
182    // TODO: collapse r_dest.
183    LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
184                          RegStorage r_dest_hi, OpSize size, int s_reg);
185    // TODO: collapse r_src.
186    LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
187                           RegStorage r_src_hi, OpSize size);
188    void SpillCoreRegs();
189    void UnSpillCoreRegs();
190    static const MipsEncodingMap EncodingMap[kMipsLast];
191    bool InexpensiveConstantInt(int32_t value);
192    bool InexpensiveConstantFloat(int32_t value);
193    bool InexpensiveConstantLong(int64_t value);
194    bool InexpensiveConstantDouble(int64_t value);
195
196  private:
197    void ConvertShortToLongBranch(LIR* lir);
198    RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1,
199                          RegLocation rl_src2, bool is_div, bool check_zero);
200    RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
201};
202
203}  // namespace art
204
205#endif  // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_
206