mir_to_lir.h revision 30adc7383a74eb3cb6db3bf42cea3a5595055ce1
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF012 (REG_DEF0 | REG_DEF1 | REG_DEF2) 95#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 96#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 97#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 98#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 99#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 100#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 101#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 102#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 103#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 104#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 105#define REG_USE012 (REG_USE01 | REG_USE2) 106#define REG_USE014 (REG_USE01 | REG_USE4) 107#define REG_USE01 (REG_USE0 | REG_USE1) 108#define REG_USE02 (REG_USE0 | REG_USE2) 109#define REG_USE12 (REG_USE1 | REG_USE2) 110#define REG_USE23 (REG_USE2 | REG_USE3) 111#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 112 113// TODO: #includes need a cleanup 114#ifndef INVALID_SREG 115#define INVALID_SREG (-1) 116#endif 117 118struct BasicBlock; 119struct CallInfo; 120struct CompilationUnit; 121struct InlineMethod; 122struct MIR; 123struct LIR; 124struct RegLocation; 125struct RegisterInfo; 126class DexFileMethodInliner; 127class MIRGraph; 128class Mir2Lir; 129 130typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 131 const MethodReference& target_method, 132 uint32_t method_idx, uintptr_t direct_code, 133 uintptr_t direct_method, InvokeType type); 134 135typedef std::vector<uint8_t> CodeBuffer; 136 137struct UseDefMasks { 138 uint64_t use_mask; // Resource mask for use. 139 uint64_t def_mask; // Resource mask for def. 140}; 141 142struct AssemblyInfo { 143 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 144}; 145 146struct LIR { 147 CodeOffset offset; // Offset of this instruction. 148 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 149 int16_t opcode; 150 LIR* next; 151 LIR* prev; 152 LIR* target; 153 struct { 154 unsigned int alias_info:17; // For Dalvik register disambiguation. 155 bool is_nop:1; // LIR is optimized away. 156 unsigned int size:4; // Note: size of encoded instruction is in bytes. 157 bool use_def_invalid:1; // If true, masks should not be used. 158 unsigned int generation:1; // Used to track visitation state during fixup pass. 159 unsigned int fixup:8; // Fixup kind. 160 } flags; 161 union { 162 UseDefMasks m; // Use & Def masks used during optimization. 163 AssemblyInfo a; // Instruction info used during assembly phase. 164 } u; 165 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 166}; 167 168// Target-specific initialization. 169Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 170 ArenaAllocator* const arena); 171Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 172 ArenaAllocator* const arena); 173Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 174 ArenaAllocator* const arena); 175Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 176 ArenaAllocator* const arena); 177 178// Utility macros to traverse the LIR list. 179#define NEXT_LIR(lir) (lir->next) 180#define PREV_LIR(lir) (lir->prev) 181 182// Defines for alias_info (tracks Dalvik register references). 183#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 184#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 185#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 186#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 187 188// Common resource macros. 189#define ENCODE_CCODE (1ULL << kCCode) 190#define ENCODE_FP_STATUS (1ULL << kFPStatus) 191 192// Abstract memory locations. 193#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 194#define ENCODE_LITERAL (1ULL << kLiteral) 195#define ENCODE_HEAP_REF (1ULL << kHeapRef) 196#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 197 198#define ENCODE_ALL (~0ULL) 199#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 200 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 201 202#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 203#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 204 do { \ 205 low_reg = both_regs & 0xff; \ 206 high_reg = (both_regs >> 8) & 0xff; \ 207 } while (false) 208 209// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 210#define STARTING_DOUBLE_SREG 0x10000 211 212// TODO: replace these macros 213#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 214#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 215#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 216#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 217#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 218 219class Mir2Lir : public Backend { 220 public: 221 /* 222 * Auxiliary information describing the location of data embedded in the Dalvik 223 * byte code stream. 224 */ 225 struct EmbeddedData { 226 CodeOffset offset; // Code offset of data block. 227 const uint16_t* table; // Original dex data. 228 DexOffset vaddr; // Dalvik offset of parent opcode. 229 }; 230 231 struct FillArrayData : EmbeddedData { 232 int32_t size; 233 }; 234 235 struct SwitchTable : EmbeddedData { 236 LIR* anchor; // Reference instruction for relative offsets. 237 LIR** targets; // Array of case targets. 238 }; 239 240 /* Static register use counts */ 241 struct RefCounts { 242 int count; 243 int s_reg; 244 }; 245 246 /* 247 * Data structure tracking the mapping detween a Dalvik value (32 or 64 bits) 248 * and native register storage. The primary purpose is to reuse previuosly 249 * loaded values, if possible, and otherwise to keep the value in register 250 * storage as long as possible. 251 * 252 * NOTE 1: wide_value refers to the width of the Dalvik value contained in 253 * this register (or pair). For example, a 64-bit register containing a 32-bit 254 * Dalvik value would have wide_value==false even though the storage container itself 255 * is wide. Similarly, a 32-bit register containing half of a 64-bit Dalvik value 256 * would have wide_value==true (and additionally would have its partner field set to the 257 * other half whose wide_value field would also be true. 258 * 259 * NOTE 2: In the case of a register pair, you can determine which of the partners 260 * is the low half by looking at the s_reg names. The high s_reg will equal low_sreg + 1. 261 * 262 * NOTE 3: In the case of a 64-bit register holding a Dalvik wide value, wide_value 263 * will be true and partner==self. s_reg refers to the low-order word of the Dalvik 264 * value, and the s_reg of the high word is implied (s_reg + 1). 265 * 266 * NOTE 4: The reg and is_temp fields should always be correct. If is_temp is false no 267 * other fields have meaning. [perhaps not true, wide should work for promoted regs?] 268 * If is_temp==true and live==false, no other fields have 269 * meaning. If is_temp==true and live==true, wide_value, partner, dirty, s_reg, def_start 270 * and def_end describe the relationship between the temp register/register pair and 271 * the Dalvik value[s] described by s_reg/s_reg+1. 272 * 273 * The fields used_storage, master_storage and storage_mask are used to track allocation 274 * in light of potential aliasing. For example, consider Arm's d2, which overlaps s4 & s5. 275 * d2's storage mask would be 0x00000003, the two low-order bits denoting 64 bits of 276 * storage use. For s4, it would be 0x0000001; for s5 0x00000002. These values should not 277 * change once initialized. The "used_storage" field tracks current allocation status. 278 * Although each record contains this field, only the field from the largest member of 279 * an aliased group is used. In our case, it would be d2's. The master_storage pointer 280 * of d2, s4 and s5 would all point to d2's used_storage field. Each bit in a used_storage 281 * represents 32 bits of storage. d2's used_storage would be initialized to 0xfffffffc. 282 * Then, if we wanted to determine whether s4 could be allocated, we would "and" 283 * s4's storage_mask with s4's *master_storage. If the result is zero, s4 is free and 284 * to allocate: *master_storage |= storage_mask. To free, *master_storage &= ~storage_mask. 285 * 286 * For an X86 vector register example, storage_mask would be: 287 * 0x00000001 for 32-bit view of xmm1 288 * 0x00000003 for 64-bit view of xmm1 289 * 0x0000000f for 128-bit view of xmm1 290 * 0x000000ff for 256-bit view of ymm1 // future expansion, if needed 291 * 0x0000ffff for 512-bit view of ymm1 // future expansion, if needed 292 * 0xffffffff for 1024-bit view of ymm1 // future expansion, if needed 293 * 294 * The "liveness" of a register is handled in a similar way. The liveness_ storage is 295 * held in the widest member of an aliased set. Note, though, that for a temp register to 296 * reused as live, it must both be marked live and the associated SReg() must match the 297 * desired s_reg. This gets a little complicated when dealing with aliased registers. All 298 * members of an aliased set will share the same liveness flags, but each will individually 299 * maintain s_reg_. In this way we can know that at least one member of an 300 * aliased set is live, but will only fully match on the appropriate alias view. For example, 301 * if Arm d1 is live as a double and has s_reg_ set to Dalvik v8 (which also implies v9 302 * because it is wide), its aliases s2 and s3 will show as live, but will have 303 * s_reg_ == INVALID_SREG. An attempt to later AllocLiveReg() of v9 with a single-precision 304 * view will fail because although s3's liveness bit is set, its s_reg_ will not match v9. 305 * This will cause all members of the aliased set to be clobbered and AllocLiveReg() will 306 * report that v9 is currently not live as a single (which is what we want). 307 * 308 * NOTE: the x86 usage is still somewhat in flux. There are competing notions of how 309 * to treat xmm registers: 310 * 1. Treat them all as 128-bits wide, but denote how much data used via bytes field. 311 * o This more closely matches reality, but means you'd need to be able to get 312 * to the associated RegisterInfo struct to figure out how it's being used. 313 * o This is how 64-bit core registers will be used - always 64 bits, but the 314 * "bytes" field will be 4 for 32-bit usage and 8 for 64-bit usage. 315 * 2. View the xmm registers based on contents. 316 * o A single in a xmm2 register would be k32BitVector, while a double in xmm2 would 317 * be a k64BitVector. 318 * o Note that the two uses above would be considered distinct registers (but with 319 * the aliasing mechanism, we could detect interference). 320 * o This is how aliased double and single float registers will be handled on 321 * Arm and MIPS. 322 * Working plan is, for all targets, to follow mechanism 1 for 64-bit core registers, and 323 * mechanism 2 for aliased float registers and x86 vector registers. 324 */ 325 class RegisterInfo { 326 public: 327 RegisterInfo(RegStorage r, uint64_t mask = ENCODE_ALL); 328 ~RegisterInfo() {} 329 static void* operator new(size_t size, ArenaAllocator* arena) { 330 return arena->Alloc(size, kArenaAllocRegAlloc); 331 } 332 333 bool InUse() { return (storage_mask_ & master_->used_storage_) != 0; } 334 void MarkInUse() { master_->used_storage_ |= storage_mask_; } 335 void MarkFree() { master_->used_storage_ &= ~storage_mask_; } 336 bool IsLive() { return (master_->liveness_ & storage_mask_) == storage_mask_; } 337 void MarkLive() { master_->liveness_ |= storage_mask_; } 338 void MarkDead() { 339 master_->liveness_ &= ~storage_mask_; 340 SetSReg(INVALID_SREG); 341 } 342 RegStorage GetReg() { return reg_; } 343 void SetReg(RegStorage reg) { reg_ = reg; } 344 bool IsTemp() { return is_temp_; } 345 void SetIsTemp(bool val) { is_temp_ = val; } 346 bool IsWide() { return wide_value_; } 347 void SetIsWide(bool val) { wide_value_ = val; } 348 bool IsDirty() { return dirty_; } 349 void SetIsDirty(bool val) { dirty_ = val; } 350 RegStorage Partner() { return partner_; } 351 void SetPartner(RegStorage partner) { partner_ = partner; } 352 int SReg() { return s_reg_; } 353 void SetSReg(int s_reg) { s_reg_ = s_reg; } 354 uint64_t DefUseMask() { return def_use_mask_; } 355 void SetDefUseMask(uint64_t def_use_mask) { def_use_mask_ = def_use_mask; } 356 RegisterInfo* Master() { return master_; } 357 void SetMaster(RegisterInfo* master) { 358 master_ = master; 359 if (master != this) { 360 master_->aliased_ = true; 361 } 362 } 363 bool IsAliased() { return aliased_; } 364 uint32_t StorageMask() { return storage_mask_; } 365 void SetStorageMask(uint32_t storage_mask) { storage_mask_ = storage_mask; } 366 LIR* DefStart() { return def_start_; } 367 void SetDefStart(LIR* def_start) { def_start_ = def_start; } 368 LIR* DefEnd() { return def_end_; } 369 void SetDefEnd(LIR* def_end) { def_end_ = def_end; } 370 void ResetDefBody() { def_start_ = def_end_ = nullptr; } 371 372 373 private: 374 RegStorage reg_; 375 bool is_temp_; // Can allocate as temp? 376 bool wide_value_; // Holds a Dalvik wide value (either itself, or part of a pair). 377 bool dirty_; // If live, is it dirty? 378 bool aliased_; // Is this the master for other aliased RegisterInfo's? 379 RegStorage partner_; // If wide_value, other reg of pair or self if 64-bit register. 380 int s_reg_; // Name of live value. 381 uint64_t def_use_mask_; // Resources for this element. 382 uint32_t used_storage_; // 1 bit per 4 bytes of storage. Unused by aliases. 383 uint32_t liveness_; // 1 bit per 4 bytes of storage. Unused by aliases. 384 RegisterInfo* master_; // Pointer to controlling storage mask. 385 uint32_t storage_mask_; // Track allocation of sub-units. 386 LIR *def_start_; // Starting inst in last def sequence. 387 LIR *def_end_; // Ending inst in last def sequence. 388 }; 389 390 class RegisterPool { 391 public: 392 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, const std::vector<RegStorage>& core_regs, 393 const std::vector<RegStorage>& sp_regs, const std::vector<RegStorage>& dp_regs, 394 const std::vector<RegStorage>& reserved_regs, 395 const std::vector<RegStorage>& core_temps, 396 const std::vector<RegStorage>& sp_temps, 397 const std::vector<RegStorage>& dp_temps); 398 ~RegisterPool() {} 399 static void* operator new(size_t size, ArenaAllocator* arena) { 400 return arena->Alloc(size, kArenaAllocRegAlloc); 401 } 402 void ResetNextTemp() { 403 next_core_reg_ = 0; 404 next_sp_reg_ = 0; 405 next_dp_reg_ = 0; 406 } 407 GrowableArray<RegisterInfo*> core_regs_; 408 int next_core_reg_; 409 GrowableArray<RegisterInfo*> sp_regs_; // Single precision float. 410 int next_sp_reg_; 411 GrowableArray<RegisterInfo*> dp_regs_; // Double precision float. 412 int next_dp_reg_; 413 414 private: 415 Mir2Lir* const m2l_; 416 }; 417 418 struct PromotionMap { 419 RegLocationType core_location:3; 420 uint8_t core_reg; 421 RegLocationType fp_location:3; 422 uint8_t FpReg; 423 bool first_in_pair; 424 }; 425 426 // 427 // Slow paths. This object is used generate a sequence of code that is executed in the 428 // slow path. For example, resolving a string or class is slow as it will only be executed 429 // once (after that it is resolved and doesn't need to be done again). We want slow paths 430 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 431 // branch over them. 432 // 433 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 434 // the Compile() function that will be called near the end of the code generated by the 435 // method. 436 // 437 // The basic flow for a slow path is: 438 // 439 // CMP reg, #value 440 // BEQ fromfast 441 // cont: 442 // ... 443 // fast path code 444 // ... 445 // more code 446 // ... 447 // RETURN 448 /// 449 // fromfast: 450 // ... 451 // slow path code 452 // ... 453 // B cont 454 // 455 // So you see we need two labels and two branches. The first branch (called fromfast) is 456 // the conditional branch to the slow path code. The second label (called cont) is used 457 // as an unconditional branch target for getting back to the code after the slow path 458 // has completed. 459 // 460 461 class LIRSlowPath { 462 public: 463 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 464 LIR* cont = nullptr) : 465 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 466 } 467 virtual ~LIRSlowPath() {} 468 virtual void Compile() = 0; 469 470 static void* operator new(size_t size, ArenaAllocator* arena) { 471 return arena->Alloc(size, kArenaAllocData); 472 } 473 474 protected: 475 LIR* GenerateTargetLabel(int opcode = kPseudoTargetLabel); 476 477 Mir2Lir* const m2l_; 478 const DexOffset current_dex_pc_; 479 LIR* const fromfast_; 480 LIR* const cont_; 481 }; 482 483 virtual ~Mir2Lir() {} 484 485 int32_t s4FromSwitchData(const void* switch_data) { 486 return *reinterpret_cast<const int32_t*>(switch_data); 487 } 488 489 /* 490 * TODO: this is a trace JIT vestige, and its use should be reconsidered. At the time 491 * it was introduced, it was intended to be a quick best guess of type without having to 492 * take the time to do type analysis. Currently, though, we have a much better idea of 493 * the types of Dalvik virtual registers. Instead of using this for a best guess, why not 494 * just use our knowledge of type to select the most appropriate register class? 495 */ 496 RegisterClass RegClassBySize(OpSize size) { 497 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 498 size == kSignedByte) ? kCoreReg : kAnyReg; 499 } 500 501 size_t CodeBufferSizeInBytes() { 502 return code_buffer_.size() / sizeof(code_buffer_[0]); 503 } 504 505 static bool IsPseudoLirOp(int opcode) { 506 return (opcode < 0); 507 } 508 509 /* 510 * LIR operands are 32-bit integers. Sometimes, (especially for managing 511 * instructions which require PC-relative fixups), we need the operands to carry 512 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 513 * hold that index in the operand array. 514 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 515 * may be worth conditionally-compiling a set of identity functions here. 516 */ 517 uint32_t WrapPointer(void* pointer) { 518 uint32_t res = pointer_storage_.Size(); 519 pointer_storage_.Insert(pointer); 520 return res; 521 } 522 523 void* UnwrapPointer(size_t index) { 524 return pointer_storage_.Get(index); 525 } 526 527 // strdup(), but allocates from the arena. 528 char* ArenaStrdup(const char* str) { 529 size_t len = strlen(str) + 1; 530 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 531 if (res != NULL) { 532 strncpy(res, str, len); 533 } 534 return res; 535 } 536 537 // Shared by all targets - implemented in codegen_util.cc 538 void AppendLIR(LIR* lir); 539 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 540 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 541 542 /** 543 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 544 * to place in a frame. 545 * @return Returns the maximum number of compiler temporaries. 546 */ 547 size_t GetMaxPossibleCompilerTemps() const; 548 549 /** 550 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 551 * @return Returns the size in bytes for space needed for compiler temporary spill region. 552 */ 553 size_t GetNumBytesForCompilerTempSpillRegion(); 554 555 DexOffset GetCurrentDexPc() const { 556 return current_dalvik_offset_; 557 } 558 559 int ComputeFrameSize(); 560 virtual void Materialize(); 561 virtual CompiledMethod* GetCompiledMethod(); 562 void MarkSafepointPC(LIR* inst); 563 void SetupResourceMasks(LIR* lir); 564 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 565 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 566 void SetupRegMask(uint64_t* mask, int reg); 567 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 568 void DumpPromotionMap(); 569 void CodegenDump(); 570 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 571 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 572 LIR* NewLIR0(int opcode); 573 LIR* NewLIR1(int opcode, int dest); 574 LIR* NewLIR2(int opcode, int dest, int src1); 575 LIR* NewLIR2NoDest(int opcode, int src, int info); 576 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 577 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 578 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 579 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 580 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 581 LIR* AddWordData(LIR* *constant_list_p, int value); 582 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 583 void ProcessSwitchTables(); 584 void DumpSparseSwitchTable(const uint16_t* table); 585 void DumpPackedSwitchTable(const uint16_t* table); 586 void MarkBoundary(DexOffset offset, const char* inst_str); 587 void NopLIR(LIR* lir); 588 void UnlinkLIR(LIR* lir); 589 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 590 bool IsInexpensiveConstant(RegLocation rl_src); 591 ConditionCode FlipComparisonOrder(ConditionCode before); 592 ConditionCode NegateComparison(ConditionCode before); 593 virtual void InstallLiteralPools(); 594 void InstallSwitchTables(); 595 void InstallFillArrayData(); 596 bool VerifyCatchEntries(); 597 void CreateMappingTables(); 598 void CreateNativeGcMap(); 599 int AssignLiteralOffset(CodeOffset offset); 600 int AssignSwitchTablesOffset(CodeOffset offset); 601 int AssignFillArrayDataOffset(CodeOffset offset); 602 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 603 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 604 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 605 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 606 RegLocation NarrowRegLoc(RegLocation loc); 607 608 // Shared by all targets - implemented in local_optimizations.cc 609 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 610 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 611 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 612 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 613 614 // Shared by all targets - implemented in ralloc_util.cc 615 int GetSRegHi(int lowSreg); 616 bool LiveOut(int s_reg); 617 void SimpleRegAlloc(); 618 void ResetRegPool(); 619 void CompilerInitPool(RegisterInfo* info, RegStorage* regs, int num); 620 void DumpRegPool(GrowableArray<RegisterInfo*>* regs); 621 void DumpCoreRegPool(); 622 void DumpFpRegPool(); 623 void DumpRegPools(); 624 /* Mark a temp register as dead. Does not affect allocation state. */ 625 void Clobber(RegStorage reg); 626 void ClobberSReg(int s_reg); 627 void ClobberAliases(RegisterInfo* info); 628 int SRegToPMap(int s_reg); 629 void RecordCorePromotion(RegStorage reg, int s_reg); 630 RegStorage AllocPreservedCoreReg(int s_reg); 631 void RecordSinglePromotion(RegStorage reg, int s_reg); 632 void RecordDoublePromotion(RegStorage reg, int s_reg); 633 RegStorage AllocPreservedSingle(int s_reg); 634 virtual RegStorage AllocPreservedDouble(int s_reg); 635 RegStorage AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required); 636 RegStorage AllocFreeTemp(); 637 RegStorage AllocTemp(); 638 RegStorage AllocTempSingle(); 639 RegStorage AllocTempDouble(); 640 void FlushReg(RegStorage reg); 641 void FlushRegWide(RegStorage reg); 642 RegStorage AllocLiveReg(int s_reg, int reg_class, bool wide); 643 RegStorage FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg); 644 void FreeTemp(RegStorage reg); 645 bool IsLive(RegStorage reg); 646 bool IsTemp(RegStorage reg); 647 bool IsPromoted(RegStorage reg); 648 bool IsDirty(RegStorage reg); 649 void LockTemp(RegStorage reg); 650 void ResetDef(RegStorage reg); 651 void NullifyRange(RegStorage reg, int s_reg); 652 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 653 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 654 RegLocation WideToNarrow(RegLocation rl); 655 void ResetDefLoc(RegLocation rl); 656 void ResetDefLocWide(RegLocation rl); 657 void ResetDefTracking(); 658 void ClobberAllRegs(); 659 void FlushSpecificReg(RegisterInfo* info); 660 void FlushAllRegs(); 661 bool RegClassMatches(int reg_class, RegStorage reg); 662 void MarkLive(RegLocation loc); 663 void MarkLiveReg(RegStorage reg, int s_reg); 664 void MarkTemp(RegStorage reg); 665 void UnmarkTemp(RegStorage reg); 666 void MarkWide(RegStorage reg); 667 void MarkClean(RegLocation loc); 668 void MarkDirty(RegLocation loc); 669 void MarkInUse(RegStorage reg); 670 bool CheckCorePoolSanity(); 671 RegLocation UpdateLoc(RegLocation loc); 672 RegLocation UpdateLocWide(RegLocation loc); 673 RegLocation UpdateRawLoc(RegLocation loc); 674 675 /** 676 * @brief Used to load register location into a typed temporary or pair of temporaries. 677 * @see EvalLoc 678 * @param loc The register location to load from. 679 * @param reg_class Type of register needed. 680 * @param update Whether the liveness information should be updated. 681 * @return Returns the properly typed temporary in physical register pairs. 682 */ 683 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 684 685 /** 686 * @brief Used to load register location into a typed temporary. 687 * @param loc The register location to load from. 688 * @param reg_class Type of register needed. 689 * @param update Whether the liveness information should be updated. 690 * @return Returns the properly typed temporary in physical register. 691 */ 692 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 693 694 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 695 void DumpCounts(const RefCounts* arr, int size, const char* msg); 696 void DoPromotion(); 697 int VRegOffset(int v_reg); 698 int SRegOffset(int s_reg); 699 RegLocation GetReturnWide(bool is_double); 700 RegLocation GetReturn(bool is_float); 701 RegisterInfo* GetRegInfo(RegStorage reg); 702 703 // Shared by all targets - implemented in gen_common.cc. 704 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 705 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 706 RegLocation rl_src, RegLocation rl_dest, int lit); 707 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 708 void HandleSlowPaths(); 709 void GenBarrier(); 710 void GenDivZeroException(); 711 // c_code holds condition code that's generated from testing divisor against 0. 712 void GenDivZeroCheck(ConditionCode c_code); 713 // reg holds divisor. 714 void GenDivZeroCheck(RegStorage reg); 715 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 716 void GenArrayBoundsCheck(int32_t index, RegStorage length); 717 LIR* GenNullCheck(RegStorage reg); 718 void MarkPossibleNullPointerException(int opt_flags); 719 void MarkPossibleStackOverflowException(); 720 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 721 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 722 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 723 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 724 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 725 RegLocation rl_src2, LIR* taken, LIR* fall_through); 726 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 727 LIR* taken, LIR* fall_through); 728 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 729 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 730 RegLocation rl_src); 731 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 732 RegLocation rl_src); 733 void GenFilledNewArray(CallInfo* info); 734 void GenSput(MIR* mir, RegLocation rl_src, 735 bool is_long_or_double, bool is_object); 736 void GenSget(MIR* mir, RegLocation rl_dest, 737 bool is_long_or_double, bool is_object); 738 void GenIGet(MIR* mir, int opt_flags, OpSize size, 739 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 740 void GenIPut(MIR* mir, int opt_flags, OpSize size, 741 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 742 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 743 RegLocation rl_src); 744 745 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 746 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 747 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 748 void GenThrow(RegLocation rl_src); 749 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 750 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 751 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 752 RegLocation rl_src1, RegLocation rl_src2); 753 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 754 RegLocation rl_src1, RegLocation rl_shift); 755 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 756 RegLocation rl_src, int lit); 757 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 758 RegLocation rl_src1, RegLocation rl_src2); 759 void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest, 760 RegLocation rl_src); 761 void GenSuspendTest(int opt_flags); 762 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 763 764 // This will be overridden by x86 implementation. 765 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 766 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 767 RegLocation rl_src1, RegLocation rl_src2); 768 769 // Shared by all targets - implemented in gen_invoke.cc. 770 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc, 771 bool use_link = true); 772 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 773 void CallRuntimeHelper(ThreadOffset<4> helper_offset, bool safepoint_pc); 774 void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc); 775 void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc); 776 void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0, 777 bool safepoint_pc); 778 void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1, 779 bool safepoint_pc); 780 void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0, 781 RegLocation arg1, bool safepoint_pc); 782 void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0, 783 int arg1, bool safepoint_pc); 784 void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1, 785 bool safepoint_pc); 786 void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1, 787 bool safepoint_pc); 788 void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0, 789 bool safepoint_pc); 790 void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0, 791 bool safepoint_pc); 792 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0, 793 RegLocation arg2, bool safepoint_pc); 794 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset, 795 RegLocation arg0, RegLocation arg1, 796 bool safepoint_pc); 797 void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 798 bool safepoint_pc); 799 void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 800 int arg2, bool safepoint_pc); 801 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0, 802 RegLocation arg2, bool safepoint_pc); 803 void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2, 804 bool safepoint_pc); 805 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset, 806 int arg0, RegLocation arg1, RegLocation arg2, 807 bool safepoint_pc); 808 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset, 809 RegLocation arg0, RegLocation arg1, 810 RegLocation arg2, 811 bool safepoint_pc); 812 void GenInvoke(CallInfo* info); 813 void GenInvokeNoInline(CallInfo* info); 814 virtual void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 815 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 816 NextCallInsn next_call_insn, 817 const MethodReference& target_method, 818 uint32_t vtable_idx, 819 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 820 bool skip_this); 821 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 822 NextCallInsn next_call_insn, 823 const MethodReference& target_method, 824 uint32_t vtable_idx, 825 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 826 bool skip_this); 827 828 /** 829 * @brief Used to determine the register location of destination. 830 * @details This is needed during generation of inline intrinsics because it finds destination 831 * of return, 832 * either the physical register or the target of move-result. 833 * @param info Information about the invoke. 834 * @return Returns the destination location. 835 */ 836 RegLocation InlineTarget(CallInfo* info); 837 838 /** 839 * @brief Used to determine the wide register location of destination. 840 * @see InlineTarget 841 * @param info Information about the invoke. 842 * @return Returns the destination location. 843 */ 844 RegLocation InlineTargetWide(CallInfo* info); 845 846 bool GenInlinedCharAt(CallInfo* info); 847 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 848 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 849 bool GenInlinedAbsInt(CallInfo* info); 850 bool GenInlinedAbsLong(CallInfo* info); 851 bool GenInlinedAbsFloat(CallInfo* info); 852 bool GenInlinedAbsDouble(CallInfo* info); 853 bool GenInlinedFloatCvt(CallInfo* info); 854 bool GenInlinedDoubleCvt(CallInfo* info); 855 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 856 bool GenInlinedStringCompareTo(CallInfo* info); 857 bool GenInlinedCurrentThread(CallInfo* info); 858 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 859 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 860 bool is_volatile, bool is_ordered); 861 virtual int LoadArgRegs(CallInfo* info, int call_state, 862 NextCallInsn next_call_insn, 863 const MethodReference& target_method, 864 uint32_t vtable_idx, 865 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 866 bool skip_this); 867 868 // Shared by all targets - implemented in gen_loadstore.cc. 869 RegLocation LoadCurrMethod(); 870 void LoadCurrMethodDirect(RegStorage r_tgt); 871 LIR* LoadConstant(RegStorage r_dest, int value); 872 // Natural word size. 873 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 874 return LoadBaseDisp(r_base, displacement, r_dest, kWord); 875 } 876 // Load 32 bits, regardless of target. 877 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 878 return LoadBaseDisp(r_base, displacement, r_dest, k32); 879 } 880 // Load a reference at base + displacement and decompress into register. 881 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 882 return LoadBaseDisp(r_base, displacement, r_dest, kReference); 883 } 884 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 885 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 886 // Load Dalvik value with 64-bit memory storage. 887 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 888 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 889 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 890 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 891 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 892 // Load Dalvik value with 64-bit memory storage. 893 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 894 // Load Dalvik value with 64-bit memory storage. 895 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 896 // Store an item of natural word size. 897 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 898 return StoreBaseDisp(r_base, displacement, r_src, kWord); 899 } 900 // Store an uncompressed reference into a compressed 32-bit container. 901 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src) { 902 return StoreBaseDisp(r_base, displacement, r_src, kReference); 903 } 904 // Store 32 bits, regardless of target. 905 LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 906 return StoreBaseDisp(r_base, displacement, r_src, k32); 907 } 908 909 /** 910 * @brief Used to do the final store in the destination as per bytecode semantics. 911 * @param rl_dest The destination dalvik register location. 912 * @param rl_src The source register location. Can be either physical register or dalvik register. 913 */ 914 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 915 916 /** 917 * @brief Used to do the final store in a wide destination as per bytecode semantics. 918 * @see StoreValue 919 * @param rl_dest The destination dalvik register location. 920 * @param rl_src The source register location. Can be either physical register or dalvik 921 * register. 922 */ 923 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 924 925 /** 926 * @brief Used to do the final store to a destination as per bytecode semantics. 927 * @see StoreValue 928 * @param rl_dest The destination dalvik register location. 929 * @param rl_src The source register location. It must be kLocPhysReg 930 * 931 * This is used for x86 two operand computations, where we have computed the correct 932 * register value that now needs to be properly registered. This is used to avoid an 933 * extra register copy that would result if StoreValue was called. 934 */ 935 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 936 937 /** 938 * @brief Used to do the final store in a wide destination as per bytecode semantics. 939 * @see StoreValueWide 940 * @param rl_dest The destination dalvik register location. 941 * @param rl_src The source register location. It must be kLocPhysReg 942 * 943 * This is used for x86 two operand computations, where we have computed the correct 944 * register values that now need to be properly registered. This is used to avoid an 945 * extra pair of register copies that would result if StoreValueWide was called. 946 */ 947 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 948 949 // Shared by all targets - implemented in mir_to_lir.cc. 950 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 951 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 952 bool MethodBlockCodeGen(BasicBlock* bb); 953 bool SpecialMIR2LIR(const InlineMethod& special); 954 void MethodMIR2LIR(); 955 // Update LIR for verbose listings. 956 void UpdateLIROffsets(); 957 958 /* 959 * @brief Load the address of the dex method into the register. 960 * @param target_method The MethodReference of the method to be invoked. 961 * @param type How the method will be invoked. 962 * @param register that will contain the code address. 963 * @note register will be passed to TargetReg to get physical register. 964 */ 965 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 966 SpecialTargetRegister symbolic_reg); 967 968 /* 969 * @brief Load the Method* of a dex method into the register. 970 * @param target_method The MethodReference of the method to be invoked. 971 * @param type How the method will be invoked. 972 * @param register that will contain the code address. 973 * @note register will be passed to TargetReg to get physical register. 974 */ 975 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 976 SpecialTargetRegister symbolic_reg); 977 978 /* 979 * @brief Load the Class* of a Dex Class type into the register. 980 * @param type How the method will be invoked. 981 * @param register that will contain the code address. 982 * @note register will be passed to TargetReg to get physical register. 983 */ 984 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 985 986 // Routines that work for the generic case, but may be overriden by target. 987 /* 988 * @brief Compare memory to immediate, and branch if condition true. 989 * @param cond The condition code that when true will branch to the target. 990 * @param temp_reg A temporary register that can be used if compare to memory is not 991 * supported by the architecture. 992 * @param base_reg The register holding the base address. 993 * @param offset The offset from the base. 994 * @param check_value The immediate to compare to. 995 * @returns The branch instruction that was generated. 996 */ 997 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 998 int offset, int check_value, LIR* target); 999 1000 // Required for target - codegen helpers. 1001 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1002 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1003 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 1004 virtual LIR* CheckSuspendUsingLoad() = 0; 1005 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 1006 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 1007 OpSize size) = 0; 1008 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 1009 int scale, OpSize size) = 0; 1010 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1011 int displacement, RegStorage r_dest, OpSize size) = 0; 1012 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 1013 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 1014 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 1015 OpSize size) = 0; 1016 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 1017 int scale, OpSize size) = 0; 1018 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 1019 int displacement, RegStorage r_src, OpSize size) = 0; 1020 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 1021 1022 // Required for target - register utilities. 1023 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 1024 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 1025 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 1026 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 1027 virtual RegLocation GetReturnAlt() = 0; 1028 virtual RegLocation GetReturnWideAlt() = 0; 1029 virtual RegLocation LocCReturn() = 0; 1030 virtual RegLocation LocCReturnDouble() = 0; 1031 virtual RegLocation LocCReturnFloat() = 0; 1032 virtual RegLocation LocCReturnWide() = 0; 1033 virtual uint64_t GetRegMaskCommon(RegStorage reg) = 0; 1034 virtual void AdjustSpillMask() = 0; 1035 virtual void ClobberCallerSave() = 0; 1036 virtual void FreeCallTemps() = 0; 1037 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 1038 virtual void LockCallTemps() = 0; 1039 virtual void MarkPreservedSingle(int v_reg, RegStorage reg) = 0; 1040 virtual void MarkPreservedDouble(int v_reg, RegStorage reg) = 0; 1041 virtual void CompilerInitializeRegAlloc() = 0; 1042 1043 // Required for target - miscellaneous. 1044 virtual void AssembleLIR() = 0; 1045 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 1046 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 1047 virtual const char* GetTargetInstFmt(int opcode) = 0; 1048 virtual const char* GetTargetInstName(int opcode) = 0; 1049 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 1050 virtual uint64_t GetPCUseDefEncoding() = 0; 1051 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 1052 virtual int GetInsnSize(LIR* lir) = 0; 1053 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 1054 1055 // Required for target - Dalvik-level generators. 1056 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1057 RegLocation rl_src1, RegLocation rl_src2) = 0; 1058 virtual void GenMulLong(Instruction::Code, 1059 RegLocation rl_dest, RegLocation rl_src1, 1060 RegLocation rl_src2) = 0; 1061 virtual void GenAddLong(Instruction::Code, 1062 RegLocation rl_dest, RegLocation rl_src1, 1063 RegLocation rl_src2) = 0; 1064 virtual void GenAndLong(Instruction::Code, 1065 RegLocation rl_dest, RegLocation rl_src1, 1066 RegLocation rl_src2) = 0; 1067 virtual void GenArithOpDouble(Instruction::Code opcode, 1068 RegLocation rl_dest, RegLocation rl_src1, 1069 RegLocation rl_src2) = 0; 1070 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 1071 RegLocation rl_src1, RegLocation rl_src2) = 0; 1072 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 1073 RegLocation rl_src1, RegLocation rl_src2) = 0; 1074 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 1075 RegLocation rl_src) = 0; 1076 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 1077 1078 /** 1079 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 1080 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 1081 * that applies on integers. The generated code will write the smallest or largest value 1082 * directly into the destination register as specified by the invoke information. 1083 * @param info Information about the invoke. 1084 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 1085 * @return Returns true if successfully generated 1086 */ 1087 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 1088 1089 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 1090 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 1091 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 1092 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 1093 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1094 RegLocation rl_src2) = 0; 1095 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1096 RegLocation rl_src2) = 0; 1097 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1098 RegLocation rl_src2) = 0; 1099 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 1100 bool is_div) = 0; 1101 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 1102 bool is_div) = 0; 1103 /* 1104 * @brief Generate an integer div or rem operation by a literal. 1105 * @param rl_dest Destination Location. 1106 * @param rl_src1 Numerator Location. 1107 * @param rl_src2 Divisor Location. 1108 * @param is_div 'true' if this is a division, 'false' for a remainder. 1109 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 1110 */ 1111 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 1112 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 1113 /* 1114 * @brief Generate an integer div or rem operation by a literal. 1115 * @param rl_dest Destination Location. 1116 * @param rl_src Numerator Location. 1117 * @param lit Divisor. 1118 * @param is_div 'true' if this is a division, 'false' for a remainder. 1119 */ 1120 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 1121 bool is_div) = 0; 1122 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 1123 1124 /** 1125 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 1126 * @details This is used for generating DivideByZero checks when divisor is held in two 1127 * separate registers. 1128 * @param reg The register holding the pair of 32-bit values. 1129 */ 1130 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1131 1132 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1133 virtual void GenExitSequence() = 0; 1134 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1135 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1136 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1137 1138 /** 1139 * @brief Lowers the kMirOpSelect MIR into LIR. 1140 * @param bb The basic block in which the MIR is from. 1141 * @param mir The MIR whose opcode is kMirOpSelect. 1142 */ 1143 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1144 1145 /** 1146 * @brief Used to generate a memory barrier in an architecture specific way. 1147 * @details The last generated LIR will be considered for use as barrier. Namely, 1148 * if the last LIR can be updated in a way where it will serve the semantics of 1149 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1150 * that can keep the semantics. 1151 * @param barrier_kind The kind of memory barrier to generate. 1152 */ 1153 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1154 1155 virtual void GenMoveException(RegLocation rl_dest) = 0; 1156 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1157 int first_bit, int second_bit) = 0; 1158 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1159 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1160 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1161 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1162 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1163 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1164 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1165 RegLocation rl_index, RegLocation rl_src, int scale, 1166 bool card_mark) = 0; 1167 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1168 RegLocation rl_src1, RegLocation rl_shift) = 0; 1169 1170 // Required for target - single operation generators. 1171 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1172 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1173 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1174 LIR* target) = 0; 1175 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1176 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1177 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1178 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1179 virtual void OpEndIT(LIR* it) = 0; 1180 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1181 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1182 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1183 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1184 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1185 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1186 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1187 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1188 1189 /** 1190 * @brief Used to generate an LIR that does a load from mem to reg. 1191 * @param r_dest The destination physical register. 1192 * @param r_base The base physical register for memory operand. 1193 * @param offset The displacement for memory operand. 1194 * @param move_type Specification on the move desired (size, alignment, register kind). 1195 * @return Returns the generate move LIR. 1196 */ 1197 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1198 MoveType move_type) = 0; 1199 1200 /** 1201 * @brief Used to generate an LIR that does a store from reg to mem. 1202 * @param r_base The base physical register for memory operand. 1203 * @param offset The displacement for memory operand. 1204 * @param r_src The destination physical register. 1205 * @param bytes_to_move The number of bytes to move. 1206 * @param is_aligned Whether the memory location is known to be aligned. 1207 * @return Returns the generate move LIR. 1208 */ 1209 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1210 MoveType move_type) = 0; 1211 1212 /** 1213 * @brief Used for generating a conditional register to register operation. 1214 * @param op The opcode kind. 1215 * @param cc The condition code that when true will perform the opcode. 1216 * @param r_dest The destination physical register. 1217 * @param r_src The source physical register. 1218 * @return Returns the newly created LIR or null in case of creation failure. 1219 */ 1220 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1221 1222 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1223 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1224 RegStorage r_src2) = 0; 1225 virtual LIR* OpTestSuspend(LIR* target) = 0; 1226 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1227 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1228 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1229 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1230 int offset) = 0; 1231 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1232 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1233 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1234 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1235 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1236 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1237 1238 // May be optimized by targets. 1239 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1240 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1241 1242 // Temp workaround 1243 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1244 1245 protected: 1246 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1247 1248 CompilationUnit* GetCompilationUnit() { 1249 return cu_; 1250 } 1251 /* 1252 * @brief Returns the index of the lowest set bit in 'x'. 1253 * @param x Value to be examined. 1254 * @returns The bit number of the lowest bit set in the value. 1255 */ 1256 int32_t LowestSetBit(uint64_t x); 1257 /* 1258 * @brief Is this value a power of two? 1259 * @param x Value to be examined. 1260 * @returns 'true' if only 1 bit is set in the value. 1261 */ 1262 bool IsPowerOfTwo(uint64_t x); 1263 /* 1264 * @brief Do these SRs overlap? 1265 * @param rl_op1 One RegLocation 1266 * @param rl_op2 The other RegLocation 1267 * @return 'true' if the VR pairs overlap 1268 * 1269 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1270 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1271 * dex, we'll want to make this case illegal. 1272 */ 1273 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1274 1275 /* 1276 * @brief Force a location (in a register) into a temporary register 1277 * @param loc location of result 1278 * @returns update location 1279 */ 1280 RegLocation ForceTemp(RegLocation loc); 1281 1282 /* 1283 * @brief Force a wide location (in registers) into temporary registers 1284 * @param loc location of result 1285 * @returns update location 1286 */ 1287 RegLocation ForceTempWide(RegLocation loc); 1288 1289 static constexpr OpSize LoadStoreOpSize(bool wide, bool ref) { 1290 return wide ? k64 : ref ? kReference : k32; 1291 } 1292 1293 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1294 RegLocation rl_dest, RegLocation rl_src); 1295 1296 void AddSlowPath(LIRSlowPath* slowpath); 1297 1298 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1299 bool type_known_abstract, bool use_declaring_class, 1300 bool can_assume_type_is_in_dex_cache, 1301 uint32_t type_idx, RegLocation rl_dest, 1302 RegLocation rl_src); 1303 /* 1304 * @brief Generate the debug_frame FDE information if possible. 1305 * @returns pointer to vector containg CFE information, or NULL. 1306 */ 1307 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1308 1309 /** 1310 * @brief Used to insert marker that can be used to associate MIR with LIR. 1311 * @details Only inserts marker if verbosity is enabled. 1312 * @param mir The mir that is currently being generated. 1313 */ 1314 void GenPrintLabel(MIR* mir); 1315 1316 /** 1317 * @brief Used to generate return sequence when there is no frame. 1318 * @details Assumes that the return registers have already been populated. 1319 */ 1320 virtual void GenSpecialExitSequence() = 0; 1321 1322 /** 1323 * @brief Used to generate code for special methods that are known to be 1324 * small enough to work in frameless mode. 1325 * @param bb The basic block of the first MIR. 1326 * @param mir The first MIR of the special method. 1327 * @param special Information about the special method. 1328 * @return Returns whether or not this was handled successfully. Returns false 1329 * if caller should punt to normal MIR2LIR conversion. 1330 */ 1331 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1332 1333 private: 1334 void ClobberBody(RegisterInfo* p); 1335 void SetCurrentDexPc(DexOffset dexpc) { 1336 current_dalvik_offset_ = dexpc; 1337 } 1338 1339 /** 1340 * @brief Used to lock register if argument at in_position was passed that way. 1341 * @details Does nothing if the argument is passed via stack. 1342 * @param in_position The argument number whose register to lock. 1343 * @param wide Whether the argument is wide. 1344 */ 1345 void LockArg(int in_position, bool wide = false); 1346 1347 /** 1348 * @brief Used to load VR argument to a physical register. 1349 * @details The load is only done if the argument is not already in physical register. 1350 * LockArg must have been previously called. 1351 * @param in_position The argument number to load. 1352 * @param wide Whether the argument is 64-bit or not. 1353 * @return Returns the register (or register pair) for the loaded argument. 1354 */ 1355 RegStorage LoadArg(int in_position, bool wide = false); 1356 1357 /** 1358 * @brief Used to load a VR argument directly to a specified register location. 1359 * @param in_position The argument number to place in register. 1360 * @param rl_dest The register location where to place argument. 1361 */ 1362 void LoadArgDirect(int in_position, RegLocation rl_dest); 1363 1364 /** 1365 * @brief Used to generate LIR for special getter method. 1366 * @param mir The mir that represents the iget. 1367 * @param special Information about the special getter method. 1368 * @return Returns whether LIR was successfully generated. 1369 */ 1370 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1371 1372 /** 1373 * @brief Used to generate LIR for special setter method. 1374 * @param mir The mir that represents the iput. 1375 * @param special Information about the special setter method. 1376 * @return Returns whether LIR was successfully generated. 1377 */ 1378 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1379 1380 /** 1381 * @brief Used to generate LIR for special return-args method. 1382 * @param mir The mir that represents the return of argument. 1383 * @param special Information about the special return-args method. 1384 * @return Returns whether LIR was successfully generated. 1385 */ 1386 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1387 1388 void AddDivZeroCheckSlowPath(LIR* branch); 1389 1390 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1391 // kArg2 as temp. 1392 void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1393 1394 public: 1395 // TODO: add accessors for these. 1396 LIR* literal_list_; // Constants. 1397 LIR* method_literal_list_; // Method literals requiring patching. 1398 LIR* class_literal_list_; // Class literals requiring patching. 1399 LIR* code_literal_list_; // Code literals requiring patching. 1400 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1401 1402 protected: 1403 CompilationUnit* const cu_; 1404 MIRGraph* const mir_graph_; 1405 GrowableArray<SwitchTable*> switch_tables_; 1406 GrowableArray<FillArrayData*> fill_array_data_; 1407 GrowableArray<RegisterInfo*> tempreg_info_; 1408 GrowableArray<RegisterInfo*> reginfo_map_; 1409 GrowableArray<void*> pointer_storage_; 1410 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1411 CodeOffset data_offset_; // starting offset of literal pool. 1412 size_t total_size_; // header + code size. 1413 LIR* block_label_list_; 1414 PromotionMap* promotion_map_; 1415 /* 1416 * TODO: The code generation utilities don't have a built-in 1417 * mechanism to propagate the original Dalvik opcode address to the 1418 * associated generated instructions. For the trace compiler, this wasn't 1419 * necessary because the interpreter handled all throws and debugging 1420 * requests. For now we'll handle this by placing the Dalvik offset 1421 * in the CompilationUnit struct before codegen for each instruction. 1422 * The low-level LIR creation utilites will pull it from here. Rework this. 1423 */ 1424 DexOffset current_dalvik_offset_; 1425 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1426 RegisterPool* reg_pool_; 1427 /* 1428 * Sanity checking for the register temp tracking. The same ssa 1429 * name should never be associated with one temp register per 1430 * instruction compilation. 1431 */ 1432 int live_sreg_; 1433 CodeBuffer code_buffer_; 1434 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1435 std::vector<uint8_t> encoded_mapping_table_; 1436 std::vector<uint32_t> core_vmap_table_; 1437 std::vector<uint32_t> fp_vmap_table_; 1438 std::vector<uint8_t> native_gc_map_; 1439 int num_core_spills_; 1440 int num_fp_spills_; 1441 int frame_size_; 1442 unsigned int core_spill_mask_; 1443 unsigned int fp_spill_mask_; 1444 LIR* first_lir_insn_; 1445 LIR* last_lir_insn_; 1446 1447 GrowableArray<LIRSlowPath*> slow_paths_; 1448}; // Class Mir2Lir 1449 1450} // namespace art 1451 1452#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1453