mir_to_lir.h revision 7a11ab09f93f54b1c07c0bf38dd65ed322e86bc6
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 18#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 19 20#include "invoke_type.h" 21#include "compiled_method.h" 22#include "dex/compiler_enums.h" 23#include "dex/compiler_ir.h" 24#include "dex/reg_storage.h" 25#include "dex/backend.h" 26#include "driver/compiler_driver.h" 27#include "leb128.h" 28#include "safe_map.h" 29#include "utils/arena_allocator.h" 30#include "utils/growable_array.h" 31 32namespace art { 33 34/* 35 * TODO: refactoring pass to move these (and other) typdefs towards usage style of runtime to 36 * add type safety (see runtime/offsets.h). 37 */ 38typedef uint32_t DexOffset; // Dex offset in code units. 39typedef uint16_t NarrowDexOffset; // For use in structs, Dex offsets range from 0 .. 0xffff. 40typedef uint32_t CodeOffset; // Native code offset in bytes. 41 42// Set to 1 to measure cost of suspend check. 43#define NO_SUSPEND 0 44 45#define IS_BINARY_OP (1ULL << kIsBinaryOp) 46#define IS_BRANCH (1ULL << kIsBranch) 47#define IS_IT (1ULL << kIsIT) 48#define IS_LOAD (1ULL << kMemLoad) 49#define IS_QUAD_OP (1ULL << kIsQuadOp) 50#define IS_QUIN_OP (1ULL << kIsQuinOp) 51#define IS_SEXTUPLE_OP (1ULL << kIsSextupleOp) 52#define IS_STORE (1ULL << kMemStore) 53#define IS_TERTIARY_OP (1ULL << kIsTertiaryOp) 54#define IS_UNARY_OP (1ULL << kIsUnaryOp) 55#define NEEDS_FIXUP (1ULL << kPCRelFixup) 56#define NO_OPERAND (1ULL << kNoOperand) 57#define REG_DEF0 (1ULL << kRegDef0) 58#define REG_DEF1 (1ULL << kRegDef1) 59#define REG_DEF2 (1ULL << kRegDef2) 60#define REG_DEFA (1ULL << kRegDefA) 61#define REG_DEFD (1ULL << kRegDefD) 62#define REG_DEF_FPCS_LIST0 (1ULL << kRegDefFPCSList0) 63#define REG_DEF_FPCS_LIST2 (1ULL << kRegDefFPCSList2) 64#define REG_DEF_LIST0 (1ULL << kRegDefList0) 65#define REG_DEF_LIST1 (1ULL << kRegDefList1) 66#define REG_DEF_LR (1ULL << kRegDefLR) 67#define REG_DEF_SP (1ULL << kRegDefSP) 68#define REG_USE0 (1ULL << kRegUse0) 69#define REG_USE1 (1ULL << kRegUse1) 70#define REG_USE2 (1ULL << kRegUse2) 71#define REG_USE3 (1ULL << kRegUse3) 72#define REG_USE4 (1ULL << kRegUse4) 73#define REG_USEA (1ULL << kRegUseA) 74#define REG_USEC (1ULL << kRegUseC) 75#define REG_USED (1ULL << kRegUseD) 76#define REG_USEB (1ULL << kRegUseB) 77#define REG_USE_FPCS_LIST0 (1ULL << kRegUseFPCSList0) 78#define REG_USE_FPCS_LIST2 (1ULL << kRegUseFPCSList2) 79#define REG_USE_LIST0 (1ULL << kRegUseList0) 80#define REG_USE_LIST1 (1ULL << kRegUseList1) 81#define REG_USE_LR (1ULL << kRegUseLR) 82#define REG_USE_PC (1ULL << kRegUsePC) 83#define REG_USE_SP (1ULL << kRegUseSP) 84#define SETS_CCODES (1ULL << kSetsCCodes) 85#define USES_CCODES (1ULL << kUsesCCodes) 86#define USE_FP_STACK (1ULL << kUseFpStack) 87#define REG_USE_LO (1ULL << kUseLo) 88#define REG_USE_HI (1ULL << kUseHi) 89#define REG_DEF_LO (1ULL << kDefLo) 90#define REG_DEF_HI (1ULL << kDefHi) 91 92// Common combo register usage patterns. 93#define REG_DEF01 (REG_DEF0 | REG_DEF1) 94#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2) 95#define REG_DEF0_USE01 (REG_DEF0 | REG_USE01) 96#define REG_DEF0_USE0 (REG_DEF0 | REG_USE0) 97#define REG_DEF0_USE12 (REG_DEF0 | REG_USE12) 98#define REG_DEF0_USE123 (REG_DEF0 | REG_USE123) 99#define REG_DEF0_USE1 (REG_DEF0 | REG_USE1) 100#define REG_DEF0_USE2 (REG_DEF0 | REG_USE2) 101#define REG_DEFAD_USEAD (REG_DEFAD_USEA | REG_USED) 102#define REG_DEFAD_USEA (REG_DEFA_USEA | REG_DEFD) 103#define REG_DEFA_USEA (REG_DEFA | REG_USEA) 104#define REG_USE012 (REG_USE01 | REG_USE2) 105#define REG_USE014 (REG_USE01 | REG_USE4) 106#define REG_USE01 (REG_USE0 | REG_USE1) 107#define REG_USE02 (REG_USE0 | REG_USE2) 108#define REG_USE12 (REG_USE1 | REG_USE2) 109#define REG_USE23 (REG_USE2 | REG_USE3) 110#define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) 111 112// TODO: #includes need a cleanup 113#ifndef INVALID_SREG 114#define INVALID_SREG (-1) 115#endif 116 117struct BasicBlock; 118struct CallInfo; 119struct CompilationUnit; 120struct InlineMethod; 121struct MIR; 122struct LIR; 123struct RegLocation; 124struct RegisterInfo; 125class DexFileMethodInliner; 126class MIRGraph; 127class Mir2Lir; 128 129typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, 130 const MethodReference& target_method, 131 uint32_t method_idx, uintptr_t direct_code, 132 uintptr_t direct_method, InvokeType type); 133 134typedef std::vector<uint8_t> CodeBuffer; 135 136struct UseDefMasks { 137 uint64_t use_mask; // Resource mask for use. 138 uint64_t def_mask; // Resource mask for def. 139}; 140 141struct AssemblyInfo { 142 LIR* pcrel_next; // Chain of LIR nodes needing pc relative fixups. 143}; 144 145struct LIR { 146 CodeOffset offset; // Offset of this instruction. 147 NarrowDexOffset dalvik_offset; // Offset of Dalvik opcode in code units (16-bit words). 148 int16_t opcode; 149 LIR* next; 150 LIR* prev; 151 LIR* target; 152 struct { 153 unsigned int alias_info:17; // For Dalvik register disambiguation. 154 bool is_nop:1; // LIR is optimized away. 155 unsigned int size:4; // Note: size of encoded instruction is in bytes. 156 bool use_def_invalid:1; // If true, masks should not be used. 157 unsigned int generation:1; // Used to track visitation state during fixup pass. 158 unsigned int fixup:8; // Fixup kind. 159 } flags; 160 union { 161 UseDefMasks m; // Use & Def masks used during optimization. 162 AssemblyInfo a; // Instruction info used during assembly phase. 163 } u; 164 int32_t operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. 165}; 166 167// Target-specific initialization. 168Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 169 ArenaAllocator* const arena); 170Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 171 ArenaAllocator* const arena); 172Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, 173 ArenaAllocator* const arena); 174 175// Utility macros to traverse the LIR list. 176#define NEXT_LIR(lir) (lir->next) 177#define PREV_LIR(lir) (lir->prev) 178 179// Defines for alias_info (tracks Dalvik register references). 180#define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) 181#define DECODE_ALIAS_INFO_WIDE_FLAG (0x10000) 182#define DECODE_ALIAS_INFO_WIDE(X) ((X & DECODE_ALIAS_INFO_WIDE_FLAG) ? 1 : 0) 183#define ENCODE_ALIAS_INFO(REG, ISWIDE) (REG | (ISWIDE ? DECODE_ALIAS_INFO_WIDE_FLAG : 0)) 184 185// Common resource macros. 186#define ENCODE_CCODE (1ULL << kCCode) 187#define ENCODE_FP_STATUS (1ULL << kFPStatus) 188 189// Abstract memory locations. 190#define ENCODE_DALVIK_REG (1ULL << kDalvikReg) 191#define ENCODE_LITERAL (1ULL << kLiteral) 192#define ENCODE_HEAP_REF (1ULL << kHeapRef) 193#define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) 194 195#define ENCODE_ALL (~0ULL) 196#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ 197 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) 198 199#define ENCODE_REG_PAIR(low_reg, high_reg) ((low_reg & 0xff) | ((high_reg & 0xff) << 8)) 200#define DECODE_REG_PAIR(both_regs, low_reg, high_reg) \ 201 do { \ 202 low_reg = both_regs & 0xff; \ 203 high_reg = (both_regs >> 8) & 0xff; \ 204 } while (false) 205 206// Mask to denote sreg as the start of a double. Must not interfere with low 16 bits. 207#define STARTING_DOUBLE_SREG 0x10000 208 209// TODO: replace these macros 210#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) 211#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) 212#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) 213#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) 214#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) 215 216class Mir2Lir : public Backend { 217 public: 218 /* 219 * Auxiliary information describing the location of data embedded in the Dalvik 220 * byte code stream. 221 */ 222 struct EmbeddedData { 223 CodeOffset offset; // Code offset of data block. 224 const uint16_t* table; // Original dex data. 225 DexOffset vaddr; // Dalvik offset of parent opcode. 226 }; 227 228 struct FillArrayData : EmbeddedData { 229 int32_t size; 230 }; 231 232 struct SwitchTable : EmbeddedData { 233 LIR* anchor; // Reference instruction for relative offsets. 234 LIR** targets; // Array of case targets. 235 }; 236 237 /* Static register use counts */ 238 struct RefCounts { 239 int count; 240 int s_reg; 241 }; 242 243 /* 244 * Data structure tracking the mapping between a Dalvik register (pair) and a 245 * native register (pair). The idea is to reuse the previously loaded value 246 * if possible, otherwise to keep the value in a native register as long as 247 * possible. 248 */ 249 struct RegisterInfo { 250 int reg; // Reg number 251 bool in_use; // Has it been allocated? 252 bool is_temp; // Can allocate as temp? 253 bool pair; // Part of a register pair? 254 int partner; // If pair, other reg of pair. 255 bool live; // Is there an associated SSA name? 256 bool dirty; // If live, is it dirty? 257 int s_reg; // Name of live value. 258 LIR *def_start; // Starting inst in last def sequence. 259 LIR *def_end; // Ending inst in last def sequence. 260 }; 261 262 struct RegisterPool { 263 int num_core_regs; 264 RegisterInfo *core_regs; 265 int next_core_reg; 266 int num_fp_regs; 267 RegisterInfo *FPRegs; 268 int next_fp_reg; 269 }; 270 271 struct PromotionMap { 272 RegLocationType core_location:3; 273 uint8_t core_reg; 274 RegLocationType fp_location:3; 275 uint8_t FpReg; 276 bool first_in_pair; 277 }; 278 279 // 280 // Slow paths. This object is used generate a sequence of code that is executed in the 281 // slow path. For example, resolving a string or class is slow as it will only be executed 282 // once (after that it is resolved and doesn't need to be done again). We want slow paths 283 // to be placed out-of-line, and not require a (mispredicted, probably) conditional forward 284 // branch over them. 285 // 286 // If you want to create a slow path, declare a class derived from LIRSlowPath and provide 287 // the Compile() function that will be called near the end of the code generated by the 288 // method. 289 // 290 // The basic flow for a slow path is: 291 // 292 // CMP reg, #value 293 // BEQ fromfast 294 // cont: 295 // ... 296 // fast path code 297 // ... 298 // more code 299 // ... 300 // RETURN 301 /// 302 // fromfast: 303 // ... 304 // slow path code 305 // ... 306 // B cont 307 // 308 // So you see we need two labels and two branches. The first branch (called fromfast) is 309 // the conditional branch to the slow path code. The second label (called cont) is used 310 // as an unconditional branch target for getting back to the code after the slow path 311 // has completed. 312 // 313 314 class LIRSlowPath { 315 public: 316 LIRSlowPath(Mir2Lir* m2l, const DexOffset dexpc, LIR* fromfast, 317 LIR* cont = nullptr) : 318 m2l_(m2l), current_dex_pc_(dexpc), fromfast_(fromfast), cont_(cont) { 319 } 320 virtual ~LIRSlowPath() {} 321 virtual void Compile() = 0; 322 323 static void* operator new(size_t size, ArenaAllocator* arena) { 324 return arena->Alloc(size, kArenaAllocData); 325 } 326 327 protected: 328 LIR* GenerateTargetLabel(); 329 330 Mir2Lir* const m2l_; 331 const DexOffset current_dex_pc_; 332 LIR* const fromfast_; 333 LIR* const cont_; 334 }; 335 336 virtual ~Mir2Lir() {} 337 338 int32_t s4FromSwitchData(const void* switch_data) { 339 return *reinterpret_cast<const int32_t*>(switch_data); 340 } 341 342 RegisterClass oat_reg_class_by_size(OpSize size) { 343 return (size == kUnsignedHalf || size == kSignedHalf || size == kUnsignedByte || 344 size == kSignedByte) ? kCoreReg : kAnyReg; 345 } 346 347 size_t CodeBufferSizeInBytes() { 348 return code_buffer_.size() / sizeof(code_buffer_[0]); 349 } 350 351 static bool IsPseudoLirOp(int opcode) { 352 return (opcode < 0); 353 } 354 355 /* 356 * LIR operands are 32-bit integers. Sometimes, (especially for managing 357 * instructions which require PC-relative fixups), we need the operands to carry 358 * pointers. To do this, we assign these pointers an index in pointer_storage_, and 359 * hold that index in the operand array. 360 * TUNING: If use of these utilities becomes more common on 32-bit builds, it 361 * may be worth conditionally-compiling a set of identity functions here. 362 */ 363 uint32_t WrapPointer(void* pointer) { 364 uint32_t res = pointer_storage_.Size(); 365 pointer_storage_.Insert(pointer); 366 return res; 367 } 368 369 void* UnwrapPointer(size_t index) { 370 return pointer_storage_.Get(index); 371 } 372 373 // strdup(), but allocates from the arena. 374 char* ArenaStrdup(const char* str) { 375 size_t len = strlen(str) + 1; 376 char* res = reinterpret_cast<char*>(arena_->Alloc(len, kArenaAllocMisc)); 377 if (res != NULL) { 378 strncpy(res, str, len); 379 } 380 return res; 381 } 382 383 // Shared by all targets - implemented in codegen_util.cc 384 void AppendLIR(LIR* lir); 385 void InsertLIRBefore(LIR* current_lir, LIR* new_lir); 386 void InsertLIRAfter(LIR* current_lir, LIR* new_lir); 387 388 /** 389 * @brief Provides the maximum number of compiler temporaries that the backend can/wants 390 * to place in a frame. 391 * @return Returns the maximum number of compiler temporaries. 392 */ 393 size_t GetMaxPossibleCompilerTemps() const; 394 395 /** 396 * @brief Provides the number of bytes needed in frame for spilling of compiler temporaries. 397 * @return Returns the size in bytes for space needed for compiler temporary spill region. 398 */ 399 size_t GetNumBytesForCompilerTempSpillRegion(); 400 401 DexOffset GetCurrentDexPc() const { 402 return current_dalvik_offset_; 403 } 404 405 int ComputeFrameSize(); 406 virtual void Materialize(); 407 virtual CompiledMethod* GetCompiledMethod(); 408 void MarkSafepointPC(LIR* inst); 409 void SetupResourceMasks(LIR* lir); 410 void SetMemRefType(LIR* lir, bool is_load, int mem_type); 411 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit); 412 void SetupRegMask(uint64_t* mask, int reg); 413 void DumpLIRInsn(LIR* arg, unsigned char* base_addr); 414 void DumpPromotionMap(); 415 void CodegenDump(); 416 LIR* RawLIR(DexOffset dalvik_offset, int opcode, int op0 = 0, int op1 = 0, 417 int op2 = 0, int op3 = 0, int op4 = 0, LIR* target = NULL); 418 LIR* NewLIR0(int opcode); 419 LIR* NewLIR1(int opcode, int dest); 420 LIR* NewLIR2(int opcode, int dest, int src1); 421 LIR* NewLIR2NoDest(int opcode, int src, int info); 422 LIR* NewLIR3(int opcode, int dest, int src1, int src2); 423 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info); 424 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2); 425 LIR* ScanLiteralPool(LIR* data_target, int value, unsigned int delta); 426 LIR* ScanLiteralPoolWide(LIR* data_target, int val_lo, int val_hi); 427 LIR* AddWordData(LIR* *constant_list_p, int value); 428 LIR* AddWideData(LIR* *constant_list_p, int val_lo, int val_hi); 429 void ProcessSwitchTables(); 430 void DumpSparseSwitchTable(const uint16_t* table); 431 void DumpPackedSwitchTable(const uint16_t* table); 432 void MarkBoundary(DexOffset offset, const char* inst_str); 433 void NopLIR(LIR* lir); 434 void UnlinkLIR(LIR* lir); 435 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2); 436 bool IsInexpensiveConstant(RegLocation rl_src); 437 ConditionCode FlipComparisonOrder(ConditionCode before); 438 ConditionCode NegateComparison(ConditionCode before); 439 virtual void InstallLiteralPools(); 440 void InstallSwitchTables(); 441 void InstallFillArrayData(); 442 bool VerifyCatchEntries(); 443 void CreateMappingTables(); 444 void CreateNativeGcMap(); 445 int AssignLiteralOffset(CodeOffset offset); 446 int AssignSwitchTablesOffset(CodeOffset offset); 447 int AssignFillArrayDataOffset(CodeOffset offset); 448 LIR* InsertCaseLabel(DexOffset vaddr, int keyVal); 449 void MarkPackedCaseLabels(Mir2Lir::SwitchTable* tab_rec); 450 void MarkSparseCaseLabels(Mir2Lir::SwitchTable* tab_rec); 451 // Handle bookkeeping to convert a wide RegLocation to a narow RegLocation. No code generated. 452 RegLocation NarrowRegLoc(RegLocation loc); 453 454 // Shared by all targets - implemented in local_optimizations.cc 455 void ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src); 456 void ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir); 457 void ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir); 458 void ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir); 459 460 // Shared by all targets - implemented in ralloc_util.cc 461 int GetSRegHi(int lowSreg); 462 bool oat_live_out(int s_reg); 463 int oatSSASrc(MIR* mir, int num); 464 void SimpleRegAlloc(); 465 void ResetRegPool(); 466 void CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num); 467 void DumpRegPool(RegisterInfo* p, int num_regs); 468 void DumpCoreRegPool(); 469 void DumpFpRegPool(); 470 /* Mark a temp register as dead. Does not affect allocation state. */ 471 void Clobber(int reg) { 472 ClobberBody(GetRegInfo(reg)); 473 } 474 void Clobber(RegStorage reg); 475 void ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg); 476 void ClobberSReg(int s_reg); 477 int SRegToPMap(int s_reg); 478 void RecordCorePromotion(RegStorage reg, int s_reg); 479 RegStorage AllocPreservedCoreReg(int s_reg); 480 void RecordFpPromotion(RegStorage reg, int s_reg); 481 RegStorage AllocPreservedSingle(int s_reg); 482 RegStorage AllocPreservedDouble(int s_reg); 483 RegStorage AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, bool required); 484 virtual RegStorage AllocTempDouble(); 485 RegStorage AllocFreeTemp(); 486 RegStorage AllocTemp(); 487 RegStorage AllocTempFloat(); 488 RegisterInfo* AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg); 489 RegisterInfo* AllocLive(int s_reg, int reg_class); 490 void FreeTemp(int reg); 491 void FreeTemp(RegStorage reg); 492 RegisterInfo* IsLive(int reg); 493 bool IsLive(RegStorage reg); 494 RegisterInfo* IsTemp(int reg); 495 bool IsTemp(RegStorage reg); 496 RegisterInfo* IsPromoted(int reg); 497 bool IsPromoted(RegStorage reg); 498 bool IsDirty(int reg); 499 bool IsDirty(RegStorage reg); 500 void LockTemp(int reg); 501 void LockTemp(RegStorage reg); 502 void ResetDef(int reg); 503 void ResetDef(RegStorage reg); 504 void NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2); 505 void MarkDef(RegLocation rl, LIR *start, LIR *finish); 506 void MarkDefWide(RegLocation rl, LIR *start, LIR *finish); 507 RegLocation WideToNarrow(RegLocation rl); 508 void ResetDefLoc(RegLocation rl); 509 virtual void ResetDefLocWide(RegLocation rl); 510 void ResetDefTracking(); 511 void ClobberAllRegs(); 512 void FlushSpecificReg(RegisterInfo* info); 513 void FlushAllRegsBody(RegisterInfo* info, int num_regs); 514 void FlushAllRegs(); 515 bool RegClassMatches(int reg_class, RegStorage reg); 516 void MarkLive(RegStorage reg, int s_reg); 517 void MarkTemp(int reg); 518 void MarkTemp(RegStorage reg); 519 void UnmarkTemp(int reg); 520 void UnmarkTemp(RegStorage reg); 521 void MarkPair(int low_reg, int high_reg); 522 void MarkClean(RegLocation loc); 523 void MarkDirty(RegLocation loc); 524 void MarkInUse(int reg); 525 void MarkInUse(RegStorage reg); 526 void CopyRegInfo(int new_reg, int old_reg); 527 void CopyRegInfo(RegStorage new_reg, RegStorage old_reg); 528 bool CheckCorePoolSanity(); 529 RegLocation UpdateLoc(RegLocation loc); 530 virtual RegLocation UpdateLocWide(RegLocation loc); 531 RegLocation UpdateRawLoc(RegLocation loc); 532 533 /** 534 * @brief Used to load register location into a typed temporary or pair of temporaries. 535 * @see EvalLoc 536 * @param loc The register location to load from. 537 * @param reg_class Type of register needed. 538 * @param update Whether the liveness information should be updated. 539 * @return Returns the properly typed temporary in physical register pairs. 540 */ 541 virtual RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 542 543 /** 544 * @brief Used to load register location into a typed temporary. 545 * @param loc The register location to load from. 546 * @param reg_class Type of register needed. 547 * @param update Whether the liveness information should be updated. 548 * @return Returns the properly typed temporary in physical register. 549 */ 550 virtual RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 551 552 void CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs); 553 void DumpCounts(const RefCounts* arr, int size, const char* msg); 554 void DoPromotion(); 555 int VRegOffset(int v_reg); 556 int SRegOffset(int s_reg); 557 RegLocation GetReturnWide(bool is_double); 558 RegLocation GetReturn(bool is_float); 559 RegisterInfo* GetRegInfo(int reg); 560 561 // Shared by all targets - implemented in gen_common.cc. 562 void AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume = nullptr); 563 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 564 RegLocation rl_src, RegLocation rl_dest, int lit); 565 bool HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit); 566 void HandleSuspendLaunchPads(); 567 void HandleSlowPaths(); 568 void GenBarrier(); 569 void GenDivZeroException(); 570 // c_code holds condition code that's generated from testing divisor against 0. 571 void GenDivZeroCheck(ConditionCode c_code); 572 // reg holds divisor. 573 void GenDivZeroCheck(RegStorage reg); 574 void GenArrayBoundsCheck(RegStorage index, RegStorage length); 575 void GenArrayBoundsCheck(int32_t index, RegStorage length); 576 LIR* GenNullCheck(RegStorage reg); 577 void MarkPossibleNullPointerException(int opt_flags); 578 void MarkPossibleStackOverflowException(); 579 void ForceImplicitNullCheck(RegStorage reg, int opt_flags); 580 LIR* GenImmedCheck(ConditionCode c_code, RegStorage reg, int imm_val, ThrowKind kind); 581 LIR* GenNullCheck(RegStorage m_reg, int opt_flags); 582 LIR* GenExplicitNullCheck(RegStorage m_reg, int opt_flags); 583 void GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 584 RegLocation rl_src2, LIR* taken, LIR* fall_through); 585 void GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, 586 LIR* taken, LIR* fall_through); 587 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 588 void GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 589 RegLocation rl_src); 590 void GenNewArray(uint32_t type_idx, RegLocation rl_dest, 591 RegLocation rl_src); 592 void GenFilledNewArray(CallInfo* info); 593 void GenSput(MIR* mir, RegLocation rl_src, 594 bool is_long_or_double, bool is_object); 595 void GenSget(MIR* mir, RegLocation rl_dest, 596 bool is_long_or_double, bool is_object); 597 void GenIGet(MIR* mir, int opt_flags, OpSize size, 598 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, bool is_object); 599 void GenIPut(MIR* mir, int opt_flags, OpSize size, 600 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, bool is_object); 601 void GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 602 RegLocation rl_src); 603 604 void GenConstClass(uint32_t type_idx, RegLocation rl_dest); 605 void GenConstString(uint32_t string_idx, RegLocation rl_dest); 606 void GenNewInstance(uint32_t type_idx, RegLocation rl_dest); 607 void GenThrow(RegLocation rl_src); 608 void GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 609 void GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src); 610 void GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 611 RegLocation rl_src1, RegLocation rl_src2); 612 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 613 RegLocation rl_src1, RegLocation rl_shift); 614 void GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, 615 RegLocation rl_src, int lit); 616 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 617 RegLocation rl_src1, RegLocation rl_src2); 618 void GenConversionCall(ThreadOffset<4> func_offset, RegLocation rl_dest, 619 RegLocation rl_src); 620 void GenSuspendTest(int opt_flags); 621 void GenSuspendTestAndBranch(int opt_flags, LIR* target); 622 623 // This will be overridden by x86 implementation. 624 virtual void GenConstWide(RegLocation rl_dest, int64_t value); 625 virtual void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 626 RegLocation rl_src1, RegLocation rl_src2); 627 628 // Shared by all targets - implemented in gen_invoke.cc. 629 LIR* CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, bool safepoint_pc, 630 bool use_link = true); 631 RegStorage CallHelperSetup(ThreadOffset<4> helper_offset); 632 void CallRuntimeHelper(ThreadOffset<4> helper_offset, bool safepoint_pc); 633 void CallRuntimeHelperImm(ThreadOffset<4> helper_offset, int arg0, bool safepoint_pc); 634 void CallRuntimeHelperReg(ThreadOffset<4> helper_offset, RegStorage arg0, bool safepoint_pc); 635 void CallRuntimeHelperRegLocation(ThreadOffset<4> helper_offset, RegLocation arg0, 636 bool safepoint_pc); 637 void CallRuntimeHelperImmImm(ThreadOffset<4> helper_offset, int arg0, int arg1, 638 bool safepoint_pc); 639 void CallRuntimeHelperImmRegLocation(ThreadOffset<4> helper_offset, int arg0, 640 RegLocation arg1, bool safepoint_pc); 641 void CallRuntimeHelperRegLocationImm(ThreadOffset<4> helper_offset, RegLocation arg0, 642 int arg1, bool safepoint_pc); 643 void CallRuntimeHelperImmReg(ThreadOffset<4> helper_offset, int arg0, RegStorage arg1, 644 bool safepoint_pc); 645 void CallRuntimeHelperRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, int arg1, 646 bool safepoint_pc); 647 void CallRuntimeHelperImmMethod(ThreadOffset<4> helper_offset, int arg0, 648 bool safepoint_pc); 649 void CallRuntimeHelperRegMethod(ThreadOffset<4> helper_offset, RegStorage arg0, 650 bool safepoint_pc); 651 void CallRuntimeHelperRegMethodRegLocation(ThreadOffset<4> helper_offset, RegStorage arg0, 652 RegLocation arg2, bool safepoint_pc); 653 void CallRuntimeHelperRegLocationRegLocation(ThreadOffset<4> helper_offset, 654 RegLocation arg0, RegLocation arg1, 655 bool safepoint_pc); 656 void CallRuntimeHelperRegReg(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 657 bool safepoint_pc); 658 void CallRuntimeHelperRegRegImm(ThreadOffset<4> helper_offset, RegStorage arg0, RegStorage arg1, 659 int arg2, bool safepoint_pc); 660 void CallRuntimeHelperImmMethodRegLocation(ThreadOffset<4> helper_offset, int arg0, 661 RegLocation arg2, bool safepoint_pc); 662 void CallRuntimeHelperImmMethodImm(ThreadOffset<4> helper_offset, int arg0, int arg2, 663 bool safepoint_pc); 664 void CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<4> helper_offset, 665 int arg0, RegLocation arg1, RegLocation arg2, 666 bool safepoint_pc); 667 void CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<4> helper_offset, 668 RegLocation arg0, RegLocation arg1, 669 RegLocation arg2, 670 bool safepoint_pc); 671 void GenInvoke(CallInfo* info); 672 void GenInvokeNoInline(CallInfo* info); 673 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 674 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 675 NextCallInsn next_call_insn, 676 const MethodReference& target_method, 677 uint32_t vtable_idx, 678 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 679 bool skip_this); 680 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 681 NextCallInsn next_call_insn, 682 const MethodReference& target_method, 683 uint32_t vtable_idx, 684 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 685 bool skip_this); 686 687 /** 688 * @brief Used to determine the register location of destination. 689 * @details This is needed during generation of inline intrinsics because it finds destination 690 * of return, 691 * either the physical register or the target of move-result. 692 * @param info Information about the invoke. 693 * @return Returns the destination location. 694 */ 695 RegLocation InlineTarget(CallInfo* info); 696 697 /** 698 * @brief Used to determine the wide register location of destination. 699 * @see InlineTarget 700 * @param info Information about the invoke. 701 * @return Returns the destination location. 702 */ 703 RegLocation InlineTargetWide(CallInfo* info); 704 705 bool GenInlinedCharAt(CallInfo* info); 706 bool GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty); 707 bool GenInlinedReverseBytes(CallInfo* info, OpSize size); 708 bool GenInlinedAbsInt(CallInfo* info); 709 bool GenInlinedAbsLong(CallInfo* info); 710 bool GenInlinedAbsFloat(CallInfo* info); 711 bool GenInlinedAbsDouble(CallInfo* info); 712 bool GenInlinedFloatCvt(CallInfo* info); 713 bool GenInlinedDoubleCvt(CallInfo* info); 714 virtual bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 715 bool GenInlinedStringCompareTo(CallInfo* info); 716 bool GenInlinedCurrentThread(CallInfo* info); 717 bool GenInlinedUnsafeGet(CallInfo* info, bool is_long, bool is_volatile); 718 bool GenInlinedUnsafePut(CallInfo* info, bool is_long, bool is_object, 719 bool is_volatile, bool is_ordered); 720 int LoadArgRegs(CallInfo* info, int call_state, 721 NextCallInsn next_call_insn, 722 const MethodReference& target_method, 723 uint32_t vtable_idx, 724 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 725 bool skip_this); 726 727 // Shared by all targets - implemented in gen_loadstore.cc. 728 RegLocation LoadCurrMethod(); 729 void LoadCurrMethodDirect(RegStorage r_tgt); 730 LIR* LoadConstant(RegStorage r_dest, int value); 731 // Natural word size. 732 LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 733 return LoadBaseDisp(r_base, displacement, r_dest, kWord, INVALID_SREG); 734 } 735 // Load 32 bits, regardless of target. 736 LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { 737 return LoadBaseDisp(r_base, displacement, r_dest, k32, INVALID_SREG); 738 } 739 // Load a reference at base + displacement and decompress into register. 740 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest) { 741 return LoadBaseDisp(r_base, displacement, r_dest, kReference, INVALID_SREG); 742 } 743 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 744 RegLocation LoadValue(RegLocation rl_src, RegisterClass op_kind); 745 // Load Dalvik value with 64-bit memory storage. 746 RegLocation LoadValueWide(RegLocation rl_src, RegisterClass op_kind); 747 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 748 void LoadValueDirect(RegLocation rl_src, RegStorage r_dest); 749 // Load Dalvik value with 32-bit memory storage. If compressed object reference, decompress. 750 void LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest); 751 // Load Dalvik value with 64-bit memory storage. 752 void LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest); 753 // Load Dalvik value with 64-bit memory storage. 754 void LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest); 755 // Store an item of natural word size. 756 LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { 757 return StoreBaseDisp(r_base, displacement, r_src, kWord); 758 } 759 // Store an uncompressed reference into a compressed 32-bit container. 760 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src) { 761 return StoreBaseDisp(r_base, displacement, r_src, kReference); 762 } 763 // Store 32 bits, regardless of target. 764 LIR* Store32Disp(RegStorage r_base, int displacement, RegStorage r_src) { 765 return StoreBaseDisp(r_base, displacement, r_src, k32); 766 } 767 768 /** 769 * @brief Used to do the final store in the destination as per bytecode semantics. 770 * @param rl_dest The destination dalvik register location. 771 * @param rl_src The source register location. Can be either physical register or dalvik register. 772 */ 773 void StoreValue(RegLocation rl_dest, RegLocation rl_src); 774 775 /** 776 * @brief Used to do the final store in a wide destination as per bytecode semantics. 777 * @see StoreValue 778 * @param rl_dest The destination dalvik register location. 779 * @param rl_src The source register location. Can be either physical register or dalvik 780 * register. 781 */ 782 void StoreValueWide(RegLocation rl_dest, RegLocation rl_src); 783 784 /** 785 * @brief Used to do the final store to a destination as per bytecode semantics. 786 * @see StoreValue 787 * @param rl_dest The destination dalvik register location. 788 * @param rl_src The source register location. It must be kLocPhysReg 789 * 790 * This is used for x86 two operand computations, where we have computed the correct 791 * register value that now needs to be properly registered. This is used to avoid an 792 * extra register copy that would result if StoreValue was called. 793 */ 794 void StoreFinalValue(RegLocation rl_dest, RegLocation rl_src); 795 796 /** 797 * @brief Used to do the final store in a wide destination as per bytecode semantics. 798 * @see StoreValueWide 799 * @param rl_dest The destination dalvik register location. 800 * @param rl_src The source register location. It must be kLocPhysReg 801 * 802 * This is used for x86 two operand computations, where we have computed the correct 803 * register values that now need to be properly registered. This is used to avoid an 804 * extra pair of register copies that would result if StoreValueWide was called. 805 */ 806 void StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src); 807 808 // Shared by all targets - implemented in mir_to_lir.cc. 809 void CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list); 810 void HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir); 811 bool MethodBlockCodeGen(BasicBlock* bb); 812 bool SpecialMIR2LIR(const InlineMethod& special); 813 void MethodMIR2LIR(); 814 // Update LIR for verbose listings. 815 void UpdateLIROffsets(); 816 817 /* 818 * @brief Load the address of the dex method into the register. 819 * @param target_method The MethodReference of the method to be invoked. 820 * @param type How the method will be invoked. 821 * @param register that will contain the code address. 822 * @note register will be passed to TargetReg to get physical register. 823 */ 824 void LoadCodeAddress(const MethodReference& target_method, InvokeType type, 825 SpecialTargetRegister symbolic_reg); 826 827 /* 828 * @brief Load the Method* of a dex method into the register. 829 * @param target_method The MethodReference of the method to be invoked. 830 * @param type How the method will be invoked. 831 * @param register that will contain the code address. 832 * @note register will be passed to TargetReg to get physical register. 833 */ 834 virtual void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 835 SpecialTargetRegister symbolic_reg); 836 837 /* 838 * @brief Load the Class* of a Dex Class type into the register. 839 * @param type How the method will be invoked. 840 * @param register that will contain the code address. 841 * @note register will be passed to TargetReg to get physical register. 842 */ 843 virtual void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 844 845 // Routines that work for the generic case, but may be overriden by target. 846 /* 847 * @brief Compare memory to immediate, and branch if condition true. 848 * @param cond The condition code that when true will branch to the target. 849 * @param temp_reg A temporary register that can be used if compare to memory is not 850 * supported by the architecture. 851 * @param base_reg The register holding the base address. 852 * @param offset The offset from the base. 853 * @param check_value The immediate to compare to. 854 * @returns The branch instruction that was generated. 855 */ 856 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 857 int offset, int check_value, LIR* target); 858 859 // Required for target - codegen helpers. 860 virtual bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 861 RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 862 virtual bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) = 0; 863 virtual LIR* CheckSuspendUsingLoad() = 0; 864 virtual RegStorage LoadHelper(ThreadOffset<4> offset) = 0; 865 virtual LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 866 int s_reg) = 0; 867 virtual LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 868 int s_reg) = 0; 869 virtual LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 870 int scale, OpSize size) = 0; 871 virtual LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 872 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 873 OpSize size, int s_reg) = 0; 874 virtual LIR* LoadConstantNoClobber(RegStorage r_dest, int value) = 0; 875 virtual LIR* LoadConstantWide(RegStorage r_dest, int64_t value) = 0; 876 virtual LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 877 OpSize size) = 0; 878 virtual LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) = 0; 879 virtual LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 880 int scale, OpSize size) = 0; 881 virtual LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 882 int displacement, RegStorage r_src, RegStorage r_src_hi, 883 OpSize size, int s_reg) = 0; 884 virtual void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) = 0; 885 886 // Required for target - register utilities. 887 virtual bool IsFpReg(int reg) = 0; 888 virtual bool IsFpReg(RegStorage reg) = 0; 889 virtual bool SameRegType(int reg1, int reg2) = 0; 890 virtual RegStorage AllocTypedTemp(bool fp_hint, int reg_class) = 0; 891 virtual RegStorage AllocTypedTempWide(bool fp_hint, int reg_class) = 0; 892 // TODO: elminate S2d. 893 virtual int S2d(int low_reg, int high_reg) = 0; 894 virtual RegStorage TargetReg(SpecialTargetRegister reg) = 0; 895 virtual RegStorage GetArgMappingToPhysicalReg(int arg_num) = 0; 896 virtual RegLocation GetReturnAlt() = 0; 897 virtual RegLocation GetReturnWideAlt() = 0; 898 virtual RegLocation LocCReturn() = 0; 899 virtual RegLocation LocCReturnDouble() = 0; 900 virtual RegLocation LocCReturnFloat() = 0; 901 virtual RegLocation LocCReturnWide() = 0; 902 // TODO: use to reduce/eliminate xx_FPREG() macro use. 903 virtual uint32_t FpRegMask() = 0; 904 virtual uint64_t GetRegMaskCommon(int reg) = 0; 905 virtual void AdjustSpillMask() = 0; 906 virtual void ClobberCallerSave() = 0; 907 virtual void FlushReg(RegStorage reg) = 0; 908 virtual void FlushRegWide(RegStorage reg) = 0; 909 virtual void FreeCallTemps() = 0; 910 virtual void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) = 0; 911 virtual void LockCallTemps() = 0; 912 virtual void MarkPreservedSingle(int v_reg, int reg) = 0; 913 virtual void CompilerInitializeRegAlloc() = 0; 914 915 // Required for target - miscellaneous. 916 virtual void AssembleLIR() = 0; 917 virtual void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix) = 0; 918 virtual void SetupTargetResourceMasks(LIR* lir, uint64_t flags) = 0; 919 virtual const char* GetTargetInstFmt(int opcode) = 0; 920 virtual const char* GetTargetInstName(int opcode) = 0; 921 virtual std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) = 0; 922 virtual uint64_t GetPCUseDefEncoding() = 0; 923 virtual uint64_t GetTargetInstFlags(int opcode) = 0; 924 virtual int GetInsnSize(LIR* lir) = 0; 925 virtual bool IsUnconditionalBranch(LIR* lir) = 0; 926 927 // Required for target - Dalvik-level generators. 928 virtual void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 929 RegLocation rl_src1, RegLocation rl_src2) = 0; 930 virtual void GenMulLong(Instruction::Code, 931 RegLocation rl_dest, RegLocation rl_src1, 932 RegLocation rl_src2) = 0; 933 virtual void GenAddLong(Instruction::Code, 934 RegLocation rl_dest, RegLocation rl_src1, 935 RegLocation rl_src2) = 0; 936 virtual void GenAndLong(Instruction::Code, 937 RegLocation rl_dest, RegLocation rl_src1, 938 RegLocation rl_src2) = 0; 939 virtual void GenArithOpDouble(Instruction::Code opcode, 940 RegLocation rl_dest, RegLocation rl_src1, 941 RegLocation rl_src2) = 0; 942 virtual void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 943 RegLocation rl_src1, RegLocation rl_src2) = 0; 944 virtual void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, 945 RegLocation rl_src1, RegLocation rl_src2) = 0; 946 virtual void GenConversion(Instruction::Code opcode, RegLocation rl_dest, 947 RegLocation rl_src) = 0; 948 virtual bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) = 0; 949 950 /** 951 * @brief Used to generate code for intrinsic java\.lang\.Math methods min and max. 952 * @details This is also applicable for java\.lang\.StrictMath since it is a simple algorithm 953 * that applies on integers. The generated code will write the smallest or largest value 954 * directly into the destination register as specified by the invoke information. 955 * @param info Information about the invoke. 956 * @param is_min If true generates code that computes minimum. Otherwise computes maximum. 957 * @return Returns true if successfully generated 958 */ 959 virtual bool GenInlinedMinMaxInt(CallInfo* info, bool is_min) = 0; 960 961 virtual bool GenInlinedSqrt(CallInfo* info) = 0; 962 virtual bool GenInlinedPeek(CallInfo* info, OpSize size) = 0; 963 virtual bool GenInlinedPoke(CallInfo* info, OpSize size) = 0; 964 virtual void GenNegLong(RegLocation rl_dest, RegLocation rl_src) = 0; 965 virtual void GenOrLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 966 RegLocation rl_src2) = 0; 967 virtual void GenSubLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 968 RegLocation rl_src2) = 0; 969 virtual void GenXorLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 970 RegLocation rl_src2) = 0; 971 virtual RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 972 bool is_div) = 0; 973 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, 974 bool is_div) = 0; 975 /* 976 * @brief Generate an integer div or rem operation by a literal. 977 * @param rl_dest Destination Location. 978 * @param rl_src1 Numerator Location. 979 * @param rl_src2 Divisor Location. 980 * @param is_div 'true' if this is a division, 'false' for a remainder. 981 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 982 */ 983 virtual RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 984 RegLocation rl_src2, bool is_div, bool check_zero) = 0; 985 /* 986 * @brief Generate an integer div or rem operation by a literal. 987 * @param rl_dest Destination Location. 988 * @param rl_src Numerator Location. 989 * @param lit Divisor. 990 * @param is_div 'true' if this is a division, 'false' for a remainder. 991 */ 992 virtual RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, 993 bool is_div) = 0; 994 virtual void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) = 0; 995 996 /** 997 * @brief Used for generating code that throws ArithmeticException if both registers are zero. 998 * @details This is used for generating DivideByZero checks when divisor is held in two 999 * separate registers. 1000 * @param reg The register holding the pair of 32-bit values. 1001 */ 1002 virtual void GenDivZeroCheckWide(RegStorage reg) = 0; 1003 1004 virtual void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) = 0; 1005 virtual void GenExitSequence() = 0; 1006 virtual void GenFillArrayData(DexOffset table_offset, RegLocation rl_src) = 0; 1007 virtual void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) = 0; 1008 virtual void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) = 0; 1009 1010 /** 1011 * @brief Lowers the kMirOpSelect MIR into LIR. 1012 * @param bb The basic block in which the MIR is from. 1013 * @param mir The MIR whose opcode is kMirOpSelect. 1014 */ 1015 virtual void GenSelect(BasicBlock* bb, MIR* mir) = 0; 1016 1017 /** 1018 * @brief Used to generate a memory barrier in an architecture specific way. 1019 * @details The last generated LIR will be considered for use as barrier. Namely, 1020 * if the last LIR can be updated in a way where it will serve the semantics of 1021 * barrier, then it will be used as such. Otherwise, a new LIR will be generated 1022 * that can keep the semantics. 1023 * @param barrier_kind The kind of memory barrier to generate. 1024 */ 1025 virtual void GenMemBarrier(MemBarrierKind barrier_kind) = 0; 1026 1027 virtual void GenMoveException(RegLocation rl_dest) = 0; 1028 virtual void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 1029 int first_bit, int second_bit) = 0; 1030 virtual void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) = 0; 1031 virtual void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) = 0; 1032 virtual void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1033 virtual void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) = 0; 1034 virtual void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1035 RegLocation rl_index, RegLocation rl_dest, int scale) = 0; 1036 virtual void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1037 RegLocation rl_index, RegLocation rl_src, int scale, 1038 bool card_mark) = 0; 1039 virtual void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1040 RegLocation rl_src1, RegLocation rl_shift) = 0; 1041 1042 // Required for target - single operation generators. 1043 virtual LIR* OpUnconditionalBranch(LIR* target) = 0; 1044 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0; 1045 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, 1046 LIR* target) = 0; 1047 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0; 1048 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0; 1049 virtual LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1050 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0; 1051 virtual void OpEndIT(LIR* it) = 0; 1052 virtual LIR* OpMem(OpKind op, RegStorage r_base, int disp) = 0; 1053 virtual LIR* OpPcRelLoad(RegStorage reg, LIR* target) = 0; 1054 virtual LIR* OpReg(OpKind op, RegStorage r_dest_src) = 0; 1055 virtual void OpRegCopy(RegStorage r_dest, RegStorage r_src) = 0; 1056 virtual LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) = 0; 1057 virtual LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) = 0; 1058 virtual LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) = 0; 1059 virtual LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) = 0; 1060 1061 /** 1062 * @brief Used to generate an LIR that does a load from mem to reg. 1063 * @param r_dest The destination physical register. 1064 * @param r_base The base physical register for memory operand. 1065 * @param offset The displacement for memory operand. 1066 * @param move_type Specification on the move desired (size, alignment, register kind). 1067 * @return Returns the generate move LIR. 1068 */ 1069 virtual LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, 1070 MoveType move_type) = 0; 1071 1072 /** 1073 * @brief Used to generate an LIR that does a store from reg to mem. 1074 * @param r_base The base physical register for memory operand. 1075 * @param offset The displacement for memory operand. 1076 * @param r_src The destination physical register. 1077 * @param bytes_to_move The number of bytes to move. 1078 * @param is_aligned Whether the memory location is known to be aligned. 1079 * @return Returns the generate move LIR. 1080 */ 1081 virtual LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, 1082 MoveType move_type) = 0; 1083 1084 /** 1085 * @brief Used for generating a conditional register to register operation. 1086 * @param op The opcode kind. 1087 * @param cc The condition code that when true will perform the opcode. 1088 * @param r_dest The destination physical register. 1089 * @param r_src The source physical register. 1090 * @return Returns the newly created LIR or null in case of creation failure. 1091 */ 1092 virtual LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) = 0; 1093 1094 virtual LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) = 0; 1095 virtual LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 1096 RegStorage r_src2) = 0; 1097 virtual LIR* OpTestSuspend(LIR* target) = 0; 1098 virtual LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) = 0; 1099 virtual LIR* OpVldm(RegStorage r_base, int count) = 0; 1100 virtual LIR* OpVstm(RegStorage r_base, int count) = 0; 1101 virtual void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, 1102 int offset) = 0; 1103 virtual void OpRegCopyWide(RegStorage dest, RegStorage src) = 0; 1104 virtual void OpTlsCmp(ThreadOffset<4> offset, int val) = 0; 1105 virtual bool InexpensiveConstantInt(int32_t value) = 0; 1106 virtual bool InexpensiveConstantFloat(int32_t value) = 0; 1107 virtual bool InexpensiveConstantLong(int64_t value) = 0; 1108 virtual bool InexpensiveConstantDouble(int64_t value) = 0; 1109 1110 // May be optimized by targets. 1111 virtual void GenMonitorEnter(int opt_flags, RegLocation rl_src); 1112 virtual void GenMonitorExit(int opt_flags, RegLocation rl_src); 1113 1114 // Temp workaround 1115 void Workaround7250540(RegLocation rl_dest, RegStorage zero_reg); 1116 1117 protected: 1118 Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 1119 1120 CompilationUnit* GetCompilationUnit() { 1121 return cu_; 1122 } 1123 /* 1124 * @brief Returns the index of the lowest set bit in 'x'. 1125 * @param x Value to be examined. 1126 * @returns The bit number of the lowest bit set in the value. 1127 */ 1128 int32_t LowestSetBit(uint64_t x); 1129 /* 1130 * @brief Is this value a power of two? 1131 * @param x Value to be examined. 1132 * @returns 'true' if only 1 bit is set in the value. 1133 */ 1134 bool IsPowerOfTwo(uint64_t x); 1135 /* 1136 * @brief Do these SRs overlap? 1137 * @param rl_op1 One RegLocation 1138 * @param rl_op2 The other RegLocation 1139 * @return 'true' if the VR pairs overlap 1140 * 1141 * Check to see if a result pair has a misaligned overlap with an operand pair. This 1142 * is not usual for dx to generate, but it is legal (for now). In a future rev of 1143 * dex, we'll want to make this case illegal. 1144 */ 1145 bool BadOverlap(RegLocation rl_op1, RegLocation rl_op2); 1146 1147 /* 1148 * @brief Force a location (in a register) into a temporary register 1149 * @param loc location of result 1150 * @returns update location 1151 */ 1152 RegLocation ForceTemp(RegLocation loc); 1153 1154 /* 1155 * @brief Force a wide location (in registers) into temporary registers 1156 * @param loc location of result 1157 * @returns update location 1158 */ 1159 RegLocation ForceTempWide(RegLocation loc); 1160 1161 virtual void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1162 RegLocation rl_dest, RegLocation rl_src); 1163 1164 void AddSlowPath(LIRSlowPath* slowpath); 1165 1166 virtual void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1167 bool type_known_abstract, bool use_declaring_class, 1168 bool can_assume_type_is_in_dex_cache, 1169 uint32_t type_idx, RegLocation rl_dest, 1170 RegLocation rl_src); 1171 /* 1172 * @brief Generate the debug_frame FDE information if possible. 1173 * @returns pointer to vector containg CFE information, or NULL. 1174 */ 1175 virtual std::vector<uint8_t>* ReturnCallFrameInformation(); 1176 1177 /** 1178 * @brief Used to insert marker that can be used to associate MIR with LIR. 1179 * @details Only inserts marker if verbosity is enabled. 1180 * @param mir The mir that is currently being generated. 1181 */ 1182 void GenPrintLabel(MIR* mir); 1183 1184 /** 1185 * @brief Used to generate return sequence when there is no frame. 1186 * @details Assumes that the return registers have already been populated. 1187 */ 1188 virtual void GenSpecialExitSequence() = 0; 1189 1190 /** 1191 * @brief Used to generate code for special methods that are known to be 1192 * small enough to work in frameless mode. 1193 * @param bb The basic block of the first MIR. 1194 * @param mir The first MIR of the special method. 1195 * @param special Information about the special method. 1196 * @return Returns whether or not this was handled successfully. Returns false 1197 * if caller should punt to normal MIR2LIR conversion. 1198 */ 1199 virtual bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); 1200 1201 private: 1202 void ClobberBody(RegisterInfo* p); 1203 void ResetDefBody(RegisterInfo* p) { 1204 p->def_start = NULL; 1205 p->def_end = NULL; 1206 } 1207 1208 void SetCurrentDexPc(DexOffset dexpc) { 1209 current_dalvik_offset_ = dexpc; 1210 } 1211 1212 /** 1213 * @brief Used to lock register if argument at in_position was passed that way. 1214 * @details Does nothing if the argument is passed via stack. 1215 * @param in_position The argument number whose register to lock. 1216 * @param wide Whether the argument is wide. 1217 */ 1218 void LockArg(int in_position, bool wide = false); 1219 1220 /** 1221 * @brief Used to load VR argument to a physical register. 1222 * @details The load is only done if the argument is not already in physical register. 1223 * LockArg must have been previously called. 1224 * @param in_position The argument number to load. 1225 * @param wide Whether the argument is 64-bit or not. 1226 * @return Returns the register (or register pair) for the loaded argument. 1227 */ 1228 RegStorage LoadArg(int in_position, bool wide = false); 1229 1230 /** 1231 * @brief Used to load a VR argument directly to a specified register location. 1232 * @param in_position The argument number to place in register. 1233 * @param rl_dest The register location where to place argument. 1234 */ 1235 void LoadArgDirect(int in_position, RegLocation rl_dest); 1236 1237 /** 1238 * @brief Used to generate LIR for special getter method. 1239 * @param mir The mir that represents the iget. 1240 * @param special Information about the special getter method. 1241 * @return Returns whether LIR was successfully generated. 1242 */ 1243 bool GenSpecialIGet(MIR* mir, const InlineMethod& special); 1244 1245 /** 1246 * @brief Used to generate LIR for special setter method. 1247 * @param mir The mir that represents the iput. 1248 * @param special Information about the special setter method. 1249 * @return Returns whether LIR was successfully generated. 1250 */ 1251 bool GenSpecialIPut(MIR* mir, const InlineMethod& special); 1252 1253 /** 1254 * @brief Used to generate LIR for special return-args method. 1255 * @param mir The mir that represents the return of argument. 1256 * @param special Information about the special return-args method. 1257 * @return Returns whether LIR was successfully generated. 1258 */ 1259 bool GenSpecialIdentity(MIR* mir, const InlineMethod& special); 1260 1261 void AddDivZeroCheckSlowPath(LIR* branch); 1262 1263 // Copy arg0 and arg1 to kArg0 and kArg1 safely, possibly using 1264 // kArg2 as temp. 1265 void CopyToArgumentRegs(RegStorage arg0, RegStorage arg1); 1266 1267 public: 1268 // TODO: add accessors for these. 1269 LIR* literal_list_; // Constants. 1270 LIR* method_literal_list_; // Method literals requiring patching. 1271 LIR* class_literal_list_; // Class literals requiring patching. 1272 LIR* code_literal_list_; // Code literals requiring patching. 1273 LIR* first_fixup_; // Doubly-linked list of LIR nodes requiring fixups. 1274 1275 protected: 1276 CompilationUnit* const cu_; 1277 MIRGraph* const mir_graph_; 1278 GrowableArray<SwitchTable*> switch_tables_; 1279 GrowableArray<FillArrayData*> fill_array_data_; 1280 GrowableArray<LIR*> suspend_launchpads_; 1281 GrowableArray<RegisterInfo*> tempreg_info_; 1282 GrowableArray<RegisterInfo*> reginfo_map_; 1283 GrowableArray<void*> pointer_storage_; 1284 CodeOffset current_code_offset_; // Working byte offset of machine instructons. 1285 CodeOffset data_offset_; // starting offset of literal pool. 1286 size_t total_size_; // header + code size. 1287 LIR* block_label_list_; 1288 PromotionMap* promotion_map_; 1289 /* 1290 * TODO: The code generation utilities don't have a built-in 1291 * mechanism to propagate the original Dalvik opcode address to the 1292 * associated generated instructions. For the trace compiler, this wasn't 1293 * necessary because the interpreter handled all throws and debugging 1294 * requests. For now we'll handle this by placing the Dalvik offset 1295 * in the CompilationUnit struct before codegen for each instruction. 1296 * The low-level LIR creation utilites will pull it from here. Rework this. 1297 */ 1298 DexOffset current_dalvik_offset_; 1299 size_t estimated_native_code_size_; // Just an estimate; used to reserve code_buffer_ size. 1300 RegisterPool* reg_pool_; 1301 /* 1302 * Sanity checking for the register temp tracking. The same ssa 1303 * name should never be associated with one temp register per 1304 * instruction compilation. 1305 */ 1306 int live_sreg_; 1307 CodeBuffer code_buffer_; 1308 // The encoding mapping table data (dex -> pc offset and pc offset -> dex) with a size prefix. 1309 std::vector<uint8_t> encoded_mapping_table_; 1310 std::vector<uint32_t> core_vmap_table_; 1311 std::vector<uint32_t> fp_vmap_table_; 1312 std::vector<uint8_t> native_gc_map_; 1313 int num_core_spills_; 1314 int num_fp_spills_; 1315 int frame_size_; 1316 unsigned int core_spill_mask_; 1317 unsigned int fp_spill_mask_; 1318 LIR* first_lir_insn_; 1319 LIR* last_lir_insn_; 1320 1321 GrowableArray<LIRSlowPath*> slow_paths_; 1322}; // Class Mir2Lir 1323 1324} // namespace art 1325 1326#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ 1327