ralloc_util.cc revision 7940e44f4517de5e2634a7e07d58d0fb26160513
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains register alloction support. */ 18 19#include "dex/compiler_ir.h" 20#include "dex/compiler_internals.h" 21#include "mir_to_lir-inl.h" 22 23namespace art { 24 25/* 26 * Free all allocated temps in the temp pools. Note that this does 27 * not affect the "liveness" of a temp register, which will stay 28 * live until it is either explicitly killed or reallocated. 29 */ 30void Mir2Lir::ResetRegPool() 31{ 32 int i; 33 for (i=0; i < reg_pool_->num_core_regs; i++) { 34 if (reg_pool_->core_regs[i].is_temp) 35 reg_pool_->core_regs[i].in_use = false; 36 } 37 for (i=0; i < reg_pool_->num_fp_regs; i++) { 38 if (reg_pool_->FPRegs[i].is_temp) 39 reg_pool_->FPRegs[i].in_use = false; 40 } 41 // Reset temp tracking sanity check. 42 if (kIsDebugBuild) { 43 live_sreg_ = INVALID_SREG; 44 } 45} 46 47 /* 48 * Set up temp & preserved register pools specialized by target. 49 * Note: num_regs may be zero. 50 */ 51void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) 52{ 53 int i; 54 for (i=0; i < num; i++) { 55 regs[i].reg = reg_nums[i]; 56 regs[i].in_use = false; 57 regs[i].is_temp = false; 58 regs[i].pair = false; 59 regs[i].live = false; 60 regs[i].dirty = false; 61 regs[i].s_reg = INVALID_SREG; 62 } 63} 64 65void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs) 66{ 67 LOG(INFO) << "================================================"; 68 for (int i = 0; i < num_regs; i++) { 69 LOG(INFO) << StringPrintf( 70 "R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d, ST:%x, EN:%x", 71 p[i].reg, p[i].is_temp, p[i].in_use, p[i].pair, p[i].partner, 72 p[i].live, p[i].dirty, p[i].s_reg, reinterpret_cast<uintptr_t>(p[i].def_start), 73 reinterpret_cast<uintptr_t>(p[i].def_end)); 74 } 75 LOG(INFO) << "================================================"; 76} 77 78void Mir2Lir::DumpCoreRegPool() 79{ 80 DumpRegPool(reg_pool_->core_regs, reg_pool_->num_core_regs); 81} 82 83void Mir2Lir::DumpFpRegPool() 84{ 85 DumpRegPool(reg_pool_->FPRegs, reg_pool_->num_fp_regs); 86} 87 88void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) 89{ 90 int i; 91 for (i=0; i< num_regs; i++) { 92 if (p[i].s_reg == s_reg) { 93 if (p[i].is_temp) { 94 p[i].live = false; 95 } 96 p[i].def_start = NULL; 97 p[i].def_end = NULL; 98 } 99 } 100} 101 102/* 103 * Break the association between a Dalvik vreg and a physical temp register of either register 104 * class. 105 * TODO: Ideally, the public version of this code should not exist. Besides its local usage 106 * in the register utilities, is is also used by code gen routines to work around a deficiency in 107 * local register allocation, which fails to distinguish between the "in" and "out" identities 108 * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg 109 * is used both as the source and destination register of an operation in which the type 110 * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is 111 * addressed. 112 */ 113void Mir2Lir::ClobberSReg(int s_reg) 114{ 115 /* Reset live temp tracking sanity checker */ 116 if (kIsDebugBuild) { 117 if (s_reg == live_sreg_) { 118 live_sreg_ = INVALID_SREG; 119 } 120 } 121 ClobberSRegBody(reg_pool_->core_regs, reg_pool_->num_core_regs, s_reg); 122 ClobberSRegBody(reg_pool_->FPRegs, reg_pool_->num_fp_regs, s_reg); 123} 124 125/* 126 * SSA names associated with the initial definitions of Dalvik 127 * registers are the same as the Dalvik register number (and 128 * thus take the same position in the promotion_map. However, 129 * the special Method* and compiler temp resisters use negative 130 * v_reg numbers to distinguish them and can have an arbitrary 131 * ssa name (above the last original Dalvik register). This function 132 * maps SSA names to positions in the promotion_map array. 133 */ 134int Mir2Lir::SRegToPMap(int s_reg) 135{ 136 DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); 137 DCHECK_GE(s_reg, 0); 138 int v_reg = mir_graph_->SRegToVReg(s_reg); 139 if (v_reg >= 0) { 140 DCHECK_LT(v_reg, cu_->num_dalvik_registers); 141 return v_reg; 142 } else { 143 int pos = std::abs(v_reg) - std::abs(SSA_METHOD_BASEREG); 144 DCHECK_LE(pos, cu_->num_compiler_temps); 145 return cu_->num_dalvik_registers + pos; 146 } 147} 148 149void Mir2Lir::RecordCorePromotion(int reg, int s_reg) 150{ 151 int p_map_idx = SRegToPMap(s_reg); 152 int v_reg = mir_graph_->SRegToVReg(s_reg); 153 GetRegInfo(reg)->in_use = true; 154 core_spill_mask_ |= (1 << reg); 155 // Include reg for later sort 156 core_vmap_table_.push_back(reg << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); 157 num_core_spills_++; 158 promotion_map_[p_map_idx].core_location = kLocPhysReg; 159 promotion_map_[p_map_idx].core_reg = reg; 160} 161 162/* Reserve a callee-save register. Return -1 if none available */ 163int Mir2Lir::AllocPreservedCoreReg(int s_reg) 164{ 165 int res = -1; 166 RegisterInfo* core_regs = reg_pool_->core_regs; 167 for (int i = 0; i < reg_pool_->num_core_regs; i++) { 168 if (!core_regs[i].is_temp && !core_regs[i].in_use) { 169 res = core_regs[i].reg; 170 RecordCorePromotion(res, s_reg); 171 break; 172 } 173 } 174 return res; 175} 176 177void Mir2Lir::RecordFpPromotion(int reg, int s_reg) 178{ 179 int p_map_idx = SRegToPMap(s_reg); 180 int v_reg = mir_graph_->SRegToVReg(s_reg); 181 GetRegInfo(reg)->in_use = true; 182 MarkPreservedSingle(v_reg, reg); 183 promotion_map_[p_map_idx].fp_location = kLocPhysReg; 184 promotion_map_[p_map_idx].FpReg = reg; 185} 186 187/* 188 * Reserve a callee-save fp single register. Try to fullfill request for 189 * even/odd allocation, but go ahead and allocate anything if not 190 * available. If nothing's available, return -1. 191 */ 192int Mir2Lir::AllocPreservedSingle(int s_reg, bool even) 193{ 194 int res = -1; 195 RegisterInfo* FPRegs = reg_pool_->FPRegs; 196 for (int i = 0; i < reg_pool_->num_fp_regs; i++) { 197 if (!FPRegs[i].is_temp && !FPRegs[i].in_use && 198 ((FPRegs[i].reg & 0x1) == 0) == even) { 199 res = FPRegs[i].reg; 200 RecordFpPromotion(res, s_reg); 201 break; 202 } 203 } 204 return res; 205} 206 207/* 208 * Somewhat messy code here. We want to allocate a pair of contiguous 209 * physical single-precision floating point registers starting with 210 * an even numbered reg. It is possible that the paired s_reg (s_reg+1) 211 * has already been allocated - try to fit if possible. Fail to 212 * allocate if we can't meet the requirements for the pair of 213 * s_reg<=sX[even] & (s_reg+1)<= sX+1. 214 */ 215int Mir2Lir::AllocPreservedDouble(int s_reg) 216{ 217 int res = -1; // Assume failure 218 int v_reg = mir_graph_->SRegToVReg(s_reg); 219 int p_map_idx = SRegToPMap(s_reg); 220 if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { 221 // Upper reg is already allocated. Can we fit? 222 int high_reg = promotion_map_[p_map_idx+1].FpReg; 223 if ((high_reg & 1) == 0) { 224 // High reg is even - fail. 225 return res; 226 } 227 // Is the low reg of the pair free? 228 RegisterInfo* p = GetRegInfo(high_reg-1); 229 if (p->in_use || p->is_temp) { 230 // Already allocated or not preserved - fail. 231 return res; 232 } 233 // OK - good to go. 234 res = p->reg; 235 p->in_use = true; 236 DCHECK_EQ((res & 1), 0); 237 MarkPreservedSingle(v_reg, res); 238 } else { 239 RegisterInfo* FPRegs = reg_pool_->FPRegs; 240 for (int i = 0; i < reg_pool_->num_fp_regs; i++) { 241 if (!FPRegs[i].is_temp && !FPRegs[i].in_use && 242 ((FPRegs[i].reg & 0x1) == 0x0) && 243 !FPRegs[i+1].is_temp && !FPRegs[i+1].in_use && 244 ((FPRegs[i+1].reg & 0x1) == 0x1) && 245 (FPRegs[i].reg + 1) == FPRegs[i+1].reg) { 246 res = FPRegs[i].reg; 247 FPRegs[i].in_use = true; 248 MarkPreservedSingle(v_reg, res); 249 FPRegs[i+1].in_use = true; 250 DCHECK_EQ(res + 1, FPRegs[i+1].reg); 251 MarkPreservedSingle(v_reg+1, res+1); 252 break; 253 } 254 } 255 } 256 if (res != -1) { 257 promotion_map_[p_map_idx].fp_location = kLocPhysReg; 258 promotion_map_[p_map_idx].FpReg = res; 259 promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; 260 promotion_map_[p_map_idx+1].FpReg = res + 1; 261 } 262 return res; 263} 264 265 266/* 267 * Reserve a callee-save fp register. If this register can be used 268 * as the first of a double, attempt to allocate an even pair of fp 269 * single regs (but if can't still attempt to allocate a single, preferring 270 * first to allocate an odd register. 271 */ 272int Mir2Lir::AllocPreservedFPReg(int s_reg, bool double_start) 273{ 274 int res = -1; 275 if (double_start) { 276 res = AllocPreservedDouble(s_reg); 277 } 278 if (res == -1) { 279 res = AllocPreservedSingle(s_reg, false /* try odd # */); 280 } 281 if (res == -1) 282 res = AllocPreservedSingle(s_reg, true /* try even # */); 283 return res; 284} 285 286int Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, 287 bool required) 288{ 289 int i; 290 int next = *next_temp; 291 for (i=0; i< num_regs; i++) { 292 if (next >= num_regs) 293 next = 0; 294 if (p[next].is_temp && !p[next].in_use && !p[next].live) { 295 Clobber(p[next].reg); 296 p[next].in_use = true; 297 p[next].pair = false; 298 *next_temp = next + 1; 299 return p[next].reg; 300 } 301 next++; 302 } 303 next = *next_temp; 304 for (i=0; i< num_regs; i++) { 305 if (next >= num_regs) 306 next = 0; 307 if (p[next].is_temp && !p[next].in_use) { 308 Clobber(p[next].reg); 309 p[next].in_use = true; 310 p[next].pair = false; 311 *next_temp = next + 1; 312 return p[next].reg; 313 } 314 next++; 315 } 316 if (required) { 317 CodegenDump(); 318 DumpRegPool(reg_pool_->core_regs, 319 reg_pool_->num_core_regs); 320 LOG(FATAL) << "No free temp registers"; 321 } 322 return -1; // No register available 323} 324 325//REDO: too many assumptions. 326int Mir2Lir::AllocTempDouble() 327{ 328 RegisterInfo* p = reg_pool_->FPRegs; 329 int num_regs = reg_pool_->num_fp_regs; 330 /* Start looking at an even reg */ 331 int next = reg_pool_->next_fp_reg & ~0x1; 332 333 // First try to avoid allocating live registers 334 for (int i=0; i < num_regs; i+=2) { 335 if (next >= num_regs) 336 next = 0; 337 if ((p[next].is_temp && !p[next].in_use && !p[next].live) && 338 (p[next+1].is_temp && !p[next+1].in_use && !p[next+1].live)) { 339 Clobber(p[next].reg); 340 Clobber(p[next+1].reg); 341 p[next].in_use = true; 342 p[next+1].in_use = true; 343 DCHECK_EQ((p[next].reg+1), p[next+1].reg); 344 DCHECK_EQ((p[next].reg & 0x1), 0); 345 reg_pool_->next_fp_reg = next + 2; 346 if (reg_pool_->next_fp_reg >= num_regs) { 347 reg_pool_->next_fp_reg = 0; 348 } 349 return p[next].reg; 350 } 351 next += 2; 352 } 353 next = reg_pool_->next_fp_reg & ~0x1; 354 355 // No choice - find a pair and kill it. 356 for (int i=0; i < num_regs; i+=2) { 357 if (next >= num_regs) 358 next = 0; 359 if (p[next].is_temp && !p[next].in_use && p[next+1].is_temp && 360 !p[next+1].in_use) { 361 Clobber(p[next].reg); 362 Clobber(p[next+1].reg); 363 p[next].in_use = true; 364 p[next+1].in_use = true; 365 DCHECK_EQ((p[next].reg+1), p[next+1].reg); 366 DCHECK_EQ((p[next].reg & 0x1), 0); 367 reg_pool_->next_fp_reg = next + 2; 368 if (reg_pool_->next_fp_reg >= num_regs) { 369 reg_pool_->next_fp_reg = 0; 370 } 371 return p[next].reg; 372 } 373 next += 2; 374 } 375 LOG(FATAL) << "No free temp registers (pair)"; 376 return -1; 377} 378 379/* Return a temp if one is available, -1 otherwise */ 380int Mir2Lir::AllocFreeTemp() 381{ 382 return AllocTempBody(reg_pool_->core_regs, 383 reg_pool_->num_core_regs, 384 ®_pool_->next_core_reg, true); 385} 386 387int Mir2Lir::AllocTemp() 388{ 389 return AllocTempBody(reg_pool_->core_regs, 390 reg_pool_->num_core_regs, 391 ®_pool_->next_core_reg, true); 392} 393 394int Mir2Lir::AllocTempFloat() 395{ 396 return AllocTempBody(reg_pool_->FPRegs, 397 reg_pool_->num_fp_regs, 398 ®_pool_->next_fp_reg, true); 399} 400 401Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) 402{ 403 int i; 404 if (s_reg == -1) 405 return NULL; 406 for (i=0; i < num_regs; i++) { 407 if (p[i].live && (p[i].s_reg == s_reg)) { 408 if (p[i].is_temp) 409 p[i].in_use = true; 410 return &p[i]; 411 } 412 } 413 return NULL; 414} 415 416Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class) 417{ 418 RegisterInfo* res = NULL; 419 switch (reg_class) { 420 case kAnyReg: 421 res = AllocLiveBody(reg_pool_->FPRegs, 422 reg_pool_->num_fp_regs, s_reg); 423 if (res) 424 break; 425 /* Intentional fallthrough */ 426 case kCoreReg: 427 res = AllocLiveBody(reg_pool_->core_regs, 428 reg_pool_->num_core_regs, s_reg); 429 break; 430 case kFPReg: 431 res = AllocLiveBody(reg_pool_->FPRegs, 432 reg_pool_->num_fp_regs, s_reg); 433 break; 434 default: 435 LOG(FATAL) << "Invalid register type"; 436 } 437 return res; 438} 439 440void Mir2Lir::FreeTemp(int reg) 441{ 442 RegisterInfo* p = reg_pool_->core_regs; 443 int num_regs = reg_pool_->num_core_regs; 444 int i; 445 for (i=0; i< num_regs; i++) { 446 if (p[i].reg == reg) { 447 if (p[i].is_temp) { 448 p[i].in_use = false; 449 } 450 p[i].pair = false; 451 return; 452 } 453 } 454 p = reg_pool_->FPRegs; 455 num_regs = reg_pool_->num_fp_regs; 456 for (i=0; i< num_regs; i++) { 457 if (p[i].reg == reg) { 458 if (p[i].is_temp) { 459 p[i].in_use = false; 460 } 461 p[i].pair = false; 462 return; 463 } 464 } 465 LOG(FATAL) << "Tried to free a non-existant temp: r" << reg; 466} 467 468Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) 469{ 470 RegisterInfo* p = reg_pool_->core_regs; 471 int num_regs = reg_pool_->num_core_regs; 472 int i; 473 for (i=0; i< num_regs; i++) { 474 if (p[i].reg == reg) { 475 return p[i].live ? &p[i] : NULL; 476 } 477 } 478 p = reg_pool_->FPRegs; 479 num_regs = reg_pool_->num_fp_regs; 480 for (i=0; i< num_regs; i++) { 481 if (p[i].reg == reg) { 482 return p[i].live ? &p[i] : NULL; 483 } 484 } 485 return NULL; 486} 487 488Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg) 489{ 490 RegisterInfo* p = GetRegInfo(reg); 491 return (p->is_temp) ? p : NULL; 492} 493 494Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg) 495{ 496 RegisterInfo* p = GetRegInfo(reg); 497 return (p->is_temp) ? NULL : p; 498} 499 500bool Mir2Lir::IsDirty(int reg) 501{ 502 RegisterInfo* p = GetRegInfo(reg); 503 return p->dirty; 504} 505 506/* 507 * Similar to AllocTemp(), but forces the allocation of a specific 508 * register. No check is made to see if the register was previously 509 * allocated. Use with caution. 510 */ 511void Mir2Lir::LockTemp(int reg) 512{ 513 RegisterInfo* p = reg_pool_->core_regs; 514 int num_regs = reg_pool_->num_core_regs; 515 int i; 516 for (i=0; i< num_regs; i++) { 517 if (p[i].reg == reg) { 518 DCHECK(p[i].is_temp); 519 p[i].in_use = true; 520 p[i].live = false; 521 return; 522 } 523 } 524 p = reg_pool_->FPRegs; 525 num_regs = reg_pool_->num_fp_regs; 526 for (i=0; i< num_regs; i++) { 527 if (p[i].reg == reg) { 528 DCHECK(p[i].is_temp); 529 p[i].in_use = true; 530 p[i].live = false; 531 return; 532 } 533 } 534 LOG(FATAL) << "Tried to lock a non-existant temp: r" << reg; 535} 536 537void Mir2Lir::ResetDef(int reg) 538{ 539 ResetDefBody(GetRegInfo(reg)); 540} 541 542void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2) 543{ 544 if (start && finish) { 545 LIR *p; 546 DCHECK_EQ(s_reg1, s_reg2); 547 for (p = start; ;p = p->next) { 548 NopLIR(p); 549 if (p == finish) 550 break; 551 } 552 } 553} 554 555/* 556 * Mark the beginning and end LIR of a def sequence. Note that 557 * on entry start points to the LIR prior to the beginning of the 558 * sequence. 559 */ 560void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) 561{ 562 DCHECK(!rl.wide); 563 DCHECK(start && start->next); 564 DCHECK(finish); 565 RegisterInfo* p = GetRegInfo(rl.low_reg); 566 p->def_start = start->next; 567 p->def_end = finish; 568} 569 570/* 571 * Mark the beginning and end LIR of a def sequence. Note that 572 * on entry start points to the LIR prior to the beginning of the 573 * sequence. 574 */ 575void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) 576{ 577 DCHECK(rl.wide); 578 DCHECK(start && start->next); 579 DCHECK(finish); 580 RegisterInfo* p = GetRegInfo(rl.low_reg); 581 ResetDef(rl.high_reg); // Only track low of pair 582 p->def_start = start->next; 583 p->def_end = finish; 584} 585 586RegLocation Mir2Lir::WideToNarrow(RegLocation rl) 587{ 588 DCHECK(rl.wide); 589 if (rl.location == kLocPhysReg) { 590 RegisterInfo* info_lo = GetRegInfo(rl.low_reg); 591 RegisterInfo* info_hi = GetRegInfo(rl.high_reg); 592 if (info_lo->is_temp) { 593 info_lo->pair = false; 594 info_lo->def_start = NULL; 595 info_lo->def_end = NULL; 596 } 597 if (info_hi->is_temp) { 598 info_hi->pair = false; 599 info_hi->def_start = NULL; 600 info_hi->def_end = NULL; 601 } 602 } 603 rl.wide = false; 604 return rl; 605} 606 607void Mir2Lir::ResetDefLoc(RegLocation rl) 608{ 609 DCHECK(!rl.wide); 610 RegisterInfo* p = IsTemp(rl.low_reg); 611 if (p && !(cu_->disable_opt & (1 << kSuppressLoads))) { 612 DCHECK(!p->pair); 613 NullifyRange(p->def_start, p->def_end, p->s_reg, rl.s_reg_low); 614 } 615 ResetDef(rl.low_reg); 616} 617 618void Mir2Lir::ResetDefLocWide(RegLocation rl) 619{ 620 DCHECK(rl.wide); 621 RegisterInfo* p_low = IsTemp(rl.low_reg); 622 RegisterInfo* p_high = IsTemp(rl.high_reg); 623 if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { 624 DCHECK(p_low->pair); 625 NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); 626 } 627 if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { 628 DCHECK(p_high->pair); 629 } 630 ResetDef(rl.low_reg); 631 ResetDef(rl.high_reg); 632} 633 634void Mir2Lir::ResetDefTracking() 635{ 636 int i; 637 for (i=0; i< reg_pool_->num_core_regs; i++) { 638 ResetDefBody(®_pool_->core_regs[i]); 639 } 640 for (i=0; i< reg_pool_->num_fp_regs; i++) { 641 ResetDefBody(®_pool_->FPRegs[i]); 642 } 643} 644 645void Mir2Lir::ClobberAllRegs() 646{ 647 int i; 648 for (i=0; i< reg_pool_->num_core_regs; i++) { 649 ClobberBody(®_pool_->core_regs[i]); 650 } 651 for (i=0; i< reg_pool_->num_fp_regs; i++) { 652 ClobberBody(®_pool_->FPRegs[i]); 653 } 654} 655 656// Make sure nothing is live and dirty 657void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) 658{ 659 int i; 660 for (i=0; i < num_regs; i++) { 661 if (info[i].live && info[i].dirty) { 662 if (info[i].pair) { 663 FlushRegWide(info[i].reg, info[i].partner); 664 } else { 665 FlushReg(info[i].reg); 666 } 667 } 668 } 669} 670 671void Mir2Lir::FlushAllRegs() 672{ 673 FlushAllRegsBody(reg_pool_->core_regs, 674 reg_pool_->num_core_regs); 675 FlushAllRegsBody(reg_pool_->FPRegs, 676 reg_pool_->num_fp_regs); 677 ClobberAllRegs(); 678} 679 680 681//TUNING: rewrite all of this reg stuff. Probably use an attribute table 682bool Mir2Lir::RegClassMatches(int reg_class, int reg) 683{ 684 if (reg_class == kAnyReg) { 685 return true; 686 } else if (reg_class == kCoreReg) { 687 return !IsFpReg(reg); 688 } else { 689 return IsFpReg(reg); 690 } 691} 692 693void Mir2Lir::MarkLive(int reg, int s_reg) 694{ 695 RegisterInfo* info = GetRegInfo(reg); 696 if ((info->reg == reg) && (info->s_reg == s_reg) && info->live) { 697 return; /* already live */ 698 } else if (s_reg != INVALID_SREG) { 699 ClobberSReg(s_reg); 700 if (info->is_temp) { 701 info->live = true; 702 } 703 } else { 704 /* Can't be live if no associated s_reg */ 705 DCHECK(info->is_temp); 706 info->live = false; 707 } 708 info->s_reg = s_reg; 709} 710 711void Mir2Lir::MarkTemp(int reg) 712{ 713 RegisterInfo* info = GetRegInfo(reg); 714 info->is_temp = true; 715} 716 717void Mir2Lir::UnmarkTemp(int reg) 718{ 719 RegisterInfo* info = GetRegInfo(reg); 720 info->is_temp = false; 721} 722 723void Mir2Lir::MarkPair(int low_reg, int high_reg) 724{ 725 RegisterInfo* info_lo = GetRegInfo(low_reg); 726 RegisterInfo* info_hi = GetRegInfo(high_reg); 727 info_lo->pair = info_hi->pair = true; 728 info_lo->partner = high_reg; 729 info_hi->partner = low_reg; 730} 731 732void Mir2Lir::MarkClean(RegLocation loc) 733{ 734 RegisterInfo* info = GetRegInfo(loc.low_reg); 735 info->dirty = false; 736 if (loc.wide) { 737 info = GetRegInfo(loc.high_reg); 738 info->dirty = false; 739 } 740} 741 742void Mir2Lir::MarkDirty(RegLocation loc) 743{ 744 if (loc.home) { 745 // If already home, can't be dirty 746 return; 747 } 748 RegisterInfo* info = GetRegInfo(loc.low_reg); 749 info->dirty = true; 750 if (loc.wide) { 751 info = GetRegInfo(loc.high_reg); 752 info->dirty = true; 753 } 754} 755 756void Mir2Lir::MarkInUse(int reg) 757{ 758 RegisterInfo* info = GetRegInfo(reg); 759 info->in_use = true; 760} 761 762void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) 763{ 764 RegisterInfo* new_info = GetRegInfo(new_reg); 765 RegisterInfo* old_info = GetRegInfo(old_reg); 766 // Target temp status must not change 767 bool is_temp = new_info->is_temp; 768 *new_info = *old_info; 769 // Restore target's temp status 770 new_info->is_temp = is_temp; 771 new_info->reg = new_reg; 772} 773 774bool Mir2Lir::CheckCorePoolSanity() 775{ 776 for (static int i = 0; i < reg_pool_->num_core_regs; i++) { 777 if (reg_pool_->core_regs[i].pair) { 778 static int my_reg = reg_pool_->core_regs[i].reg; 779 static int my_sreg = reg_pool_->core_regs[i].s_reg; 780 static int partner_reg = reg_pool_->core_regs[i].partner; 781 static RegisterInfo* partner = GetRegInfo(partner_reg); 782 DCHECK(partner != NULL); 783 DCHECK(partner->pair); 784 DCHECK_EQ(my_reg, partner->partner); 785 static int partner_sreg = partner->s_reg; 786 if (my_sreg == INVALID_SREG) { 787 DCHECK_EQ(partner_sreg, INVALID_SREG); 788 } else { 789 int diff = my_sreg - partner_sreg; 790 DCHECK((diff == -1) || (diff == 1)); 791 } 792 } 793 if (!reg_pool_->core_regs[i].live) { 794 DCHECK(reg_pool_->core_regs[i].def_start == NULL); 795 DCHECK(reg_pool_->core_regs[i].def_end == NULL); 796 } 797 } 798 return true; 799} 800 801/* 802 * Return an updated location record with current in-register status. 803 * If the value lives in live temps, reflect that fact. No code 804 * is generated. If the live value is part of an older pair, 805 * clobber both low and high. 806 * TUNING: clobbering both is a bit heavy-handed, but the alternative 807 * is a bit complex when dealing with FP regs. Examine code to see 808 * if it's worthwhile trying to be more clever here. 809 */ 810 811RegLocation Mir2Lir::UpdateLoc(RegLocation loc) 812{ 813 DCHECK(!loc.wide); 814 DCHECK(CheckCorePoolSanity()); 815 if (loc.location != kLocPhysReg) { 816 DCHECK((loc.location == kLocDalvikFrame) || 817 (loc.location == kLocCompilerTemp)); 818 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 819 if (info_lo) { 820 if (info_lo->pair) { 821 Clobber(info_lo->reg); 822 Clobber(info_lo->partner); 823 FreeTemp(info_lo->reg); 824 } else { 825 loc.low_reg = info_lo->reg; 826 loc.location = kLocPhysReg; 827 } 828 } 829 } 830 831 return loc; 832} 833 834/* see comments for update_loc */ 835RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) 836{ 837 DCHECK(loc.wide); 838 DCHECK(CheckCorePoolSanity()); 839 if (loc.location != kLocPhysReg) { 840 DCHECK((loc.location == kLocDalvikFrame) || 841 (loc.location == kLocCompilerTemp)); 842 // Are the dalvik regs already live in physical registers? 843 RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); 844 RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); 845 bool match = true; 846 match = match && (info_lo != NULL); 847 match = match && (info_hi != NULL); 848 // Are they both core or both FP? 849 match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); 850 // If a pair of floating point singles, are they properly aligned? 851 if (match && IsFpReg(info_lo->reg)) { 852 match &= ((info_lo->reg & 0x1) == 0); 853 match &= ((info_hi->reg - info_lo->reg) == 1); 854 } 855 // If previously used as a pair, it is the same pair? 856 if (match && (info_lo->pair || info_hi->pair)) { 857 match = (info_lo->pair == info_hi->pair); 858 match &= ((info_lo->reg == info_hi->partner) && 859 (info_hi->reg == info_lo->partner)); 860 } 861 if (match) { 862 // Can reuse - update the register usage info 863 loc.low_reg = info_lo->reg; 864 loc.high_reg = info_hi->reg; 865 loc.location = kLocPhysReg; 866 MarkPair(loc.low_reg, loc.high_reg); 867 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 868 return loc; 869 } 870 // Can't easily reuse - clobber and free any overlaps 871 if (info_lo) { 872 Clobber(info_lo->reg); 873 FreeTemp(info_lo->reg); 874 if (info_lo->pair) 875 Clobber(info_lo->partner); 876 } 877 if (info_hi) { 878 Clobber(info_hi->reg); 879 FreeTemp(info_hi->reg); 880 if (info_hi->pair) 881 Clobber(info_hi->partner); 882 } 883 } 884 return loc; 885} 886 887 888/* For use in cases we don't know (or care) width */ 889RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) 890{ 891 if (loc.wide) 892 return UpdateLocWide(loc); 893 else 894 return UpdateLoc(loc); 895} 896 897RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) 898{ 899 DCHECK(loc.wide); 900 int new_regs; 901 int low_reg; 902 int high_reg; 903 904 loc = UpdateLocWide(loc); 905 906 /* If already in registers, we can assume proper form. Right reg class? */ 907 if (loc.location == kLocPhysReg) { 908 DCHECK_EQ(IsFpReg(loc.low_reg), IsFpReg(loc.high_reg)); 909 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 910 if (!RegClassMatches(reg_class, loc.low_reg)) { 911 /* Wrong register class. Reallocate and copy */ 912 new_regs = AllocTypedTempPair(loc.fp, reg_class); 913 low_reg = new_regs & 0xff; 914 high_reg = (new_regs >> 8) & 0xff; 915 OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg); 916 CopyRegInfo(low_reg, loc.low_reg); 917 CopyRegInfo(high_reg, loc.high_reg); 918 Clobber(loc.low_reg); 919 Clobber(loc.high_reg); 920 loc.low_reg = low_reg; 921 loc.high_reg = high_reg; 922 MarkPair(loc.low_reg, loc.high_reg); 923 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 924 } 925 return loc; 926 } 927 928 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 929 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 930 931 new_regs = AllocTypedTempPair(loc.fp, reg_class); 932 loc.low_reg = new_regs & 0xff; 933 loc.high_reg = (new_regs >> 8) & 0xff; 934 935 MarkPair(loc.low_reg, loc.high_reg); 936 if (update) { 937 loc.location = kLocPhysReg; 938 MarkLive(loc.low_reg, loc.s_reg_low); 939 MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low)); 940 } 941 DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); 942 return loc; 943} 944 945RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) 946{ 947 int new_reg; 948 949 if (loc.wide) 950 return EvalLocWide(loc, reg_class, update); 951 952 loc = UpdateLoc(loc); 953 954 if (loc.location == kLocPhysReg) { 955 if (!RegClassMatches(reg_class, loc.low_reg)) { 956 /* Wrong register class. Realloc, copy and transfer ownership */ 957 new_reg = AllocTypedTemp(loc.fp, reg_class); 958 OpRegCopy(new_reg, loc.low_reg); 959 CopyRegInfo(new_reg, loc.low_reg); 960 Clobber(loc.low_reg); 961 loc.low_reg = new_reg; 962 } 963 return loc; 964 } 965 966 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 967 968 new_reg = AllocTypedTemp(loc.fp, reg_class); 969 loc.low_reg = new_reg; 970 971 if (update) { 972 loc.location = kLocPhysReg; 973 MarkLive(loc.low_reg, loc.s_reg_low); 974 } 975 return loc; 976} 977 978/* USE SSA names to count references of base Dalvik v_regs. */ 979void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts) { 980 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 981 RegLocation loc = mir_graph_->reg_location_[i]; 982 RefCounts* counts = loc.fp ? fp_counts : core_counts; 983 int p_map_idx = SRegToPMap(loc.s_reg_low); 984 //Don't count easily regenerated immediates 985 if (loc.fp || !IsInexpensiveConstant(loc)) { 986 counts[p_map_idx].count += mir_graph_->GetUseCount(i); 987 } 988 if (loc.wide && loc.fp && !loc.high_word) { 989 counts[p_map_idx].double_start = true; 990 } 991 } 992} 993 994/* qsort callback function, sort descending */ 995static int SortCounts(const void *val1, const void *val2) 996{ 997 const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); 998 const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); 999 return (op1->count == op2->count) ? 0 : (op1->count < op2->count ? 1 : -1); 1000} 1001 1002void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) 1003{ 1004 LOG(INFO) << msg; 1005 for (int i = 0; i < size; i++) { 1006 LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; 1007 } 1008} 1009 1010/* 1011 * Note: some portions of this code required even if the kPromoteRegs 1012 * optimization is disabled. 1013 */ 1014void Mir2Lir::DoPromotion() 1015{ 1016 int reg_bias = cu_->num_compiler_temps + 1; 1017 int dalvik_regs = cu_->num_dalvik_registers; 1018 int num_regs = dalvik_regs + reg_bias; 1019 const int promotion_threshold = 1; 1020 1021 // Allow target code to add any special registers 1022 AdjustSpillMask(); 1023 1024 /* 1025 * Simple register promotion. Just do a static count of the uses 1026 * of Dalvik registers. Note that we examine the SSA names, but 1027 * count based on original Dalvik register name. Count refs 1028 * separately based on type in order to give allocation 1029 * preference to fp doubles - which must be allocated sequential 1030 * physical single fp registers started with an even-numbered 1031 * reg. 1032 * TUNING: replace with linear scan once we have the ability 1033 * to describe register live ranges for GC. 1034 */ 1035 RefCounts *core_regs = 1036 static_cast<RefCounts*>(arena_->NewMem(sizeof(RefCounts) * num_regs, true, 1037 ArenaAllocator::kAllocRegAlloc)); 1038 RefCounts *FpRegs = 1039 static_cast<RefCounts *>(arena_->NewMem(sizeof(RefCounts) * num_regs, true, 1040 ArenaAllocator::kAllocRegAlloc)); 1041 // Set ssa names for original Dalvik registers 1042 for (int i = 0; i < dalvik_regs; i++) { 1043 core_regs[i].s_reg = FpRegs[i].s_reg = i; 1044 } 1045 // Set ssa name for Method* 1046 core_regs[dalvik_regs].s_reg = mir_graph_->GetMethodSReg(); 1047 FpRegs[dalvik_regs].s_reg = mir_graph_->GetMethodSReg(); // For consistecy 1048 // Set ssa names for compiler_temps 1049 for (int i = 1; i <= cu_->num_compiler_temps; i++) { 1050 CompilerTemp* ct = mir_graph_->compiler_temps_.Get(i); 1051 core_regs[dalvik_regs + i].s_reg = ct->s_reg; 1052 FpRegs[dalvik_regs + i].s_reg = ct->s_reg; 1053 } 1054 1055 // Sum use counts of SSA regs by original Dalvik vreg. 1056 CountRefs(core_regs, FpRegs); 1057 1058 /* 1059 * Ideally, we'd allocate doubles starting with an even-numbered 1060 * register. Bias the counts to try to allocate any vreg that's 1061 * used as the start of a pair first. 1062 */ 1063 for (int i = 0; i < num_regs; i++) { 1064 if (FpRegs[i].double_start) { 1065 FpRegs[i].count *= 2; 1066 } 1067 } 1068 1069 // Sort the count arrays 1070 qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); 1071 qsort(FpRegs, num_regs, sizeof(RefCounts), SortCounts); 1072 1073 if (cu_->verbose) { 1074 DumpCounts(core_regs, num_regs, "Core regs after sort"); 1075 DumpCounts(FpRegs, num_regs, "Fp regs after sort"); 1076 } 1077 1078 if (!(cu_->disable_opt & (1 << kPromoteRegs))) { 1079 // Promote FpRegs 1080 for (int i = 0; (i < num_regs) && 1081 (FpRegs[i].count >= promotion_threshold ); i++) { 1082 int p_map_idx = SRegToPMap(FpRegs[i].s_reg); 1083 if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { 1084 int reg = AllocPreservedFPReg(FpRegs[i].s_reg, 1085 FpRegs[i].double_start); 1086 if (reg < 0) { 1087 break; // No more left 1088 } 1089 } 1090 } 1091 1092 // Promote core regs 1093 for (int i = 0; (i < num_regs) && 1094 (core_regs[i].count >= promotion_threshold); i++) { 1095 int p_map_idx = SRegToPMap(core_regs[i].s_reg); 1096 if (promotion_map_[p_map_idx].core_location != 1097 kLocPhysReg) { 1098 int reg = AllocPreservedCoreReg(core_regs[i].s_reg); 1099 if (reg < 0) { 1100 break; // No more left 1101 } 1102 } 1103 } 1104 } 1105 1106 // Now, update SSA names to new home locations 1107 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 1108 RegLocation *curr = &mir_graph_->reg_location_[i]; 1109 int p_map_idx = SRegToPMap(curr->s_reg_low); 1110 if (!curr->wide) { 1111 if (curr->fp) { 1112 if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { 1113 curr->location = kLocPhysReg; 1114 curr->low_reg = promotion_map_[p_map_idx].FpReg; 1115 curr->home = true; 1116 } 1117 } else { 1118 if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { 1119 curr->location = kLocPhysReg; 1120 curr->low_reg = promotion_map_[p_map_idx].core_reg; 1121 curr->home = true; 1122 } 1123 } 1124 curr->high_reg = INVALID_REG; 1125 } else { 1126 if (curr->high_word) { 1127 continue; 1128 } 1129 if (curr->fp) { 1130 if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && 1131 (promotion_map_[p_map_idx+1].fp_location == 1132 kLocPhysReg)) { 1133 int low_reg = promotion_map_[p_map_idx].FpReg; 1134 int high_reg = promotion_map_[p_map_idx+1].FpReg; 1135 // Doubles require pair of singles starting at even reg 1136 if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { 1137 curr->location = kLocPhysReg; 1138 curr->low_reg = low_reg; 1139 curr->high_reg = high_reg; 1140 curr->home = true; 1141 } 1142 } 1143 } else { 1144 if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) 1145 && (promotion_map_[p_map_idx+1].core_location == 1146 kLocPhysReg)) { 1147 curr->location = kLocPhysReg; 1148 curr->low_reg = promotion_map_[p_map_idx].core_reg; 1149 curr->high_reg = promotion_map_[p_map_idx+1].core_reg; 1150 curr->home = true; 1151 } 1152 } 1153 } 1154 } 1155 if (cu_->verbose) { 1156 DumpPromotionMap(); 1157 } 1158} 1159 1160/* Returns sp-relative offset in bytes for a VReg */ 1161int Mir2Lir::VRegOffset(int v_reg) 1162{ 1163 return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, 1164 fp_spill_mask_, frame_size_, v_reg); 1165} 1166 1167/* Returns sp-relative offset in bytes for a SReg */ 1168int Mir2Lir::SRegOffset(int s_reg) 1169{ 1170 return VRegOffset(mir_graph_->SRegToVReg(s_reg)); 1171} 1172 1173/* Mark register usage state and return long retloc */ 1174RegLocation Mir2Lir::GetReturnWide(bool is_double) 1175{ 1176 RegLocation gpr_res = LocCReturnWide(); 1177 RegLocation fpr_res = LocCReturnDouble(); 1178 RegLocation res = is_double ? fpr_res : gpr_res; 1179 Clobber(res.low_reg); 1180 Clobber(res.high_reg); 1181 LockTemp(res.low_reg); 1182 LockTemp(res.high_reg); 1183 MarkPair(res.low_reg, res.high_reg); 1184 return res; 1185} 1186 1187RegLocation Mir2Lir::GetReturn(bool is_float) 1188{ 1189 RegLocation gpr_res = LocCReturn(); 1190 RegLocation fpr_res = LocCReturnFloat(); 1191 RegLocation res = is_float ? fpr_res : gpr_res; 1192 Clobber(res.low_reg); 1193 if (cu_->instruction_set == kMips) { 1194 MarkInUse(res.low_reg); 1195 } else { 1196 LockTemp(res.low_reg); 1197 } 1198 return res; 1199} 1200 1201void Mir2Lir::SimpleRegAlloc() 1202{ 1203 DoPromotion(); 1204 1205 if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { 1206 LOG(INFO) << "After Promotion"; 1207 mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); 1208 } 1209 1210 /* Set the frame size */ 1211 frame_size_ = ComputeFrameSize(); 1212} 1213 1214/* 1215 * Get the "real" sreg number associated with an s_reg slot. In general, 1216 * s_reg values passed through codegen are the SSA names created by 1217 * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location 1218 * array. However, renaming is accomplished by simply replacing RegLocation 1219 * entries in the reglocation[] array. Therefore, when location 1220 * records for operands are first created, we need to ask the locRecord 1221 * identified by the dataflow pass what it's new name is. 1222 */ 1223int Mir2Lir::GetSRegHi(int lowSreg) { 1224 return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; 1225} 1226 1227bool Mir2Lir::oat_live_out(int s_reg) { 1228 //For now. 1229 return true; 1230} 1231 1232int Mir2Lir::oatSSASrc(MIR* mir, int num) { 1233 DCHECK_GT(mir->ssa_rep->num_uses, num); 1234 return mir->ssa_rep->uses[num]; 1235} 1236 1237} // namespace art 1238