ralloc_util.cc revision d9f4c52071b305b777c7d7d08176b19882b393d8
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains register alloction support. */ 18 19#include "dex/compiler_ir.h" 20#include "dex/compiler_internals.h" 21#include "mir_to_lir-inl.h" 22 23namespace art { 24 25/* 26 * Free all allocated temps in the temp pools. Note that this does 27 * not affect the "liveness" of a temp register, which will stay 28 * live until it is either explicitly killed or reallocated. 29 */ 30void Mir2Lir::ResetRegPool() { 31 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 32 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 33 info->MarkFree(); 34 } 35 // Reset temp tracking sanity check. 36 if (kIsDebugBuild) { 37 live_sreg_ = INVALID_SREG; 38 } 39} 40 41Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, uint64_t mask) 42 : reg_(r), is_temp_(false), wide_value_(false), dirty_(false), aliased_(false), partner_(r), 43 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr), 44 def_end_(nullptr), alias_chain_(nullptr) { 45 switch (r.StorageSize()) { 46 case 0: storage_mask_ = 0xffffffff; break; 47 case 4: storage_mask_ = 0x00000001; break; 48 case 8: storage_mask_ = 0x00000003; break; 49 case 16: storage_mask_ = 0x0000000f; break; 50 case 32: storage_mask_ = 0x000000ff; break; 51 case 64: storage_mask_ = 0x0000ffff; break; 52 case 128: storage_mask_ = 0xffffffff; break; 53 } 54 used_storage_ = r.Valid() ? ~storage_mask_ : storage_mask_; 55 liveness_ = used_storage_; 56} 57 58Mir2Lir::RegisterPool::RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena, 59 const std::vector<RegStorage>& core_regs, 60 const std::vector<RegStorage>& core64_regs, 61 const std::vector<RegStorage>& sp_regs, 62 const std::vector<RegStorage>& dp_regs, 63 const std::vector<RegStorage>& reserved_regs, 64 const std::vector<RegStorage>& reserved64_regs, 65 const std::vector<RegStorage>& core_temps, 66 const std::vector<RegStorage>& core64_temps, 67 const std::vector<RegStorage>& sp_temps, 68 const std::vector<RegStorage>& dp_temps) : 69 core_regs_(arena, core_regs.size()), next_core_reg_(0), 70 core64_regs_(arena, core64_regs.size()), next_core64_reg_(0), 71 sp_regs_(arena, sp_regs.size()), next_sp_reg_(0), 72 dp_regs_(arena, dp_regs.size()), next_dp_reg_(0), m2l_(m2l) { 73 // Initialize the fast lookup map. 74 m2l_->reginfo_map_.Reset(); 75 if (kIsDebugBuild) { 76 m2l_->reginfo_map_.Resize(RegStorage::kMaxRegs); 77 for (unsigned i = 0; i < RegStorage::kMaxRegs; i++) { 78 m2l_->reginfo_map_.Insert(nullptr); 79 } 80 } else { 81 m2l_->reginfo_map_.SetSize(RegStorage::kMaxRegs); 82 } 83 84 // Construct the register pool. 85 for (RegStorage reg : core_regs) { 86 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 87 m2l_->reginfo_map_.Put(reg.GetReg(), info); 88 core_regs_.Insert(info); 89 } 90 for (RegStorage reg : core64_regs) { 91 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 92 m2l_->reginfo_map_.Put(reg.GetReg(), info); 93 core64_regs_.Insert(info); 94 } 95 for (RegStorage reg : sp_regs) { 96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 97 m2l_->reginfo_map_.Put(reg.GetReg(), info); 98 sp_regs_.Insert(info); 99 } 100 for (RegStorage reg : dp_regs) { 101 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); 102 m2l_->reginfo_map_.Put(reg.GetReg(), info); 103 dp_regs_.Insert(info); 104 } 105 106 // Keep special registers from being allocated. 107 for (RegStorage reg : reserved_regs) { 108 m2l_->MarkInUse(reg); 109 } 110 for (RegStorage reg : reserved64_regs) { 111 m2l_->MarkInUse(reg); 112 } 113 114 // Mark temp regs - all others not in use can be used for promotion 115 for (RegStorage reg : core_temps) { 116 m2l_->MarkTemp(reg); 117 } 118 for (RegStorage reg : core64_temps) { 119 m2l_->MarkTemp(reg); 120 } 121 for (RegStorage reg : sp_temps) { 122 m2l_->MarkTemp(reg); 123 } 124 for (RegStorage reg : dp_temps) { 125 m2l_->MarkTemp(reg); 126 } 127 128 // Add an entry for InvalidReg with zero'd mask. 129 RegisterInfo* invalid_reg = new (arena) RegisterInfo(RegStorage::InvalidReg(), 0); 130 m2l_->reginfo_map_.Put(RegStorage::InvalidReg().GetReg(), invalid_reg); 131} 132 133void Mir2Lir::DumpRegPool(GrowableArray<RegisterInfo*>* regs) { 134 LOG(INFO) << "================================================"; 135 GrowableArray<RegisterInfo*>::Iterator it(regs); 136 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 137 LOG(INFO) << StringPrintf( 138 "R[%d:%d:%c]: T:%d, U:%d, W:%d, p:%d, LV:%d, D:%d, SR:%d, DEF:%d", 139 info->GetReg().GetReg(), info->GetReg().GetRegNum(), info->GetReg().IsFloat() ? 'f' : 'c', 140 info->IsTemp(), info->InUse(), info->IsWide(), info->Partner().GetReg(), info->IsLive(), 141 info->IsDirty(), info->SReg(), info->DefStart() != nullptr); 142 } 143 LOG(INFO) << "================================================"; 144} 145 146void Mir2Lir::DumpCoreRegPool() { 147 DumpRegPool(®_pool_->core_regs_); 148} 149 150void Mir2Lir::DumpFpRegPool() { 151 DumpRegPool(®_pool_->sp_regs_); 152 DumpRegPool(®_pool_->dp_regs_); 153} 154 155void Mir2Lir::DumpRegPools() { 156 LOG(INFO) << "Core registers"; 157 DumpCoreRegPool(); 158 LOG(INFO) << "FP registers"; 159 DumpFpRegPool(); 160} 161 162void Mir2Lir::Clobber(RegStorage reg) { 163 if (UNLIKELY(reg.IsPair())) { 164 DCHECK(!GetRegInfo(reg.GetLow())->IsAliased()); 165 Clobber(reg.GetLow()); 166 DCHECK(!GetRegInfo(reg.GetHigh())->IsAliased()); 167 Clobber(reg.GetHigh()); 168 } else { 169 RegisterInfo* info = GetRegInfo(reg); 170 if (info->IsTemp() && !info->IsDead()) { 171 if (info->GetReg() != info->Partner()) { 172 ClobberBody(GetRegInfo(info->Partner())); 173 } 174 ClobberBody(info); 175 if (info->IsAliased()) { 176 ClobberAliases(info, info->StorageMask()); 177 } else { 178 RegisterInfo* master = info->Master(); 179 if (info != master) { 180 ClobberBody(info->Master()); 181 ClobberAliases(info->Master(), info->StorageMask()); 182 } 183 } 184 } 185 } 186} 187 188void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask) { 189 for (RegisterInfo* alias = info->GetAliasChain(); alias != nullptr; 190 alias = alias->GetAliasChain()) { 191 DCHECK(!alias->IsAliased()); // Only the master should be marked as alised. 192 // Only clobber if we have overlap. 193 if ((alias->StorageMask() & clobber_mask) != 0) { 194 ClobberBody(alias); 195 } 196 } 197} 198 199/* 200 * Break the association between a Dalvik vreg and a physical temp register of either register 201 * class. 202 * TODO: Ideally, the public version of this code should not exist. Besides its local usage 203 * in the register utilities, is is also used by code gen routines to work around a deficiency in 204 * local register allocation, which fails to distinguish between the "in" and "out" identities 205 * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg 206 * is used both as the source and destination register of an operation in which the type 207 * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is 208 * addressed. 209 */ 210void Mir2Lir::ClobberSReg(int s_reg) { 211 if (s_reg != INVALID_SREG) { 212 if (kIsDebugBuild && s_reg == live_sreg_) { 213 live_sreg_ = INVALID_SREG; 214 } 215 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 216 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 217 if (info->SReg() == s_reg) { 218 if (info->GetReg() != info->Partner()) { 219 // Dealing with a pair - clobber the other half. 220 DCHECK(!info->IsAliased()); 221 ClobberBody(GetRegInfo(info->Partner())); 222 } 223 ClobberBody(info); 224 if (info->IsAliased()) { 225 ClobberAliases(info, info->StorageMask()); 226 } 227 } 228 } 229 } 230} 231 232/* 233 * SSA names associated with the initial definitions of Dalvik 234 * registers are the same as the Dalvik register number (and 235 * thus take the same position in the promotion_map. However, 236 * the special Method* and compiler temp resisters use negative 237 * v_reg numbers to distinguish them and can have an arbitrary 238 * ssa name (above the last original Dalvik register). This function 239 * maps SSA names to positions in the promotion_map array. 240 */ 241int Mir2Lir::SRegToPMap(int s_reg) { 242 DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); 243 DCHECK_GE(s_reg, 0); 244 int v_reg = mir_graph_->SRegToVReg(s_reg); 245 if (v_reg >= 0) { 246 DCHECK_LT(v_reg, cu_->num_dalvik_registers); 247 return v_reg; 248 } else { 249 /* 250 * It must be the case that the v_reg for temporary is less than or equal to the 251 * base reg for temps. For that reason, "position" must be zero or positive. 252 */ 253 unsigned int position = std::abs(v_reg) - std::abs(static_cast<int>(kVRegTempBaseReg)); 254 255 // The temporaries are placed after dalvik registers in the promotion map 256 DCHECK_LT(position, mir_graph_->GetNumUsedCompilerTemps()); 257 return cu_->num_dalvik_registers + position; 258 } 259} 260 261// TODO: refactor following Alloc/Record routines - much commonality. 262void Mir2Lir::RecordCorePromotion(RegStorage reg, int s_reg) { 263 int p_map_idx = SRegToPMap(s_reg); 264 int v_reg = mir_graph_->SRegToVReg(s_reg); 265 int reg_num = reg.GetRegNum(); 266 GetRegInfo(reg)->MarkInUse(); 267 core_spill_mask_ |= (1 << reg_num); 268 // Include reg for later sort 269 core_vmap_table_.push_back(reg_num << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); 270 num_core_spills_++; 271 promotion_map_[p_map_idx].core_location = kLocPhysReg; 272 promotion_map_[p_map_idx].core_reg = reg_num; 273} 274 275/* Reserve a callee-save register. Return InvalidReg if none available */ 276RegStorage Mir2Lir::AllocPreservedCoreReg(int s_reg) { 277 RegStorage res; 278 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->core_regs_); 279 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 280 if (!info->IsTemp() && !info->InUse()) { 281 res = info->GetReg(); 282 RecordCorePromotion(res, s_reg); 283 break; 284 } 285 } 286 return res; 287} 288 289void Mir2Lir::RecordSinglePromotion(RegStorage reg, int s_reg) { 290 int p_map_idx = SRegToPMap(s_reg); 291 int v_reg = mir_graph_->SRegToVReg(s_reg); 292 GetRegInfo(reg)->MarkInUse(); 293 MarkPreservedSingle(v_reg, reg); 294 promotion_map_[p_map_idx].fp_location = kLocPhysReg; 295 promotion_map_[p_map_idx].FpReg = reg.GetReg(); 296} 297 298// Reserve a callee-save sp single register. 299RegStorage Mir2Lir::AllocPreservedSingle(int s_reg) { 300 RegStorage res; 301 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); 302 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 303 if (!info->IsTemp() && !info->InUse()) { 304 res = info->GetReg(); 305 RecordSinglePromotion(res, s_reg); 306 break; 307 } 308 } 309 return res; 310} 311 312void Mir2Lir::RecordDoublePromotion(RegStorage reg, int s_reg) { 313 int p_map_idx = SRegToPMap(s_reg); 314 int v_reg = mir_graph_->SRegToVReg(s_reg); 315 GetRegInfo(reg)->MarkInUse(); 316 MarkPreservedDouble(v_reg, reg); 317 promotion_map_[p_map_idx].fp_location = kLocPhysReg; 318 promotion_map_[p_map_idx].FpReg = reg.GetReg(); 319} 320 321// Reserve a callee-save dp solo register. 322RegStorage Mir2Lir::AllocPreservedDouble(int s_reg) { 323 RegStorage res; 324 GrowableArray<RegisterInfo*>::Iterator it(®_pool_->dp_regs_); 325 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 326 if (!info->IsTemp() && !info->InUse()) { 327 res = info->GetReg(); 328 RecordDoublePromotion(res, s_reg); 329 break; 330 } 331 } 332 return res; 333} 334 335 336RegStorage Mir2Lir::AllocTempBody(GrowableArray<RegisterInfo*> ®s, int* next_temp, bool required) { 337 int num_regs = regs.Size(); 338 int next = *next_temp; 339 for (int i = 0; i< num_regs; i++) { 340 if (next >= num_regs) 341 next = 0; 342 RegisterInfo* info = regs.Get(next); 343 // Try to allocate a register that doesn't hold a live value. 344 if (info->IsTemp() && !info->InUse() && info->IsDead()) { 345 Clobber(info->GetReg()); 346 info->MarkInUse(); 347 /* 348 * NOTE: "wideness" is an attribute of how the container is used, not its physical size. 349 * The caller will set wideness as appropriate. 350 */ 351 info->SetIsWide(false); 352 *next_temp = next + 1; 353 return info->GetReg(); 354 } 355 next++; 356 } 357 next = *next_temp; 358 // No free non-live regs. Anything we can kill? 359 for (int i = 0; i< num_regs; i++) { 360 if (next >= num_regs) 361 next = 0; 362 RegisterInfo* info = regs.Get(next); 363 if (info->IsTemp() && !info->InUse()) { 364 // Got one. Kill it. 365 ClobberSReg(info->SReg()); 366 Clobber(info->GetReg()); 367 info->MarkInUse(); 368 if (info->IsWide()) { 369 RegisterInfo* partner = GetRegInfo(info->Partner()); 370 DCHECK_EQ(info->GetReg().GetRegNum(), partner->Partner().GetRegNum()); 371 DCHECK(partner->IsWide()); 372 info->SetIsWide(false); 373 partner->SetIsWide(false); 374 } 375 *next_temp = next + 1; 376 return info->GetReg(); 377 } 378 next++; 379 } 380 if (required) { 381 CodegenDump(); 382 DumpRegPools(); 383 LOG(FATAL) << "No free temp registers"; 384 } 385 return RegStorage::InvalidReg(); // No register available 386} 387 388/* Return a temp if one is available, -1 otherwise */ 389RegStorage Mir2Lir::AllocFreeTemp() { 390 return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, false); 391} 392 393RegStorage Mir2Lir::AllocTemp() { 394 return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, true); 395} 396 397RegStorage Mir2Lir::AllocTempWide() { 398 RegStorage res; 399 if (reg_pool_->core64_regs_.Size() != 0) { 400 res = AllocTempBody(reg_pool_->core64_regs_, ®_pool_->next_core64_reg_, true); 401 } else { 402 RegStorage low_reg = AllocTemp(); 403 RegStorage high_reg = AllocTemp(); 404 res = RegStorage::MakeRegPair(low_reg, high_reg); 405 } 406 return res; 407} 408 409RegStorage Mir2Lir::AllocTempWord() { 410 // FIXME: temporary workaround. For bring-up purposes, x86_64 needs the ability 411 // to allocate wide values as a pair of core registers. However, we can't hold 412 // a reference in a register pair. This workaround will be removed when the 413 // reference handling code is reworked, or x86_64 backend starts using wide core 414 // registers - whichever happens first. 415 if (cu_->instruction_set == kX86_64) { 416 return AllocTemp(); 417 } else { 418 return (Is64BitInstructionSet(cu_->instruction_set)) ? AllocTempWide() : AllocTemp(); 419 } 420} 421 422RegStorage Mir2Lir::AllocTempSingle() { 423 RegStorage res = AllocTempBody(reg_pool_->sp_regs_, ®_pool_->next_sp_reg_, true); 424 DCHECK(res.IsSingle()) << "Reg: 0x" << std::hex << res.GetRawBits(); 425 return res; 426} 427 428RegStorage Mir2Lir::AllocTempDouble() { 429 RegStorage res = AllocTempBody(reg_pool_->dp_regs_, ®_pool_->next_dp_reg_, true); 430 DCHECK(res.IsDouble()) << "Reg: 0x" << std::hex << res.GetRawBits(); 431 return res; 432} 433 434RegStorage Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { 435 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 436 return AllocTempDouble(); 437 } 438 return AllocTempWide(); 439} 440 441RegStorage Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { 442 if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { 443 return AllocTempSingle(); 444 } 445 return AllocTemp(); 446} 447 448RegStorage Mir2Lir::FindLiveReg(GrowableArray<RegisterInfo*> ®s, int s_reg) { 449 RegStorage res; 450 GrowableArray<RegisterInfo*>::Iterator it(®s); 451 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 452 if ((info->SReg() == s_reg) && info->IsLive()) { 453 res = info->GetReg(); 454 break; 455 } 456 } 457 return res; 458} 459 460RegStorage Mir2Lir::AllocLiveReg(int s_reg, int reg_class, bool wide) { 461 RegStorage reg; 462 // TODO: might be worth a sanity check here to verify at most 1 live reg per s_reg. 463 if ((reg_class == kAnyReg) || (reg_class == kFPReg)) { 464 reg = FindLiveReg(wide ? reg_pool_->dp_regs_ : reg_pool_->sp_regs_, s_reg); 465 } 466 if (!reg.Valid() && (reg_class != kFPReg)) { 467 if (Is64BitInstructionSet(cu_->instruction_set)) { 468 reg = FindLiveReg(wide ? reg_pool_->core64_regs_ : reg_pool_->core_regs_, s_reg); 469 } else { 470 reg = FindLiveReg(reg_pool_->core_regs_, s_reg); 471 } 472 } 473 if (reg.Valid()) { 474 if (wide && !reg.IsFloat() && !Is64BitInstructionSet(cu_->instruction_set)) { 475 // Only allow reg pairs for core regs on 32-bit targets. 476 RegStorage high_reg = FindLiveReg(reg_pool_->core_regs_, s_reg + 1); 477 if (high_reg.Valid()) { 478 reg = RegStorage::MakeRegPair(reg, high_reg); 479 MarkWide(reg); 480 } else { 481 // Only half available. 482 reg = RegStorage::InvalidReg(); 483 } 484 } 485 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { 486 // Width mismatch - don't try to reuse. 487 reg = RegStorage::InvalidReg(); 488 } 489 } 490 if (reg.Valid()) { 491 if (reg.IsPair()) { 492 RegisterInfo* info_low = GetRegInfo(reg.GetLow()); 493 RegisterInfo* info_high = GetRegInfo(reg.GetHigh()); 494 if (info_low->IsTemp()) { 495 info_low->MarkInUse(); 496 } 497 if (info_high->IsTemp()) { 498 info_high->MarkInUse(); 499 } 500 } else { 501 RegisterInfo* info = GetRegInfo(reg); 502 if (info->IsTemp()) { 503 info->MarkInUse(); 504 } 505 } 506 } else { 507 // Either not found, or something didn't match up. Clobber to prevent any stale instances. 508 ClobberSReg(s_reg); 509 if (wide) { 510 ClobberSReg(s_reg + 1); 511 } 512 } 513 return reg; 514} 515 516void Mir2Lir::FreeTemp(RegStorage reg) { 517 if (reg.IsPair()) { 518 FreeTemp(reg.GetLow()); 519 FreeTemp(reg.GetHigh()); 520 } else { 521 RegisterInfo* p = GetRegInfo(reg); 522 if (p->IsTemp()) { 523 p->MarkFree(); 524 p->SetIsWide(false); 525 p->SetPartner(reg); 526 } 527 } 528} 529 530void Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { 531 DCHECK(rl_keep.wide); 532 DCHECK(rl_free.wide); 533 int free_low = rl_free.reg.GetLowReg(); 534 int free_high = rl_free.reg.GetHighReg(); 535 int keep_low = rl_keep.reg.GetLowReg(); 536 int keep_high = rl_keep.reg.GetHighReg(); 537 if ((free_low != keep_low) && (free_low != keep_high) && 538 (free_high != keep_low) && (free_high != keep_high)) { 539 // No overlap, free both 540 FreeTemp(rl_free.reg); 541 } 542} 543 544bool Mir2Lir::IsLive(RegStorage reg) { 545 bool res; 546 if (reg.IsPair()) { 547 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 548 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 549 DCHECK_EQ(p_lo->IsLive(), p_hi->IsLive()); 550 res = p_lo->IsLive() || p_hi->IsLive(); 551 } else { 552 RegisterInfo* p = GetRegInfo(reg); 553 res = p->IsLive(); 554 } 555 return res; 556} 557 558bool Mir2Lir::IsTemp(RegStorage reg) { 559 bool res; 560 if (reg.IsPair()) { 561 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 562 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 563 res = p_lo->IsTemp() || p_hi->IsTemp(); 564 } else { 565 RegisterInfo* p = GetRegInfo(reg); 566 res = p->IsTemp(); 567 } 568 return res; 569} 570 571bool Mir2Lir::IsPromoted(RegStorage reg) { 572 bool res; 573 if (reg.IsPair()) { 574 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 575 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 576 res = !p_lo->IsTemp() || !p_hi->IsTemp(); 577 } else { 578 RegisterInfo* p = GetRegInfo(reg); 579 res = !p->IsTemp(); 580 } 581 return res; 582} 583 584bool Mir2Lir::IsDirty(RegStorage reg) { 585 bool res; 586 if (reg.IsPair()) { 587 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 588 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 589 res = p_lo->IsDirty() || p_hi->IsDirty(); 590 } else { 591 RegisterInfo* p = GetRegInfo(reg); 592 res = p->IsDirty(); 593 } 594 return res; 595} 596 597/* 598 * Similar to AllocTemp(), but forces the allocation of a specific 599 * register. No check is made to see if the register was previously 600 * allocated. Use with caution. 601 */ 602void Mir2Lir::LockTemp(RegStorage reg) { 603 DCHECK(IsTemp(reg)); 604 if (reg.IsPair()) { 605 RegisterInfo* p_lo = GetRegInfo(reg.GetLow()); 606 RegisterInfo* p_hi = GetRegInfo(reg.GetHigh()); 607 p_lo->MarkInUse(); 608 p_lo->MarkDead(); 609 p_hi->MarkInUse(); 610 p_hi->MarkDead(); 611 } else { 612 RegisterInfo* p = GetRegInfo(reg); 613 p->MarkInUse(); 614 p->MarkDead(); 615 } 616} 617 618void Mir2Lir::ResetDef(RegStorage reg) { 619 if (reg.IsPair()) { 620 GetRegInfo(reg.GetLow())->ResetDefBody(); 621 GetRegInfo(reg.GetHigh())->ResetDefBody(); 622 } else { 623 GetRegInfo(reg)->ResetDefBody(); 624 } 625} 626 627void Mir2Lir::NullifyRange(RegStorage reg, int s_reg) { 628 RegisterInfo* info = nullptr; 629 RegStorage rs = reg.IsPair() ? reg.GetLow() : reg; 630 if (IsTemp(rs)) { 631 info = GetRegInfo(reg); 632 } 633 if ((info != nullptr) && (info->DefStart() != nullptr) && (info->DefEnd() != nullptr)) { 634 DCHECK_EQ(info->SReg(), s_reg); // Make sure we're on the same page. 635 for (LIR* p = info->DefStart();; p = p->next) { 636 NopLIR(p); 637 if (p == info->DefEnd()) { 638 break; 639 } 640 } 641 } 642} 643 644/* 645 * Mark the beginning and end LIR of a def sequence. Note that 646 * on entry start points to the LIR prior to the beginning of the 647 * sequence. 648 */ 649void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) { 650 DCHECK(!rl.wide); 651 DCHECK(start && start->next); 652 DCHECK(finish); 653 RegisterInfo* p = GetRegInfo(rl.reg); 654 p->SetDefStart(start->next); 655 p->SetDefEnd(finish); 656} 657 658/* 659 * Mark the beginning and end LIR of a def sequence. Note that 660 * on entry start points to the LIR prior to the beginning of the 661 * sequence. 662 */ 663void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) { 664 DCHECK(rl.wide); 665 DCHECK(start && start->next); 666 DCHECK(finish); 667 RegisterInfo* p; 668 if (rl.reg.IsPair()) { 669 p = GetRegInfo(rl.reg.GetLow()); 670 ResetDef(rl.reg.GetHigh()); // Only track low of pair 671 } else { 672 p = GetRegInfo(rl.reg); 673 } 674 p->SetDefStart(start->next); 675 p->SetDefEnd(finish); 676} 677 678RegLocation Mir2Lir::WideToNarrow(RegLocation rl) { 679 DCHECK(rl.wide); 680 if (rl.location == kLocPhysReg) { 681 if (rl.reg.IsPair()) { 682 RegisterInfo* info_lo = GetRegInfo(rl.reg.GetLow()); 683 RegisterInfo* info_hi = GetRegInfo(rl.reg.GetHigh()); 684 if (info_lo->IsTemp()) { 685 info_lo->SetIsWide(false); 686 info_lo->ResetDefBody(); 687 } 688 if (info_hi->IsTemp()) { 689 info_hi->SetIsWide(false); 690 info_hi->ResetDefBody(); 691 } 692 rl.reg = rl.reg.GetLow(); 693 } else { 694 /* 695 * TODO: If not a pair, we can't just drop the high register. On some targets, we may be 696 * able to re-cast the 64-bit register as 32 bits, so it might be worthwhile to revisit 697 * this code. Will probably want to make this a virtual function. 698 */ 699 // Can't narrow 64-bit register. Clobber. 700 if (GetRegInfo(rl.reg)->IsTemp()) { 701 Clobber(rl.reg); 702 FreeTemp(rl.reg); 703 } 704 rl.location = kLocDalvikFrame; 705 } 706 } 707 rl.wide = false; 708 return rl; 709} 710 711void Mir2Lir::ResetDefLoc(RegLocation rl) { 712 DCHECK(!rl.wide); 713 if (IsTemp(rl.reg) && !(cu_->disable_opt & (1 << kSuppressLoads))) { 714 NullifyRange(rl.reg, rl.s_reg_low); 715 } 716 ResetDef(rl.reg); 717} 718 719void Mir2Lir::ResetDefLocWide(RegLocation rl) { 720 DCHECK(rl.wide); 721 // If pair, only track low reg of pair. 722 RegStorage rs = rl.reg.IsPair() ? rl.reg.GetLow() : rl.reg; 723 if (IsTemp(rs) && !(cu_->disable_opt & (1 << kSuppressLoads))) { 724 NullifyRange(rs, rl.s_reg_low); 725 } 726 ResetDef(rs); 727} 728 729void Mir2Lir::ResetDefTracking() { 730 GrowableArray<RegisterInfo*>::Iterator core_it(®_pool_->core_regs_); 731 for (RegisterInfo* info = core_it.Next(); info != nullptr; info = core_it.Next()) { 732 info->ResetDefBody(); 733 } 734 GrowableArray<RegisterInfo*>::Iterator sp_it(®_pool_->core_regs_); 735 for (RegisterInfo* info = sp_it.Next(); info != nullptr; info = sp_it.Next()) { 736 info->ResetDefBody(); 737 } 738 GrowableArray<RegisterInfo*>::Iterator dp_it(®_pool_->core_regs_); 739 for (RegisterInfo* info = dp_it.Next(); info != nullptr; info = dp_it.Next()) { 740 info->ResetDefBody(); 741 } 742} 743 744void Mir2Lir::ClobberAllTemps() { 745 GrowableArray<RegisterInfo*>::Iterator iter(&tempreg_info_); 746 for (RegisterInfo* info = iter.Next(); info != NULL; info = iter.Next()) { 747 ClobberBody(info); 748 } 749} 750 751void Mir2Lir::FlushRegWide(RegStorage reg) { 752 if (reg.IsPair()) { 753 RegisterInfo* info1 = GetRegInfo(reg.GetLow()); 754 RegisterInfo* info2 = GetRegInfo(reg.GetHigh()); 755 DCHECK(info1 && info2 && info1->IsWide() && info2->IsWide() && 756 (info1->Partner() == info2->GetReg()) && (info2->Partner() == info1->GetReg())); 757 if ((info1->IsLive() && info1->IsDirty()) || (info2->IsLive() && info2->IsDirty())) { 758 if (!(info1->IsTemp() && info2->IsTemp())) { 759 /* Should not happen. If it does, there's a problem in eval_loc */ 760 LOG(FATAL) << "Long half-temp, half-promoted"; 761 } 762 763 info1->SetIsDirty(false); 764 info2->SetIsDirty(false); 765 if (mir_graph_->SRegToVReg(info2->SReg()) < mir_graph_->SRegToVReg(info1->SReg())) { 766 info1 = info2; 767 } 768 int v_reg = mir_graph_->SRegToVReg(info1->SReg()); 769 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); 770 } 771 } else { 772 RegisterInfo* info = GetRegInfo(reg); 773 if (info->IsLive() && info->IsDirty()) { 774 info->SetIsDirty(false); 775 int v_reg = mir_graph_->SRegToVReg(info->SReg()); 776 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, k64); 777 } 778 } 779} 780 781void Mir2Lir::FlushReg(RegStorage reg) { 782 DCHECK(!reg.IsPair()); 783 RegisterInfo* info = GetRegInfo(reg); 784 if (info->IsLive() && info->IsDirty()) { 785 info->SetIsDirty(false); 786 int v_reg = mir_graph_->SRegToVReg(info->SReg()); 787 StoreBaseDisp(TargetReg(kSp), VRegOffset(v_reg), reg, kWord); 788 } 789} 790 791void Mir2Lir::FlushSpecificReg(RegisterInfo* info) { 792 if (info->IsWide()) { 793 FlushRegWide(info->GetReg()); 794 } else { 795 FlushReg(info->GetReg()); 796 } 797} 798 799void Mir2Lir::FlushAllRegs() { 800 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); 801 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 802 if (info->IsDirty() && info->IsLive()) { 803 FlushSpecificReg(info); 804 } 805 info->MarkDead(); 806 info->SetIsWide(false); 807 } 808} 809 810 811bool Mir2Lir::RegClassMatches(int reg_class, RegStorage reg) { 812 if (reg_class == kAnyReg) { 813 return true; 814 } else if (reg_class == kCoreReg) { 815 return !reg.IsFloat(); 816 } else { 817 return reg.IsFloat(); 818 } 819} 820 821void Mir2Lir::MarkLive(RegLocation loc) { 822 RegStorage reg = loc.reg; 823 if (!IsTemp(reg)) { 824 return; 825 } 826 int s_reg = loc.s_reg_low; 827 if (s_reg == INVALID_SREG) { 828 // Can't be live if no associated sreg. 829 if (reg.IsPair()) { 830 GetRegInfo(reg.GetLow())->MarkDead(); 831 GetRegInfo(reg.GetHigh())->MarkDead(); 832 } else { 833 GetRegInfo(reg)->MarkDead(); 834 } 835 } else { 836 if (reg.IsPair()) { 837 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 838 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 839 if (info_lo->IsLive() && (info_lo->SReg() == s_reg) && info_hi->IsLive() && 840 (info_hi->SReg() == s_reg)) { 841 return; // Already live. 842 } 843 ClobberSReg(s_reg); 844 ClobberSReg(s_reg + 1); 845 info_lo->MarkLive(s_reg); 846 info_hi->MarkLive(s_reg + 1); 847 } else { 848 RegisterInfo* info = GetRegInfo(reg); 849 if (info->IsLive() && (info->SReg() == s_reg)) { 850 return; // Already live. 851 } 852 ClobberSReg(s_reg); 853 if (loc.wide) { 854 ClobberSReg(s_reg + 1); 855 } 856 info->MarkLive(s_reg); 857 } 858 if (loc.wide) { 859 MarkWide(reg); 860 } else { 861 MarkNarrow(reg); 862 } 863 } 864} 865 866void Mir2Lir::MarkTemp(RegStorage reg) { 867 DCHECK(!reg.IsPair()); 868 RegisterInfo* info = GetRegInfo(reg); 869 tempreg_info_.Insert(info); 870 info->SetIsTemp(true); 871} 872 873void Mir2Lir::UnmarkTemp(RegStorage reg) { 874 DCHECK(!reg.IsPair()); 875 RegisterInfo* info = GetRegInfo(reg); 876 tempreg_info_.Delete(info); 877 info->SetIsTemp(false); 878} 879 880void Mir2Lir::MarkWide(RegStorage reg) { 881 if (reg.IsPair()) { 882 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 883 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 884 // Unpair any old partners. 885 if (info_lo->IsWide() && info_lo->Partner() != info_hi->GetReg()) { 886 GetRegInfo(info_lo->Partner())->SetIsWide(false); 887 } 888 if (info_hi->IsWide() && info_hi->Partner() != info_lo->GetReg()) { 889 GetRegInfo(info_hi->Partner())->SetIsWide(false); 890 } 891 info_lo->SetIsWide(true); 892 info_hi->SetIsWide(true); 893 info_lo->SetPartner(reg.GetHigh()); 894 info_hi->SetPartner(reg.GetLow()); 895 } else { 896 RegisterInfo* info = GetRegInfo(reg); 897 info->SetIsWide(true); 898 info->SetPartner(reg); 899 } 900} 901 902void Mir2Lir::MarkNarrow(RegStorage reg) { 903 DCHECK(!reg.IsPair()); 904 RegisterInfo* info = GetRegInfo(reg); 905 info->SetIsWide(false); 906 info->SetPartner(reg); 907} 908 909void Mir2Lir::MarkClean(RegLocation loc) { 910 if (loc.reg.IsPair()) { 911 RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); 912 info->SetIsDirty(false); 913 info = GetRegInfo(loc.reg.GetHigh()); 914 info->SetIsDirty(false); 915 } else { 916 RegisterInfo* info = GetRegInfo(loc.reg); 917 info->SetIsDirty(false); 918 } 919} 920 921// FIXME: need to verify rules/assumptions about how wide values are treated in 64BitSolos. 922void Mir2Lir::MarkDirty(RegLocation loc) { 923 if (loc.home) { 924 // If already home, can't be dirty 925 return; 926 } 927 if (loc.reg.IsPair()) { 928 RegisterInfo* info = GetRegInfo(loc.reg.GetLow()); 929 info->SetIsDirty(true); 930 info = GetRegInfo(loc.reg.GetHigh()); 931 info->SetIsDirty(true); 932 } else { 933 RegisterInfo* info = GetRegInfo(loc.reg); 934 info->SetIsDirty(true); 935 } 936} 937 938void Mir2Lir::MarkInUse(RegStorage reg) { 939 if (reg.IsPair()) { 940 GetRegInfo(reg.GetLow())->MarkInUse(); 941 GetRegInfo(reg.GetHigh())->MarkInUse(); 942 } else { 943 GetRegInfo(reg)->MarkInUse(); 944 } 945} 946 947bool Mir2Lir::CheckCorePoolSanity() { 948 GrowableArray<RegisterInfo*>::Iterator it(&tempreg_info_); 949 for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { 950 if (info->IsTemp() && info->IsLive() && info->IsWide()) { 951 RegStorage my_reg = info->GetReg(); 952 int my_sreg = info->SReg(); 953 RegStorage partner_reg = info->Partner(); 954 RegisterInfo* partner = GetRegInfo(partner_reg); 955 DCHECK(partner != NULL); 956 DCHECK(partner->IsWide()); 957 DCHECK_EQ(my_reg.GetReg(), partner->Partner().GetReg()); 958 DCHECK(partner->IsLive()); 959 int partner_sreg = partner->SReg(); 960 if (my_sreg == INVALID_SREG) { 961 DCHECK_EQ(partner_sreg, INVALID_SREG); 962 } else { 963 int diff = my_sreg - partner_sreg; 964 DCHECK((diff == 0) || (diff == -1) || (diff == 1)); 965 } 966 } 967 if (info->Master() != info) { 968 // Aliased. 969 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { 970 // If I'm live, master should not be live, but should show liveness in alias set. 971 DCHECK_EQ(info->Master()->SReg(), INVALID_SREG); 972 DCHECK(!info->Master()->IsDead()); 973 } 974// TODO: Add checks in !info->IsDead() case to ensure every live bit is owned by exactly 1 reg. 975 } 976 if (info->IsAliased()) { 977 // Has child aliases. 978 DCHECK_EQ(info->Master(), info); 979 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { 980 // Master live, no child should be dead - all should show liveness in set. 981 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) { 982 DCHECK(!p->IsDead()); 983 DCHECK_EQ(p->SReg(), INVALID_SREG); 984 } 985 } else if (!info->IsDead()) { 986 // Master not live, one or more aliases must be. 987 bool live_alias = false; 988 for (RegisterInfo* p = info->GetAliasChain(); p != nullptr; p = p->GetAliasChain()) { 989 live_alias |= p->IsLive(); 990 } 991 DCHECK(live_alias); 992 } 993 } 994 if (info->IsLive() && (info->SReg() == INVALID_SREG)) { 995 // If not fully live, should have INVALID_SREG and def's should be null. 996 DCHECK(info->DefStart() == nullptr); 997 DCHECK(info->DefEnd() == nullptr); 998 } 999 } 1000 return true; 1001} 1002 1003/* 1004 * Return an updated location record with current in-register status. 1005 * If the value lives in live temps, reflect that fact. No code 1006 * is generated. If the live value is part of an older pair, 1007 * clobber both low and high. 1008 * TUNING: clobbering both is a bit heavy-handed, but the alternative 1009 * is a bit complex when dealing with FP regs. Examine code to see 1010 * if it's worthwhile trying to be more clever here. 1011 */ 1012RegLocation Mir2Lir::UpdateLoc(RegLocation loc) { 1013 DCHECK(!loc.wide); 1014 DCHECK(CheckCorePoolSanity()); 1015 if (loc.location != kLocPhysReg) { 1016 DCHECK((loc.location == kLocDalvikFrame) || 1017 (loc.location == kLocCompilerTemp)); 1018 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, false); 1019 if (reg.Valid()) { 1020 bool match = true; 1021 RegisterInfo* info = GetRegInfo(reg); 1022 match &= !reg.IsPair(); 1023 match &= !info->IsWide(); 1024 if (match) { 1025 loc.location = kLocPhysReg; 1026 loc.reg = reg; 1027 } else { 1028 Clobber(reg); 1029 FreeTemp(reg); 1030 } 1031 } 1032 } 1033 return loc; 1034} 1035 1036RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) { 1037 DCHECK(loc.wide); 1038 DCHECK(CheckCorePoolSanity()); 1039 if (loc.location != kLocPhysReg) { 1040 DCHECK((loc.location == kLocDalvikFrame) || 1041 (loc.location == kLocCompilerTemp)); 1042 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); 1043 if (reg.Valid()) { 1044 bool match = true; 1045 if (reg.IsPair()) { 1046 // If we've got a register pair, make sure that it was last used as the same pair. 1047 RegisterInfo* info_lo = GetRegInfo(reg.GetLow()); 1048 RegisterInfo* info_hi = GetRegInfo(reg.GetHigh()); 1049 match &= info_lo->IsWide(); 1050 match &= info_hi->IsWide(); 1051 match &= (info_lo->Partner() == info_hi->GetReg()); 1052 match &= (info_hi->Partner() == info_lo->GetReg()); 1053 } else { 1054 RegisterInfo* info = GetRegInfo(reg); 1055 match &= info->IsWide(); 1056 match &= (info->GetReg() == info->Partner()); 1057 } 1058 if (match) { 1059 loc.location = kLocPhysReg; 1060 loc.reg = reg; 1061 } else { 1062 Clobber(reg); 1063 FreeTemp(reg); 1064 } 1065 } 1066 } 1067 return loc; 1068} 1069 1070/* For use in cases we don't know (or care) width */ 1071RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) { 1072 if (loc.wide) 1073 return UpdateLocWide(loc); 1074 else 1075 return UpdateLoc(loc); 1076} 1077 1078RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { 1079 DCHECK(loc.wide); 1080 1081 loc = UpdateLocWide(loc); 1082 1083 /* If already in registers, we can assume proper form. Right reg class? */ 1084 if (loc.location == kLocPhysReg) { 1085 if (!RegClassMatches(reg_class, loc.reg)) { 1086 // Wrong register class. Reallocate and transfer ownership. 1087 RegStorage new_regs = AllocTypedTempWide(loc.fp, reg_class); 1088 // Clobber the old regs. 1089 Clobber(loc.reg); 1090 // ...and mark the new ones live. 1091 loc.reg = new_regs; 1092 MarkWide(loc.reg); 1093 MarkLive(loc); 1094 } 1095 return loc; 1096 } 1097 1098 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 1099 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); 1100 1101 loc.reg = AllocTypedTempWide(loc.fp, reg_class); 1102 MarkWide(loc.reg); 1103 1104 if (update) { 1105 loc.location = kLocPhysReg; 1106 MarkLive(loc); 1107 } 1108 return loc; 1109} 1110 1111RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { 1112 if (loc.wide) { 1113 return EvalLocWide(loc, reg_class, update); 1114 } 1115 1116 loc = UpdateLoc(loc); 1117 1118 if (loc.location == kLocPhysReg) { 1119 if (!RegClassMatches(reg_class, loc.reg)) { 1120 // Wrong register class. Reallocate and transfer ownership. 1121 RegStorage new_reg = AllocTypedTemp(loc.fp, reg_class); 1122 // Clobber the old reg. 1123 Clobber(loc.reg); 1124 // ...and mark the new one live. 1125 loc.reg = new_reg; 1126 MarkLive(loc); 1127 } 1128 return loc; 1129 } 1130 1131 DCHECK_NE(loc.s_reg_low, INVALID_SREG); 1132 1133 loc.reg = AllocTypedTemp(loc.fp, reg_class); 1134 1135 if (update) { 1136 loc.location = kLocPhysReg; 1137 MarkLive(loc); 1138 } 1139 return loc; 1140} 1141 1142/* USE SSA names to count references of base Dalvik v_regs. */ 1143void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts, size_t num_regs) { 1144 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 1145 RegLocation loc = mir_graph_->reg_location_[i]; 1146 RefCounts* counts = loc.fp ? fp_counts : core_counts; 1147 int p_map_idx = SRegToPMap(loc.s_reg_low); 1148 if (loc.fp) { 1149 if (loc.wide) { 1150 // Treat doubles as a unit, using upper half of fp_counts array. 1151 counts[p_map_idx + num_regs].count += mir_graph_->GetUseCount(i); 1152 i++; 1153 } else { 1154 counts[p_map_idx].count += mir_graph_->GetUseCount(i); 1155 } 1156 } else if (!IsInexpensiveConstant(loc)) { 1157 counts[p_map_idx].count += mir_graph_->GetUseCount(i); 1158 } 1159 } 1160} 1161 1162/* qsort callback function, sort descending */ 1163static int SortCounts(const void *val1, const void *val2) { 1164 const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); 1165 const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); 1166 // Note that we fall back to sorting on reg so we get stable output 1167 // on differing qsort implementations (such as on host and target or 1168 // between local host and build servers). 1169 return (op1->count == op2->count) 1170 ? (op1->s_reg - op2->s_reg) 1171 : (op1->count < op2->count ? 1 : -1); 1172} 1173 1174void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) { 1175 LOG(INFO) << msg; 1176 for (int i = 0; i < size; i++) { 1177 if ((arr[i].s_reg & STARTING_DOUBLE_SREG) != 0) { 1178 LOG(INFO) << "s_reg[D" << (arr[i].s_reg & ~STARTING_DOUBLE_SREG) << "]: " << arr[i].count; 1179 } else { 1180 LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; 1181 } 1182 } 1183} 1184 1185/* 1186 * Note: some portions of this code required even if the kPromoteRegs 1187 * optimization is disabled. 1188 */ 1189void Mir2Lir::DoPromotion() { 1190 int dalvik_regs = cu_->num_dalvik_registers; 1191 int num_regs = dalvik_regs + mir_graph_->GetNumUsedCompilerTemps(); 1192 const int promotion_threshold = 1; 1193 // Allocate the promotion map - one entry for each Dalvik vReg or compiler temp 1194 promotion_map_ = static_cast<PromotionMap*> 1195 (arena_->Alloc(num_regs * sizeof(promotion_map_[0]), kArenaAllocRegAlloc)); 1196 1197 // Allow target code to add any special registers 1198 AdjustSpillMask(); 1199 1200 /* 1201 * Simple register promotion. Just do a static count of the uses 1202 * of Dalvik registers. Note that we examine the SSA names, but 1203 * count based on original Dalvik register name. Count refs 1204 * separately based on type in order to give allocation 1205 * preference to fp doubles - which must be allocated sequential 1206 * physical single fp registers starting with an even-numbered 1207 * reg. 1208 * TUNING: replace with linear scan once we have the ability 1209 * to describe register live ranges for GC. 1210 */ 1211 RefCounts *core_regs = 1212 static_cast<RefCounts*>(arena_->Alloc(sizeof(RefCounts) * num_regs, 1213 kArenaAllocRegAlloc)); 1214 RefCounts *FpRegs = 1215 static_cast<RefCounts *>(arena_->Alloc(sizeof(RefCounts) * num_regs * 2, 1216 kArenaAllocRegAlloc)); 1217 // Set ssa names for original Dalvik registers 1218 for (int i = 0; i < dalvik_regs; i++) { 1219 core_regs[i].s_reg = FpRegs[i].s_reg = i; 1220 } 1221 1222 // Set ssa names for compiler temporaries 1223 for (unsigned int ct_idx = 0; ct_idx < mir_graph_->GetNumUsedCompilerTemps(); ct_idx++) { 1224 CompilerTemp* ct = mir_graph_->GetCompilerTemp(ct_idx); 1225 core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; 1226 FpRegs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; 1227 FpRegs[num_regs + dalvik_regs + ct_idx].s_reg = ct->s_reg_low; 1228 } 1229 1230 // Duplicate in upper half to represent possible fp double starting sregs. 1231 for (int i = 0; i < num_regs; i++) { 1232 FpRegs[num_regs + i].s_reg = FpRegs[i].s_reg | STARTING_DOUBLE_SREG; 1233 } 1234 1235 // Sum use counts of SSA regs by original Dalvik vreg. 1236 CountRefs(core_regs, FpRegs, num_regs); 1237 1238 1239 // Sort the count arrays 1240 qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); 1241 qsort(FpRegs, num_regs * 2, sizeof(RefCounts), SortCounts); 1242 1243 if (cu_->verbose) { 1244 DumpCounts(core_regs, num_regs, "Core regs after sort"); 1245 DumpCounts(FpRegs, num_regs * 2, "Fp regs after sort"); 1246 } 1247 1248 if (!(cu_->disable_opt & (1 << kPromoteRegs))) { 1249 // Promote FpRegs 1250 for (int i = 0; (i < (num_regs * 2)) && (FpRegs[i].count >= promotion_threshold); i++) { 1251 int p_map_idx = SRegToPMap(FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG); 1252 if ((FpRegs[i].s_reg & STARTING_DOUBLE_SREG) != 0) { 1253 if ((promotion_map_[p_map_idx].fp_location != kLocPhysReg) && 1254 (promotion_map_[p_map_idx + 1].fp_location != kLocPhysReg)) { 1255 int low_sreg = FpRegs[i].s_reg & ~STARTING_DOUBLE_SREG; 1256 // Ignore result - if can't alloc double may still be able to alloc singles. 1257 AllocPreservedDouble(low_sreg); 1258 } 1259 } else if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { 1260 RegStorage reg = AllocPreservedSingle(FpRegs[i].s_reg); 1261 if (!reg.Valid()) { 1262 break; // No more left. 1263 } 1264 } 1265 } 1266 1267 // Promote core regs 1268 for (int i = 0; (i < num_regs) && 1269 (core_regs[i].count >= promotion_threshold); i++) { 1270 int p_map_idx = SRegToPMap(core_regs[i].s_reg); 1271 if (promotion_map_[p_map_idx].core_location != 1272 kLocPhysReg) { 1273 RegStorage reg = AllocPreservedCoreReg(core_regs[i].s_reg); 1274 if (!reg.Valid()) { 1275 break; // No more left 1276 } 1277 } 1278 } 1279 } 1280 1281 // Now, update SSA names to new home locations 1282 for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { 1283 RegLocation *curr = &mir_graph_->reg_location_[i]; 1284 int p_map_idx = SRegToPMap(curr->s_reg_low); 1285 if (!curr->wide) { 1286 if (curr->fp) { 1287 if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { 1288 curr->location = kLocPhysReg; 1289 curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].FpReg); 1290 curr->home = true; 1291 } 1292 } else { 1293 if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { 1294 curr->location = kLocPhysReg; 1295 curr->reg = RegStorage::Solo32(promotion_map_[p_map_idx].core_reg); 1296 curr->home = true; 1297 } 1298 } 1299 } else { 1300 if (curr->high_word) { 1301 continue; 1302 } 1303 if (curr->fp) { 1304 if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && 1305 (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg)) { 1306 int low_reg = promotion_map_[p_map_idx].FpReg; 1307 int high_reg = promotion_map_[p_map_idx+1].FpReg; 1308 // Doubles require pair of singles starting at even reg 1309 // TODO: move target-specific restrictions out of here. 1310 if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { 1311 curr->location = kLocPhysReg; 1312 if (cu_->instruction_set == kThumb2) { 1313 curr->reg = RegStorage::FloatSolo64(RegStorage::RegNum(low_reg) >> 1); 1314 } else { 1315 curr->reg = RegStorage(RegStorage::k64BitPair, low_reg, high_reg); 1316 } 1317 curr->home = true; 1318 } 1319 } 1320 } else { 1321 if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) 1322 && (promotion_map_[p_map_idx+1].core_location == 1323 kLocPhysReg)) { 1324 curr->location = kLocPhysReg; 1325 curr->reg = RegStorage(RegStorage::k64BitPair, promotion_map_[p_map_idx].core_reg, 1326 promotion_map_[p_map_idx+1].core_reg); 1327 curr->home = true; 1328 } 1329 } 1330 } 1331 } 1332 if (cu_->verbose) { 1333 DumpPromotionMap(); 1334 } 1335} 1336 1337/* Returns sp-relative offset in bytes for a VReg */ 1338int Mir2Lir::VRegOffset(int v_reg) { 1339 return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, 1340 fp_spill_mask_, frame_size_, v_reg, 1341 cu_->instruction_set); 1342} 1343 1344/* Returns sp-relative offset in bytes for a SReg */ 1345int Mir2Lir::SRegOffset(int s_reg) { 1346 return VRegOffset(mir_graph_->SRegToVReg(s_reg)); 1347} 1348 1349/* Mark register usage state and return long retloc */ 1350RegLocation Mir2Lir::GetReturnWide(bool is_double) { 1351 RegLocation gpr_res = LocCReturnWide(); 1352 RegLocation fpr_res = LocCReturnDouble(); 1353 RegLocation res = is_double ? fpr_res : gpr_res; 1354 Clobber(res.reg); 1355 LockTemp(res.reg); 1356 MarkWide(res.reg); 1357 return res; 1358} 1359 1360RegLocation Mir2Lir::GetReturn(bool is_float) { 1361 RegLocation gpr_res = LocCReturn(); 1362 RegLocation fpr_res = LocCReturnFloat(); 1363 RegLocation res = is_float ? fpr_res : gpr_res; 1364 Clobber(res.reg); 1365 if (cu_->instruction_set == kMips) { 1366 MarkInUse(res.reg); 1367 } else { 1368 LockTemp(res.reg); 1369 } 1370 return res; 1371} 1372 1373void Mir2Lir::SimpleRegAlloc() { 1374 DoPromotion(); 1375 1376 if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { 1377 LOG(INFO) << "After Promotion"; 1378 mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); 1379 } 1380 1381 /* Set the frame size */ 1382 frame_size_ = ComputeFrameSize(); 1383} 1384 1385/* 1386 * Get the "real" sreg number associated with an s_reg slot. In general, 1387 * s_reg values passed through codegen are the SSA names created by 1388 * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location 1389 * array. However, renaming is accomplished by simply replacing RegLocation 1390 * entries in the reglocation[] array. Therefore, when location 1391 * records for operands are first created, we need to ask the locRecord 1392 * identified by the dataflow pass what it's new name is. 1393 */ 1394int Mir2Lir::GetSRegHi(int lowSreg) { 1395 return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; 1396} 1397 1398bool Mir2Lir::LiveOut(int s_reg) { 1399 // For now. 1400 return true; 1401} 1402 1403} // namespace art 1404