assemble_x86.cc revision 2c498d1f28e62e81fbdb477ff93ca7454e7493d7
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "x86_lir.h" 20 21namespace art { 22 23#define MAX_ASSEMBLER_RETRIES 50 24 25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" }, 28 { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, 29 30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \ 40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \ 41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \ 45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \ 52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \ 53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \ 57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \ 60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \ 61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \ 68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \ 69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \ 73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \ 76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \ 77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" } 80 81ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 82 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 83 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 84 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 85 0x80, 0x0 /* RegMem8/imm8 */, 86 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 87ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 88 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 89 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 90 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 91 0x80, 0x1 /* RegMem8/imm8 */, 92 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 93ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 94 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 95 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 96 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 97 0x80, 0x2 /* RegMem8/imm8 */, 98 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 99ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 100 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 101 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 102 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 103 0x80, 0x3 /* RegMem8/imm8 */, 104 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 105ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 106 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 107 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 108 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 109 0x80, 0x4 /* RegMem8/imm8 */, 110 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 111ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 112 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 113 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 114 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 115 0x80, 0x5 /* RegMem8/imm8 */, 116 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 117ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 118 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 119 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 120 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 121 0x80, 0x6 /* RegMem8/imm8 */, 122 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 123ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 124 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 125 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 126 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 127 0x80, 0x7 /* RegMem8/imm8 */, 128 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 129#undef ENCODING_MAP 130 131 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" }, 132 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 133 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 134 135 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" }, 136 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 137 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 138 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" }, 139 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 140 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 141 142 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" }, 143 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 144 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" }, 145 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" }, 146 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" }, 147 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 148 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" }, 149 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" }, 150 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" }, 151 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 152 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" }, 153 154 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" }, 155 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 156 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" }, 157 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" }, 158 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" }, 159 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 160 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" }, 161 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" }, 162 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" }, 163 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 164 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" }, 165 166 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" }, 167 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 168 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" }, 169 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" }, 170 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" }, 171 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 172 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" }, 173 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" }, 174 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" }, 175 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 176 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" }, 177 178 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 179 180 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, {0, 0, 0x0F, 0x40, 0, 0, 0, 0}, "Cmovcc32RR", "!2c !0r,!1r" }, 181 182#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 183{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \ 184{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 185{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 186{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \ 187{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \ 188{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 189 \ 190{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \ 191{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 192{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 193{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \ 194{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \ 195{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 196 \ 197{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \ 198{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 199{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 200{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \ 201{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \ 202{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" } 203 204 SHIFT_ENCODING_MAP(Rol, 0x0), 205 SHIFT_ENCODING_MAP(Ror, 0x1), 206 SHIFT_ENCODING_MAP(Rcl, 0x2), 207 SHIFT_ENCODING_MAP(Rcr, 0x3), 208 SHIFT_ENCODING_MAP(Sal, 0x4), 209 SHIFT_ENCODING_MAP(Shr, 0x5), 210 SHIFT_ENCODING_MAP(Sar, 0x7), 211#undef SHIFT_ENCODING_MAP 212 213 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" }, 214 { kX86Shld32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1}, "Shld32", "!0r,!1r,!2d" }, 215 { kX86Shrd32RRI, kRegRegImmRev, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1}, "Shrd32", "!0r,!1r,!2d" }, 216 217 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" }, 218 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" }, 219 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 220 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" }, 221 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" }, 222 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 223 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" }, 224 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" }, 225 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 226 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" }, 227 228#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 229 reg, reg_kind, reg_flags, \ 230 mem, mem_kind, mem_flags, \ 231 arr, arr_kind, arr_flags, imm, \ 232 b_flags, hw_flags, w_flags, \ 233 b_format, hw_format, w_format) \ 234{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \ 235{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \ 236{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \ 237{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \ 238{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \ 239{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \ 240{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \ 241{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \ 242{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" } 243 244 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 245 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 246 247 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 248 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 249 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 250 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 251#undef UNARY_ENCODING_MAP 252 253 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0 }, "Cdq", "" }, 254 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" }, 255 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" }, 256 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" }, 257 258#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 259{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ 260{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ 261{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 262 263 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 264 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" }, 265 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 266 267 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 268 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" }, 269 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 270 271 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 272 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 273 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 274 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 275 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 276 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 277 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES), 278 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES), 279 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES), 280 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES), 281 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0), 282 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0), 283 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0), 284 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0), 285 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0), 286 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0), 287 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 288 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 289 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0), 290 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0), 291 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0), 292 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0), 293 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0), 294 295 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" }, 296 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" }, 297 { kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" }, 298 { kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" }, 299 300 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), 301 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsMR", "[!0r+!1d],!2r" }, 302 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 303 304 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), 305 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsMR", "[!0r+!1d],!2r" }, 306 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0 }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 307 308 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRM", "!0r,[!1r+!2d]" }, 309 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0 }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 310 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsMR", "[!0r+!1d],!2r" }, 311 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0 }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 312 313 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRM", "!0r,[!1r+!2d]" }, 314 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0 }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 315 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsMR", "[!0r+!1d],!2r" }, 316 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0 }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 317 318 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 319 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" }, 320 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" }, 321 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 322 323 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" }, 324 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" }, 325 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 326 327 // TODO: load/store? 328 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 329 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" }, 330 331 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES), 332 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES), 333 334 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" }, 335 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" }, 336 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 337 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 338 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 339 { kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" }, 340 { kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, 341 342 EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 343 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 344 EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 345 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 346#undef EXT_0F_ENCODING_MAP 347 348 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" }, 349 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" }, 350 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" }, 351 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" }, 352 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" }, 353 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" }, 354 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" }, 355 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 356 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" }, 357 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" }, 358 359 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" }, 360 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 361 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" }, 362}; 363 364static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) { 365 size_t size = 0; 366 if (entry->skeleton.prefix1 > 0) { 367 ++size; 368 if (entry->skeleton.prefix2 > 0) { 369 ++size; 370 } 371 } 372 ++size; // opcode 373 if (entry->skeleton.opcode == 0x0F) { 374 ++size; 375 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 376 ++size; 377 } 378 } 379 ++size; // modrm 380 if (has_sib || base == rX86_SP) { 381 // SP requires a SIB byte. 382 ++size; 383 } 384 if (displacement != 0 || base == rBP) { 385 // BP requires an explicit displacement, even when it's 0. 386 if (entry->opcode != kX86Lea32RA) { 387 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name; 388 } 389 size += IS_SIMM8(displacement) ? 1 : 4; 390 } 391 size += entry->skeleton.immediate_bytes; 392 return size; 393} 394 395int X86Mir2Lir::GetInsnSize(LIR* lir) { 396 DCHECK(!IsPseudoLirOp(lir->opcode)); 397 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 398 switch (entry->kind) { 399 case kData: 400 return 4; // 4 bytes of data 401 case kNop: 402 return lir->operands[0]; // length of nop is sole operand 403 case kNullary: 404 return 1; // 1 byte of opcode 405 case kRegOpcode: // lir operands - 0: reg 406 return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm 407 case kReg: // lir operands - 0: reg 408 return ComputeSize(entry, 0, 0, false); 409 case kMem: // lir operands - 0: base, 1: disp 410 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 411 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 412 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 413 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 414 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 415 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 416 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 417 case kThreadReg: // lir operands - 0: disp, 1: reg 418 return ComputeSize(entry, 0, lir->operands[0], false); 419 case kRegReg: 420 return ComputeSize(entry, 0, 0, false); 421 case kRegRegStore: 422 return ComputeSize(entry, 0, 0, false); 423 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 424 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 425 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 426 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 427 case kRegThread: // lir operands - 0: reg, 1: disp 428 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 429 case kRegImm: { // lir operands - 0: reg, 1: immediate 430 size_t size = ComputeSize(entry, 0, 0, false); 431 if (entry->skeleton.ax_opcode == 0) { 432 return size; 433 } else { 434 // AX opcodes don't require the modrm byte. 435 int reg = lir->operands[0]; 436 return size - (reg == rAX ? 1 : 0); 437 } 438 } 439 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 440 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 441 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 442 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 443 case kThreadImm: // lir operands - 0: disp, 1: imm 444 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 445 case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm 446 case kRegRegImmRev: 447 return ComputeSize(entry, 0, 0, false); 448 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 449 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 450 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 451 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 452 case kMovRegImm: // lir operands - 0: reg, 1: immediate 453 return 1 + entry->skeleton.immediate_bytes; 454 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 455 // Shift by immediate one has a shorter opcode. 456 return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0); 457 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 458 // Shift by immediate one has a shorter opcode. 459 return ComputeSize(entry, lir->operands[0], lir->operands[1], false) - 460 (lir->operands[2] == 1 ? 1 : 0); 461 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 462 // Shift by immediate one has a shorter opcode. 463 return ComputeSize(entry, lir->operands[0], lir->operands[3], true) - 464 (lir->operands[4] == 1 ? 1 : 0); 465 case kShiftRegCl: 466 return ComputeSize(entry, 0, 0, false); 467 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 468 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 469 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 470 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 471 case kRegCond: // lir operands - 0: reg, 1: cond 472 return ComputeSize(entry, 0, 0, false); 473 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 474 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 475 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 476 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 477 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: cond 478 return ComputeSize(entry, 0, 0, false); 479 case kJcc: 480 if (lir->opcode == kX86Jcc8) { 481 return 2; // opcode + rel8 482 } else { 483 DCHECK(lir->opcode == kX86Jcc32); 484 return 6; // 2 byte opcode + rel32 485 } 486 case kJmp: 487 if (lir->opcode == kX86Jmp8) { 488 return 2; // opcode + rel8 489 } else if (lir->opcode == kX86Jmp32) { 490 return 5; // opcode + rel32 491 } else { 492 DCHECK(lir->opcode == kX86JmpR); 493 return 2; // opcode + modrm 494 } 495 case kCall: 496 switch (lir->opcode) { 497 case kX86CallR: return 2; // opcode modrm 498 case kX86CallM: // lir operands - 0: base, 1: disp 499 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 500 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 501 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 502 case kX86CallT: // lir operands - 0: disp 503 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 504 default: 505 break; 506 } 507 break; 508 case kPcRel: 509 if (entry->opcode == kX86PcRelLoadRA) { 510 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 511 return ComputeSize(entry, lir->operands[1], 0x12345678, true); 512 } else { 513 DCHECK(entry->opcode == kX86PcRelAdr); 514 return 5; // opcode with reg + 4 byte immediate 515 } 516 case kMacro: 517 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 518 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 519 ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) - 520 (lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding 521 default: 522 break; 523 } 524 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 525 return 0; 526} 527 528void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) { 529 if (entry->skeleton.prefix1 != 0) { 530 code_buffer_.push_back(entry->skeleton.prefix1); 531 if (entry->skeleton.prefix2 != 0) { 532 code_buffer_.push_back(entry->skeleton.prefix2); 533 } 534 } else { 535 DCHECK_EQ(0, entry->skeleton.prefix2); 536 } 537} 538 539void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { 540 code_buffer_.push_back(entry->skeleton.opcode); 541 if (entry->skeleton.opcode == 0x0F) { 542 code_buffer_.push_back(entry->skeleton.extra_opcode1); 543 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 544 code_buffer_.push_back(entry->skeleton.extra_opcode2); 545 } else { 546 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 547 } 548 } else { 549 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 550 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 551 } 552} 553 554void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) { 555 EmitPrefix(entry); 556 EmitOpcode(entry); 557} 558 559static uint8_t ModrmForDisp(int base, int disp) { 560 // BP requires an explicit disp, so do not omit it in the 0 case 561 if (disp == 0 && base != rBP) { 562 return 0; 563 } else if (IS_SIMM8(disp)) { 564 return 1; 565 } else { 566 return 2; 567 } 568} 569 570void X86Mir2Lir::EmitDisp(uint8_t base, int disp) { 571 // BP requires an explicit disp, so do not omit it in the 0 case 572 if (disp == 0 && base != rBP) { 573 return; 574 } else if (IS_SIMM8(disp)) { 575 code_buffer_.push_back(disp & 0xFF); 576 } else { 577 code_buffer_.push_back(disp & 0xFF); 578 code_buffer_.push_back((disp >> 8) & 0xFF); 579 code_buffer_.push_back((disp >> 16) & 0xFF); 580 code_buffer_.push_back((disp >> 24) & 0xFF); 581 } 582} 583 584void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) { 585 DCHECK_LT(reg_or_opcode, 8); 586 DCHECK_LT(base, 8); 587 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; 588 code_buffer_.push_back(modrm); 589 if (base == rX86_SP) { 590 // Special SIB for SP base 591 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); 592 } 593 EmitDisp(base, disp); 594} 595 596void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, 597 int scale, int disp) { 598 DCHECK_LT(reg_or_opcode, 8); 599 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP; 600 code_buffer_.push_back(modrm); 601 DCHECK_LT(scale, 4); 602 DCHECK_LT(index, 8); 603 DCHECK_LT(base, 8); 604 uint8_t sib = (scale << 6) | (index << 3) | base; 605 code_buffer_.push_back(sib); 606 EmitDisp(base, disp); 607} 608 609void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) { 610 switch (entry->skeleton.immediate_bytes) { 611 case 1: 612 DCHECK(IS_SIMM8(imm)); 613 code_buffer_.push_back(imm & 0xFF); 614 break; 615 case 2: 616 DCHECK(IS_SIMM16(imm)); 617 code_buffer_.push_back(imm & 0xFF); 618 code_buffer_.push_back((imm >> 8) & 0xFF); 619 break; 620 case 4: 621 code_buffer_.push_back(imm & 0xFF); 622 code_buffer_.push_back((imm >> 8) & 0xFF); 623 code_buffer_.push_back((imm >> 16) & 0xFF); 624 code_buffer_.push_back((imm >> 24) & 0xFF); 625 break; 626 default: 627 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 628 << ") for instruction: " << entry->name; 629 break; 630 } 631} 632 633void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) { 634 EmitPrefixAndOpcode(entry); 635 // There's no 3-byte instruction with +rd 636 DCHECK(entry->skeleton.opcode != 0x0F || 637 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); 638 DCHECK(!X86_FPREG(reg)); 639 DCHECK_LT(reg, 8); 640 code_buffer_.back() += reg; 641 DCHECK_EQ(0, entry->skeleton.ax_opcode); 642 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 643} 644 645void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) { 646 EmitPrefixAndOpcode(entry); 647 if (X86_FPREG(reg)) { 648 reg = reg & X86_FP_REG_MASK; 649 } 650 if (reg >= 4) { 651 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 652 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 653 } 654 DCHECK_LT(reg, 8); 655 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 656 code_buffer_.push_back(modrm); 657 DCHECK_EQ(0, entry->skeleton.ax_opcode); 658 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 659} 660 661void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) { 662 EmitPrefix(entry); 663 code_buffer_.push_back(entry->skeleton.opcode); 664 DCHECK_NE(0x0F, entry->skeleton.opcode); 665 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 666 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 667 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 668 DCHECK_EQ(0, entry->skeleton.ax_opcode); 669 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 670} 671 672void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, 673 int scale, int disp) { 674 EmitPrefixAndOpcode(entry); 675 EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp); 676 DCHECK_EQ(0, entry->skeleton.ax_opcode); 677 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 678} 679 680void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, 681 uint8_t base, int disp, uint8_t reg) { 682 EmitPrefixAndOpcode(entry); 683 if (X86_FPREG(reg)) { 684 reg = reg & X86_FP_REG_MASK; 685 } 686 if (reg >= 4) { 687 DCHECK(strchr(entry->name, '8') == NULL || 688 entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM) 689 << entry->name << " " << static_cast<int>(reg) 690 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 691 } 692 EmitModrmDisp(reg, base, disp); 693 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 694 DCHECK_EQ(0, entry->skeleton.ax_opcode); 695 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 696} 697 698void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, 699 uint8_t reg, uint8_t base, int disp) { 700 // Opcode will flip operands. 701 EmitMemReg(entry, base, disp, reg); 702} 703 704void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 705 int scale, int disp) { 706 EmitPrefixAndOpcode(entry); 707 if (X86_FPREG(reg)) { 708 reg = reg & X86_FP_REG_MASK; 709 } 710 EmitModrmSibDisp(reg, base, index, scale, disp); 711 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 712 DCHECK_EQ(0, entry->skeleton.ax_opcode); 713 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 714} 715 716void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 717 uint8_t reg) { 718 // Opcode will flip operands. 719 EmitRegArray(entry, reg, base, index, scale, disp); 720} 721 722void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) { 723 DCHECK_NE(entry->skeleton.prefix1, 0); 724 EmitPrefixAndOpcode(entry); 725 if (X86_FPREG(reg)) { 726 reg = reg & X86_FP_REG_MASK; 727 } 728 if (reg >= 4) { 729 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 730 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 731 } 732 DCHECK_LT(reg, 8); 733 uint8_t modrm = (0 << 6) | (reg << 3) | rBP; 734 code_buffer_.push_back(modrm); 735 code_buffer_.push_back(disp & 0xFF); 736 code_buffer_.push_back((disp >> 8) & 0xFF); 737 code_buffer_.push_back((disp >> 16) & 0xFF); 738 code_buffer_.push_back((disp >> 24) & 0xFF); 739 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 740 DCHECK_EQ(0, entry->skeleton.ax_opcode); 741 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 742} 743 744void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { 745 EmitPrefixAndOpcode(entry); 746 if (X86_FPREG(reg1)) { 747 reg1 = reg1 & X86_FP_REG_MASK; 748 } 749 if (X86_FPREG(reg2)) { 750 reg2 = reg2 & X86_FP_REG_MASK; 751 } 752 DCHECK_LT(reg1, 8); 753 DCHECK_LT(reg2, 8); 754 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 755 code_buffer_.push_back(modrm); 756 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 757 DCHECK_EQ(0, entry->skeleton.ax_opcode); 758 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 759} 760 761void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, 762 uint8_t reg1, uint8_t reg2, int32_t imm) { 763 EmitPrefixAndOpcode(entry); 764 if (X86_FPREG(reg1)) { 765 reg1 = reg1 & X86_FP_REG_MASK; 766 } 767 if (X86_FPREG(reg2)) { 768 reg2 = reg2 & X86_FP_REG_MASK; 769 } 770 DCHECK_LT(reg1, 8); 771 DCHECK_LT(reg2, 8); 772 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 773 code_buffer_.push_back(modrm); 774 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 775 DCHECK_EQ(0, entry->skeleton.ax_opcode); 776 EmitImm(entry, imm); 777} 778 779void X86Mir2Lir::EmitRegRegImmRev(const X86EncodingMap* entry, 780 uint8_t reg1, uint8_t reg2, int32_t imm) { 781 EmitRegRegImm(entry, reg2, reg1, imm); 782} 783 784void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, 785 uint8_t reg, uint8_t base, int disp, int32_t imm) { 786 EmitPrefixAndOpcode(entry); 787 DCHECK(!X86_FPREG(reg)); 788 DCHECK_LT(reg, 8); 789 EmitModrmDisp(reg, base, disp); 790 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 791 DCHECK_EQ(0, entry->skeleton.ax_opcode); 792 EmitImm(entry, imm); 793} 794 795void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 796 if (entry->skeleton.prefix1 != 0) { 797 code_buffer_.push_back(entry->skeleton.prefix1); 798 if (entry->skeleton.prefix2 != 0) { 799 code_buffer_.push_back(entry->skeleton.prefix2); 800 } 801 } else { 802 DCHECK_EQ(0, entry->skeleton.prefix2); 803 } 804 if (reg == rAX && entry->skeleton.ax_opcode != 0) { 805 code_buffer_.push_back(entry->skeleton.ax_opcode); 806 } else { 807 EmitOpcode(entry); 808 if (X86_FPREG(reg)) { 809 reg = reg & X86_FP_REG_MASK; 810 } 811 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 812 code_buffer_.push_back(modrm); 813 } 814 EmitImm(entry, imm); 815} 816 817void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) { 818 EmitPrefixAndOpcode(entry); 819 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 820 DCHECK_EQ(0, entry->skeleton.ax_opcode); 821 EmitImm(entry, imm); 822} 823 824void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) { 825 EmitPrefixAndOpcode(entry); 826 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 827 code_buffer_.push_back(modrm); 828 code_buffer_.push_back(disp & 0xFF); 829 code_buffer_.push_back((disp >> 8) & 0xFF); 830 code_buffer_.push_back((disp >> 16) & 0xFF); 831 code_buffer_.push_back((disp >> 24) & 0xFF); 832 EmitImm(entry, imm); 833 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 834} 835 836void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 837 DCHECK_LT(reg, 8); 838 code_buffer_.push_back(0xB8 + reg); 839 code_buffer_.push_back(imm & 0xFF); 840 code_buffer_.push_back((imm >> 8) & 0xFF); 841 code_buffer_.push_back((imm >> 16) & 0xFF); 842 code_buffer_.push_back((imm >> 24) & 0xFF); 843} 844 845void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 846 EmitPrefix(entry); 847 if (imm != 1) { 848 code_buffer_.push_back(entry->skeleton.opcode); 849 } else { 850 // Shorter encoding for 1 bit shift 851 code_buffer_.push_back(entry->skeleton.ax_opcode); 852 } 853 DCHECK_NE(0x0F, entry->skeleton.opcode); 854 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 855 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 856 if (reg >= 4) { 857 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 858 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 859 } 860 DCHECK_LT(reg, 8); 861 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 862 code_buffer_.push_back(modrm); 863 if (imm != 1) { 864 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 865 DCHECK(IS_SIMM8(imm)); 866 code_buffer_.push_back(imm & 0xFF); 867 } 868} 869 870void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) { 871 DCHECK_EQ(cl, static_cast<uint8_t>(rCX)); 872 EmitPrefix(entry); 873 code_buffer_.push_back(entry->skeleton.opcode); 874 DCHECK_NE(0x0F, entry->skeleton.opcode); 875 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 876 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 877 DCHECK_LT(reg, 8); 878 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 879 code_buffer_.push_back(modrm); 880 DCHECK_EQ(0, entry->skeleton.ax_opcode); 881 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 882} 883 884void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, 885 int displacement, uint8_t cl) { 886 DCHECK_EQ(cl, static_cast<uint8_t>(rCX)); 887 EmitPrefix(entry); 888 code_buffer_.push_back(entry->skeleton.opcode); 889 DCHECK_NE(0x0F, entry->skeleton.opcode); 890 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 891 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 892 DCHECK_LT(base, 8); 893 EmitModrmDisp(entry->skeleton.modrm_opcode, base, displacement); 894 DCHECK_EQ(0, entry->skeleton.ax_opcode); 895 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 896} 897 898void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) { 899 if (entry->skeleton.prefix1 != 0) { 900 code_buffer_.push_back(entry->skeleton.prefix1); 901 if (entry->skeleton.prefix2 != 0) { 902 code_buffer_.push_back(entry->skeleton.prefix2); 903 } 904 } else { 905 DCHECK_EQ(0, entry->skeleton.prefix2); 906 } 907 DCHECK_EQ(0, entry->skeleton.ax_opcode); 908 DCHECK_EQ(0x0F, entry->skeleton.opcode); 909 code_buffer_.push_back(0x0F); 910 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 911 code_buffer_.push_back(0x90 | condition); 912 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 913 DCHECK_LT(reg, 8); 914 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 915 code_buffer_.push_back(modrm); 916 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 917} 918 919void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition) { 920 // Generate prefix and opcode without the condition 921 EmitPrefixAndOpcode(entry); 922 923 // Now add the condition. The last byte of opcode is the one that receives it. 924 DCHECK_LE(condition, 0xF); 925 code_buffer_.back() += condition; 926 927 // Not expecting to have to encode immediate or do anything special for ModR/M since there are two registers. 928 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 929 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 930 931 // Check that registers requested for encoding are sane. 932 DCHECK_LT(reg1, 8); 933 DCHECK_LT(reg2, 8); 934 935 // For register to register encoding, the mod is 3. 936 const uint8_t mod = (3 << 6); 937 938 // Encode the ModR/M byte now. 939 const uint8_t modrm = mod | (reg1 << 3) | reg2; 940 code_buffer_.push_back(modrm); 941} 942 943void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) { 944 if (entry->opcode == kX86Jmp8) { 945 DCHECK(IS_SIMM8(rel)); 946 code_buffer_.push_back(0xEB); 947 code_buffer_.push_back(rel & 0xFF); 948 } else if (entry->opcode == kX86Jmp32) { 949 code_buffer_.push_back(0xE9); 950 code_buffer_.push_back(rel & 0xFF); 951 code_buffer_.push_back((rel >> 8) & 0xFF); 952 code_buffer_.push_back((rel >> 16) & 0xFF); 953 code_buffer_.push_back((rel >> 24) & 0xFF); 954 } else { 955 DCHECK(entry->opcode == kX86JmpR); 956 code_buffer_.push_back(entry->skeleton.opcode); 957 uint8_t reg = static_cast<uint8_t>(rel); 958 DCHECK_LT(reg, 8); 959 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 960 code_buffer_.push_back(modrm); 961 } 962} 963 964void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) { 965 DCHECK_LT(cc, 16); 966 if (entry->opcode == kX86Jcc8) { 967 DCHECK(IS_SIMM8(rel)); 968 code_buffer_.push_back(0x70 | cc); 969 code_buffer_.push_back(rel & 0xFF); 970 } else { 971 DCHECK(entry->opcode == kX86Jcc32); 972 code_buffer_.push_back(0x0F); 973 code_buffer_.push_back(0x80 | cc); 974 code_buffer_.push_back(rel & 0xFF); 975 code_buffer_.push_back((rel >> 8) & 0xFF); 976 code_buffer_.push_back((rel >> 16) & 0xFF); 977 code_buffer_.push_back((rel >> 24) & 0xFF); 978 } 979} 980 981void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) { 982 EmitPrefixAndOpcode(entry); 983 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 984 DCHECK_EQ(0, entry->skeleton.ax_opcode); 985 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 986} 987 988void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) { 989 DCHECK_NE(entry->skeleton.prefix1, 0); 990 EmitPrefixAndOpcode(entry); 991 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 992 code_buffer_.push_back(modrm); 993 code_buffer_.push_back(disp & 0xFF); 994 code_buffer_.push_back((disp >> 8) & 0xFF); 995 code_buffer_.push_back((disp >> 16) & 0xFF); 996 code_buffer_.push_back((disp >> 24) & 0xFF); 997 DCHECK_EQ(0, entry->skeleton.ax_opcode); 998 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 999} 1000 1001void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg, 1002 int base_or_table, uint8_t index, int scale, int table_or_disp) { 1003 int disp; 1004 if (entry->opcode == kX86PcRelLoadRA) { 1005 Mir2Lir::EmbeddedData *tab_rec = 1006 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 1007 disp = tab_rec->offset; 1008 } else { 1009 DCHECK(entry->opcode == kX86PcRelAdr); 1010 Mir2Lir::EmbeddedData *tab_rec = 1011 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table)); 1012 disp = tab_rec->offset; 1013 } 1014 EmitPrefix(entry); 1015 if (X86_FPREG(reg)) { 1016 reg = reg & X86_FP_REG_MASK; 1017 } 1018 DCHECK_LT(reg, 8); 1019 if (entry->opcode == kX86PcRelLoadRA) { 1020 code_buffer_.push_back(entry->skeleton.opcode); 1021 DCHECK_NE(0x0F, entry->skeleton.opcode); 1022 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1023 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1024 uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP; 1025 code_buffer_.push_back(modrm); 1026 DCHECK_LT(scale, 4); 1027 DCHECK_LT(index, 8); 1028 DCHECK_LT(base_or_table, 8); 1029 uint8_t base = static_cast<uint8_t>(base_or_table); 1030 uint8_t sib = (scale << 6) | (index << 3) | base; 1031 code_buffer_.push_back(sib); 1032 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1033 } else { 1034 code_buffer_.push_back(entry->skeleton.opcode + reg); 1035 } 1036 code_buffer_.push_back(disp & 0xFF); 1037 code_buffer_.push_back((disp >> 8) & 0xFF); 1038 code_buffer_.push_back((disp >> 16) & 0xFF); 1039 code_buffer_.push_back((disp >> 24) & 0xFF); 1040 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1041 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1042} 1043 1044void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) { 1045 DCHECK(entry->opcode == kX86StartOfMethod) << entry->name; 1046 code_buffer_.push_back(0xE8); // call +0 1047 code_buffer_.push_back(0); 1048 code_buffer_.push_back(0); 1049 code_buffer_.push_back(0); 1050 code_buffer_.push_back(0); 1051 1052 DCHECK_LT(reg, 8); 1053 code_buffer_.push_back(0x58 + reg); // pop reg 1054 1055 EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */); 1056} 1057 1058void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 1059 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 1060 << BuildInsnString(entry->fmt, lir, 0); 1061 for (int i = 0; i < GetInsnSize(lir); ++i) { 1062 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 1063 } 1064} 1065 1066/* 1067 * Assemble the LIR into binary instruction format. Note that we may 1068 * discover that pc-relative displacements may not fit the selected 1069 * instruction. In those cases we will try to substitute a new code 1070 * sequence or request that the trace be shortened and retried. 1071 */ 1072AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 1073 LIR *lir; 1074 AssemblerStatus res = kSuccess; // Assume success 1075 1076 const bool kVerbosePcFixup = false; 1077 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1078 if (IsPseudoLirOp(lir->opcode)) { 1079 continue; 1080 } 1081 1082 if (lir->flags.is_nop) { 1083 continue; 1084 } 1085 1086 if (lir->flags.fixup != kFixupNone) { 1087 switch (lir->opcode) { 1088 case kX86Jcc8: { 1089 LIR *target_lir = lir->target; 1090 DCHECK(target_lir != NULL); 1091 int delta = 0; 1092 CodeOffset pc; 1093 if (IS_SIMM8(lir->operands[0])) { 1094 pc = lir->offset + 2 /* opcode + rel8 */; 1095 } else { 1096 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1097 } 1098 CodeOffset target = target_lir->offset; 1099 delta = target - pc; 1100 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1101 if (kVerbosePcFixup) { 1102 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1103 << " delta: " << delta << " old delta: " << lir->operands[0]; 1104 } 1105 lir->opcode = kX86Jcc32; 1106 SetupResourceMasks(lir); 1107 res = kRetryAll; 1108 } 1109 if (kVerbosePcFixup) { 1110 LOG(INFO) << "Source:"; 1111 DumpLIRInsn(lir, 0); 1112 LOG(INFO) << "Target:"; 1113 DumpLIRInsn(target_lir, 0); 1114 LOG(INFO) << "Delta " << delta; 1115 } 1116 lir->operands[0] = delta; 1117 break; 1118 } 1119 case kX86Jcc32: { 1120 LIR *target_lir = lir->target; 1121 DCHECK(target_lir != NULL); 1122 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1123 CodeOffset target = target_lir->offset; 1124 int delta = target - pc; 1125 if (kVerbosePcFixup) { 1126 LOG(INFO) << "Source:"; 1127 DumpLIRInsn(lir, 0); 1128 LOG(INFO) << "Target:"; 1129 DumpLIRInsn(target_lir, 0); 1130 LOG(INFO) << "Delta " << delta; 1131 } 1132 lir->operands[0] = delta; 1133 break; 1134 } 1135 case kX86Jmp8: { 1136 LIR *target_lir = lir->target; 1137 DCHECK(target_lir != NULL); 1138 int delta = 0; 1139 CodeOffset pc; 1140 if (IS_SIMM8(lir->operands[0])) { 1141 pc = lir->offset + 2 /* opcode + rel8 */; 1142 } else { 1143 pc = lir->offset + 5 /* opcode + rel32 */; 1144 } 1145 CodeOffset target = target_lir->offset; 1146 delta = target - pc; 1147 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1148 // Useless branch 1149 NopLIR(lir); 1150 if (kVerbosePcFixup) { 1151 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1152 } 1153 res = kRetryAll; 1154 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1155 if (kVerbosePcFixup) { 1156 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1157 } 1158 lir->opcode = kX86Jmp32; 1159 SetupResourceMasks(lir); 1160 res = kRetryAll; 1161 } 1162 lir->operands[0] = delta; 1163 break; 1164 } 1165 case kX86Jmp32: { 1166 LIR *target_lir = lir->target; 1167 DCHECK(target_lir != NULL); 1168 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1169 CodeOffset target = target_lir->offset; 1170 int delta = target - pc; 1171 lir->operands[0] = delta; 1172 break; 1173 } 1174 default: 1175 if (lir->flags.fixup == kFixupLoad) { 1176 LIR *target_lir = lir->target; 1177 DCHECK(target_lir != NULL); 1178 CodeOffset target = target_lir->offset; 1179 lir->operands[2] = target; 1180 int newSize = GetInsnSize(lir); 1181 if (newSize != lir->flags.size) { 1182 lir->flags.size = newSize; 1183 res = kRetryAll; 1184 } 1185 } 1186 break; 1187 } 1188 } 1189 1190 /* 1191 * If one of the pc-relative instructions expanded we'll have 1192 * to make another pass. Don't bother to fully assemble the 1193 * instruction. 1194 */ 1195 if (res != kSuccess) { 1196 continue; 1197 } 1198 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1199 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1200 size_t starting_cbuf_size = code_buffer_.size(); 1201 switch (entry->kind) { 1202 case kData: // 4 bytes of data 1203 code_buffer_.push_back(lir->operands[0]); 1204 break; 1205 case kNullary: // 1 byte of opcode 1206 DCHECK_EQ(0, entry->skeleton.prefix1); 1207 DCHECK_EQ(0, entry->skeleton.prefix2); 1208 EmitOpcode(entry); 1209 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1210 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1211 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1212 break; 1213 case kRegOpcode: // lir operands - 0: reg 1214 EmitOpRegOpcode(entry, lir->operands[0]); 1215 break; 1216 case kReg: // lir operands - 0: reg 1217 EmitOpReg(entry, lir->operands[0]); 1218 break; 1219 case kMem: // lir operands - 0: base, 1: disp 1220 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1221 break; 1222 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 1223 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); 1224 break; 1225 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1226 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1227 break; 1228 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 1229 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1230 break; 1231 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1232 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1233 lir->operands[3], lir->operands[4]); 1234 break; 1235 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1236 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1237 break; 1238 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1239 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1240 lir->operands[3], lir->operands[4]); 1241 break; 1242 case kRegThread: // lir operands - 0: reg, 1: disp 1243 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1244 break; 1245 case kRegReg: // lir operands - 0: reg1, 1: reg2 1246 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1247 break; 1248 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1249 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1250 break; 1251 case kRegRegImmRev: 1252 EmitRegRegImmRev(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1253 break; 1254 case kRegRegImm: 1255 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1256 break; 1257 case kRegMemImm: 1258 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1259 lir->operands[3]); 1260 break; 1261 case kRegImm: // lir operands - 0: reg, 1: immediate 1262 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1263 break; 1264 case kThreadImm: // lir operands - 0: disp, 1: immediate 1265 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1266 break; 1267 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1268 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1269 break; 1270 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1271 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1272 break; 1273 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1274 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1275 break; 1276 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl 1277 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1278 break; 1279 case kRegCond: // lir operands - 0: reg, 1: condition 1280 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1281 break; 1282 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition 1283 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1284 break; 1285 case kJmp: // lir operands - 0: rel 1286 EmitJmp(entry, lir->operands[0]); 1287 break; 1288 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1289 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1290 break; 1291 case kCall: 1292 switch (entry->opcode) { 1293 case kX86CallM: // lir operands - 0: base, 1: disp 1294 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1295 break; 1296 case kX86CallT: // lir operands - 0: disp 1297 EmitCallThread(entry, lir->operands[0]); 1298 break; 1299 default: 1300 EmitUnimplemented(entry, lir); 1301 break; 1302 } 1303 break; 1304 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1305 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1306 lir->operands[3], lir->operands[4]); 1307 break; 1308 case kMacro: 1309 EmitMacro(entry, lir->operands[0], lir->offset); 1310 break; 1311 default: 1312 EmitUnimplemented(entry, lir); 1313 break; 1314 } 1315 CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)), 1316 code_buffer_.size() - starting_cbuf_size) 1317 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1318 } 1319 return res; 1320} 1321 1322// LIR offset assignment. 1323// TODO: consolidate w/ Arm assembly mechanism. 1324int X86Mir2Lir::AssignInsnOffsets() { 1325 LIR* lir; 1326 int offset = 0; 1327 1328 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1329 lir->offset = offset; 1330 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1331 if (!lir->flags.is_nop) { 1332 offset += lir->flags.size; 1333 } 1334 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1335 if (offset & 0x2) { 1336 offset += 2; 1337 lir->operands[0] = 1; 1338 } else { 1339 lir->operands[0] = 0; 1340 } 1341 } 1342 /* Pseudo opcodes don't consume space */ 1343 } 1344 return offset; 1345} 1346 1347/* 1348 * Walk the compilation unit and assign offsets to instructions 1349 * and literals and compute the total size of the compiled unit. 1350 * TODO: consolidate w/ Arm assembly mechanism. 1351 */ 1352void X86Mir2Lir::AssignOffsets() { 1353 int offset = AssignInsnOffsets(); 1354 1355 /* Const values have to be word aligned */ 1356 offset = (offset + 3) & ~3; 1357 1358 /* Set up offsets for literals */ 1359 data_offset_ = offset; 1360 1361 offset = AssignLiteralOffset(offset); 1362 1363 offset = AssignSwitchTablesOffset(offset); 1364 1365 offset = AssignFillArrayDataOffset(offset); 1366 1367 total_size_ = offset; 1368} 1369 1370/* 1371 * Go over each instruction in the list and calculate the offset from the top 1372 * before sending them off to the assembler. If out-of-range branch distance is 1373 * seen rearrange the instructions a bit to correct it. 1374 * TODO: consolidate w/ Arm assembly mechanism. 1375 */ 1376void X86Mir2Lir::AssembleLIR() { 1377 cu_->NewTimingSplit("Assemble"); 1378 AssignOffsets(); 1379 int assembler_retries = 0; 1380 /* 1381 * Assemble here. Note that we generate code with optimistic assumptions 1382 * and if found now to work, we'll have to redo the sequence and retry. 1383 */ 1384 1385 while (true) { 1386 AssemblerStatus res = AssembleInstructions(0); 1387 if (res == kSuccess) { 1388 break; 1389 } else { 1390 assembler_retries++; 1391 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1392 CodegenDump(); 1393 LOG(FATAL) << "Assembler error - too many retries"; 1394 } 1395 // Redo offsets and try again 1396 AssignOffsets(); 1397 code_buffer_.clear(); 1398 } 1399 } 1400 1401 // Install literals 1402 InstallLiteralPools(); 1403 1404 // Install switch tables 1405 InstallSwitchTables(); 1406 1407 // Install fill array data 1408 InstallFillArrayData(); 1409 1410 // Create the mapping table and native offset to reference map. 1411 cu_->NewTimingSplit("PcMappingTable"); 1412 CreateMappingTables(); 1413 1414 cu_->NewTimingSplit("GcMap"); 1415 CreateNativeGcMap(); 1416} 1417 1418} // namespace art 1419