assemble_x86.cc revision 343adb52d3f031b6b5e005ff51f9cb04df219b21
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "x86_lir.h" 20 21namespace art { 22 23#define MAX_ASSEMBLER_RETRIES 50 24 25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" }, 28 { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, 29 30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \ 40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \ 41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \ 45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \ 52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \ 53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \ 57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \ 60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \ 61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \ 68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \ 69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \ 73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \ 76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \ 77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" } 80 81ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 82 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 83 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 84 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 85 0x80, 0x0 /* RegMem8/imm8 */, 86 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 87ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 88 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 89 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 90 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 91 0x80, 0x1 /* RegMem8/imm8 */, 92 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 93ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 94 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 95 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 96 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 97 0x80, 0x2 /* RegMem8/imm8 */, 98 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 99ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 100 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 101 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 102 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 103 0x80, 0x3 /* RegMem8/imm8 */, 104 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 105ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 106 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 107 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 108 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 109 0x80, 0x4 /* RegMem8/imm8 */, 110 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 111ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 112 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 113 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 114 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 115 0x80, 0x5 /* RegMem8/imm8 */, 116 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 117ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 118 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 119 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 120 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 121 0x80, 0x6 /* RegMem8/imm8 */, 122 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 123ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 124 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 125 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 126 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 127 0x80, 0x7 /* RegMem8/imm8 */, 128 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 129#undef ENCODING_MAP 130 131 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" }, 132 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 133 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 134 135 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" }, 136 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 137 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 138 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" }, 139 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 140 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 141 142 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" }, 143 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 144 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" }, 145 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" }, 146 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" }, 147 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 148 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" }, 149 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" }, 150 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" }, 151 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 152 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" }, 153 154 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" }, 155 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 156 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" }, 157 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" }, 158 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" }, 159 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 160 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" }, 161 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" }, 162 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" }, 163 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 164 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" }, 165 166 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" }, 167 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 168 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" }, 169 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" }, 170 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" }, 171 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 172 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" }, 173 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" }, 174 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" }, 175 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 176 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" }, 177 178 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 179 180#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 181{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \ 182{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 183{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 184{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \ 185{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \ 186{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 187 \ 188{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \ 189{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 190{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 191{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \ 192{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \ 193{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 194 \ 195{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \ 196{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 197{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 198{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \ 199{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \ 200{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" } 201 202 SHIFT_ENCODING_MAP(Rol, 0x0), 203 SHIFT_ENCODING_MAP(Ror, 0x1), 204 SHIFT_ENCODING_MAP(Rcl, 0x2), 205 SHIFT_ENCODING_MAP(Rcr, 0x3), 206 SHIFT_ENCODING_MAP(Sal, 0x4), 207 SHIFT_ENCODING_MAP(Shr, 0x5), 208 SHIFT_ENCODING_MAP(Sar, 0x7), 209#undef SHIFT_ENCODING_MAP 210 211 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" }, 212 213 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" }, 214 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" }, 215 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 216 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" }, 217 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" }, 218 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 219 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" }, 220 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" }, 221 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 222 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" }, 223 224#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 225 reg, reg_kind, reg_flags, \ 226 mem, mem_kind, mem_flags, \ 227 arr, arr_kind, arr_flags, imm, \ 228 b_flags, hw_flags, w_flags, \ 229 b_format, hw_format, w_format) \ 230{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \ 231{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \ 232{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \ 233{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \ 234{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \ 235{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \ 236{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \ 237{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \ 238{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" } 239 240 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 241 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 242 243 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 244 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 245 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 246 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 247#undef UNARY_ENCODING_MAP 248 249 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" }, 250 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0 }, "Push32R", "!0r" }, 251 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0 }, "Pop32R", "!0r" }, 252 253#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 254{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ 255{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ 256{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 257 258 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 259 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" }, 260 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 261 262 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 263 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" }, 264 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 265 266 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 267 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 268 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 269 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 270 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 271 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 272 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES), 273 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES), 274 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES), 275 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES), 276 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0), 277 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0), 278 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0), 279 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0), 280 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0), 281 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0), 282 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 283 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 284 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0), 285 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0), 286 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0), 287 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0), 288 289 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" }, 290 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" }, 291 { kX86SqrtsdRR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0xF2, 0, 0x0F, 0x51, 0, 0, 0, 0 }, "SqrtsdRR", "!0r,!1r" }, 292 { kX86FstpdM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0 }, "FstpdM", "[!0r,!1d]" }, 293 294 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 295 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" }, 296 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" }, 297 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 298 299 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" }, 300 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" }, 301 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 302 303 // TODO: load/store? 304 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 305 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" }, 306 307 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES), 308 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES), 309 310 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" }, 311 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" }, 312 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 313 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 314 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 315 { kX86LockCmpxchg8bM, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1d]" }, 316 { kX86LockCmpxchg8bA, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0 }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, 317 318 EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 319 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 320 EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 321 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 322#undef EXT_0F_ENCODING_MAP 323 324 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" }, 325 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" }, 326 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" }, 327 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" }, 328 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" }, 329 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" }, 330 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" }, 331 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 332 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" }, 333 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" }, 334 335 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" }, 336 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 337 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" }, 338}; 339 340static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) { 341 size_t size = 0; 342 if (entry->skeleton.prefix1 > 0) { 343 ++size; 344 if (entry->skeleton.prefix2 > 0) { 345 ++size; 346 } 347 } 348 ++size; // opcode 349 if (entry->skeleton.opcode == 0x0F) { 350 ++size; 351 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 352 ++size; 353 } 354 } 355 ++size; // modrm 356 if (has_sib || base == rX86_SP) { 357 // SP requires a SIB byte. 358 ++size; 359 } 360 if (displacement != 0 || base == rBP) { 361 // BP requires an explicit displacement, even when it's 0. 362 if (entry->opcode != kX86Lea32RA) { 363 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name; 364 } 365 size += IS_SIMM8(displacement) ? 1 : 4; 366 } 367 size += entry->skeleton.immediate_bytes; 368 return size; 369} 370 371int X86Mir2Lir::GetInsnSize(LIR* lir) { 372 DCHECK(!IsPseudoLirOp(lir->opcode)); 373 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 374 switch (entry->kind) { 375 case kData: 376 return 4; // 4 bytes of data 377 case kNop: 378 return lir->operands[0]; // length of nop is sole operand 379 case kNullary: 380 return 1; // 1 byte of opcode 381 case kRegOpcode: // lir operands - 0: reg 382 return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm 383 case kReg: // lir operands - 0: reg 384 return ComputeSize(entry, 0, 0, false); 385 case kMem: // lir operands - 0: base, 1: disp 386 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 387 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 388 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 389 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 390 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 391 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 392 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 393 case kThreadReg: // lir operands - 0: disp, 1: reg 394 return ComputeSize(entry, 0, lir->operands[0], false); 395 case kRegReg: 396 return ComputeSize(entry, 0, 0, false); 397 case kRegRegStore: 398 return ComputeSize(entry, 0, 0, false); 399 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 400 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 401 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 402 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 403 case kRegThread: // lir operands - 0: reg, 1: disp 404 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 405 case kRegImm: { // lir operands - 0: reg, 1: immediate 406 size_t size = ComputeSize(entry, 0, 0, false); 407 if (entry->skeleton.ax_opcode == 0) { 408 return size; 409 } else { 410 // AX opcodes don't require the modrm byte. 411 int reg = lir->operands[0]; 412 return size - (reg == rAX ? 1 : 0); 413 } 414 } 415 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 416 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 417 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 418 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 419 case kThreadImm: // lir operands - 0: disp, 1: imm 420 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 421 case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm 422 return ComputeSize(entry, 0, 0, false); 423 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 424 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 425 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 426 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 427 case kMovRegImm: // lir operands - 0: reg, 1: immediate 428 return 1 + entry->skeleton.immediate_bytes; 429 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 430 // Shift by immediate one has a shorter opcode. 431 return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0); 432 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 433 // Shift by immediate one has a shorter opcode. 434 return ComputeSize(entry, lir->operands[0], lir->operands[1], false) - 435 (lir->operands[2] == 1 ? 1 : 0); 436 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 437 // Shift by immediate one has a shorter opcode. 438 return ComputeSize(entry, lir->operands[0], lir->operands[3], true) - 439 (lir->operands[4] == 1 ? 1 : 0); 440 case kShiftRegCl: 441 return ComputeSize(entry, 0, 0, false); 442 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 443 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 444 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 445 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 446 case kRegCond: // lir operands - 0: reg, 1: cond 447 return ComputeSize(entry, 0, 0, false); 448 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 449 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 450 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 451 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 452 case kJcc: 453 if (lir->opcode == kX86Jcc8) { 454 return 2; // opcode + rel8 455 } else { 456 DCHECK(lir->opcode == kX86Jcc32); 457 return 6; // 2 byte opcode + rel32 458 } 459 case kJmp: 460 if (lir->opcode == kX86Jmp8) { 461 return 2; // opcode + rel8 462 } else if (lir->opcode == kX86Jmp32) { 463 return 5; // opcode + rel32 464 } else { 465 DCHECK(lir->opcode == kX86JmpR); 466 return 2; // opcode + modrm 467 } 468 case kCall: 469 switch (lir->opcode) { 470 case kX86CallR: return 2; // opcode modrm 471 case kX86CallM: // lir operands - 0: base, 1: disp 472 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 473 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 474 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 475 case kX86CallT: // lir operands - 0: disp 476 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 477 default: 478 break; 479 } 480 break; 481 case kPcRel: 482 if (entry->opcode == kX86PcRelLoadRA) { 483 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 484 return ComputeSize(entry, lir->operands[1], 0x12345678, true); 485 } else { 486 DCHECK(entry->opcode == kX86PcRelAdr); 487 return 5; // opcode with reg + 4 byte immediate 488 } 489 case kMacro: 490 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 491 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 492 ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) - 493 (lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding 494 default: 495 break; 496 } 497 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 498 return 0; 499} 500 501void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry) { 502 if (entry->skeleton.prefix1 != 0) { 503 code_buffer_.push_back(entry->skeleton.prefix1); 504 if (entry->skeleton.prefix2 != 0) { 505 code_buffer_.push_back(entry->skeleton.prefix2); 506 } 507 } else { 508 DCHECK_EQ(0, entry->skeleton.prefix2); 509 } 510} 511 512void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { 513 code_buffer_.push_back(entry->skeleton.opcode); 514 if (entry->skeleton.opcode == 0x0F) { 515 code_buffer_.push_back(entry->skeleton.extra_opcode1); 516 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 517 code_buffer_.push_back(entry->skeleton.extra_opcode2); 518 } else { 519 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 520 } 521 } else { 522 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 523 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 524 } 525} 526 527void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry) { 528 EmitPrefix(entry); 529 EmitOpcode(entry); 530} 531 532static uint8_t ModrmForDisp(int base, int disp) { 533 // BP requires an explicit disp, so do not omit it in the 0 case 534 if (disp == 0 && base != rBP) { 535 return 0; 536 } else if (IS_SIMM8(disp)) { 537 return 1; 538 } else { 539 return 2; 540 } 541} 542 543void X86Mir2Lir::EmitDisp(uint8_t base, int disp) { 544 // BP requires an explicit disp, so do not omit it in the 0 case 545 if (disp == 0 && base != rBP) { 546 return; 547 } else if (IS_SIMM8(disp)) { 548 code_buffer_.push_back(disp & 0xFF); 549 } else { 550 code_buffer_.push_back(disp & 0xFF); 551 code_buffer_.push_back((disp >> 8) & 0xFF); 552 code_buffer_.push_back((disp >> 16) & 0xFF); 553 code_buffer_.push_back((disp >> 24) & 0xFF); 554 } 555} 556 557void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp) { 558 DCHECK_LT(reg_or_opcode, 8); 559 DCHECK_LT(base, 8); 560 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; 561 code_buffer_.push_back(modrm); 562 if (base == rX86_SP) { 563 // Special SIB for SP base 564 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); 565 } 566 EmitDisp(base, disp); 567} 568 569void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, 570 int scale, int disp) { 571 DCHECK_LT(reg_or_opcode, 8); 572 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | rX86_SP; 573 code_buffer_.push_back(modrm); 574 DCHECK_LT(scale, 4); 575 DCHECK_LT(index, 8); 576 DCHECK_LT(base, 8); 577 uint8_t sib = (scale << 6) | (index << 3) | base; 578 code_buffer_.push_back(sib); 579 EmitDisp(base, disp); 580} 581 582void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int imm) { 583 switch (entry->skeleton.immediate_bytes) { 584 case 1: 585 DCHECK(IS_SIMM8(imm)); 586 code_buffer_.push_back(imm & 0xFF); 587 break; 588 case 2: 589 DCHECK(IS_SIMM16(imm)); 590 code_buffer_.push_back(imm & 0xFF); 591 code_buffer_.push_back((imm >> 8) & 0xFF); 592 break; 593 case 4: 594 code_buffer_.push_back(imm & 0xFF); 595 code_buffer_.push_back((imm >> 8) & 0xFF); 596 code_buffer_.push_back((imm >> 16) & 0xFF); 597 code_buffer_.push_back((imm >> 24) & 0xFF); 598 break; 599 default: 600 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 601 << ") for instruction: " << entry->name; 602 break; 603 } 604} 605 606void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) { 607 EmitPrefixAndOpcode(entry); 608 // There's no 3-byte instruction with +rd 609 DCHECK(entry->skeleton.opcode != 0x0F || 610 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); 611 DCHECK(!X86_FPREG(reg)); 612 DCHECK_LT(reg, 8); 613 code_buffer_.back() += reg; 614 DCHECK_EQ(0, entry->skeleton.ax_opcode); 615 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 616} 617 618void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) { 619 EmitPrefixAndOpcode(entry); 620 if (X86_FPREG(reg)) { 621 reg = reg & X86_FP_REG_MASK; 622 } 623 if (reg >= 4) { 624 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 625 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 626 } 627 DCHECK_LT(reg, 8); 628 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 629 code_buffer_.push_back(modrm); 630 DCHECK_EQ(0, entry->skeleton.ax_opcode); 631 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 632} 633 634void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) { 635 EmitPrefix(entry); 636 code_buffer_.push_back(entry->skeleton.opcode); 637 DCHECK_NE(0x0F, entry->skeleton.opcode); 638 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 639 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 640 DCHECK_NE(rX86_SP, base); 641 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 642 DCHECK_EQ(0, entry->skeleton.ax_opcode); 643 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 644} 645 646void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, 647 int scale, int disp) { 648 EmitPrefixAndOpcode(entry); 649 EmitModrmSibDisp(entry->skeleton.modrm_opcode, base, index, scale, disp); 650 DCHECK_EQ(0, entry->skeleton.ax_opcode); 651 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 652} 653 654void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, 655 uint8_t base, int disp, uint8_t reg) { 656 EmitPrefixAndOpcode(entry); 657 if (X86_FPREG(reg)) { 658 reg = reg & X86_FP_REG_MASK; 659 } 660 if (reg >= 4) { 661 DCHECK(strchr(entry->name, '8') == NULL || 662 entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM) 663 << entry->name << " " << static_cast<int>(reg) 664 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 665 } 666 EmitModrmDisp(reg, base, disp); 667 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 668 DCHECK_EQ(0, entry->skeleton.ax_opcode); 669 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 670} 671 672void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, 673 uint8_t reg, uint8_t base, int disp) { 674 // Opcode will flip operands. 675 EmitMemReg(entry, base, disp, reg); 676} 677 678void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 679 int scale, int disp) { 680 EmitPrefixAndOpcode(entry); 681 if (X86_FPREG(reg)) { 682 reg = reg & X86_FP_REG_MASK; 683 } 684 EmitModrmSibDisp(reg, base, index, scale, disp); 685 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 686 DCHECK_EQ(0, entry->skeleton.ax_opcode); 687 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 688} 689 690void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 691 uint8_t reg) { 692 // Opcode will flip operands. 693 EmitRegArray(entry, reg, base, index, scale, disp); 694} 695 696void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) { 697 DCHECK_NE(entry->skeleton.prefix1, 0); 698 EmitPrefixAndOpcode(entry); 699 if (X86_FPREG(reg)) { 700 reg = reg & X86_FP_REG_MASK; 701 } 702 if (reg >= 4) { 703 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 704 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 705 } 706 DCHECK_LT(reg, 8); 707 uint8_t modrm = (0 << 6) | (reg << 3) | rBP; 708 code_buffer_.push_back(modrm); 709 code_buffer_.push_back(disp & 0xFF); 710 code_buffer_.push_back((disp >> 8) & 0xFF); 711 code_buffer_.push_back((disp >> 16) & 0xFF); 712 code_buffer_.push_back((disp >> 24) & 0xFF); 713 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 714 DCHECK_EQ(0, entry->skeleton.ax_opcode); 715 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 716} 717 718void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { 719 EmitPrefixAndOpcode(entry); 720 if (X86_FPREG(reg1)) { 721 reg1 = reg1 & X86_FP_REG_MASK; 722 } 723 if (X86_FPREG(reg2)) { 724 reg2 = reg2 & X86_FP_REG_MASK; 725 } 726 DCHECK_LT(reg1, 8); 727 DCHECK_LT(reg2, 8); 728 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 729 code_buffer_.push_back(modrm); 730 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 731 DCHECK_EQ(0, entry->skeleton.ax_opcode); 732 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 733} 734 735void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, 736 uint8_t reg1, uint8_t reg2, int32_t imm) { 737 EmitPrefixAndOpcode(entry); 738 if (X86_FPREG(reg1)) { 739 reg1 = reg1 & X86_FP_REG_MASK; 740 } 741 if (X86_FPREG(reg2)) { 742 reg2 = reg2 & X86_FP_REG_MASK; 743 } 744 DCHECK_LT(reg1, 8); 745 DCHECK_LT(reg2, 8); 746 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 747 code_buffer_.push_back(modrm); 748 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 749 DCHECK_EQ(0, entry->skeleton.ax_opcode); 750 EmitImm(entry, imm); 751} 752 753void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 754 if (entry->skeleton.prefix1 != 0) { 755 code_buffer_.push_back(entry->skeleton.prefix1); 756 if (entry->skeleton.prefix2 != 0) { 757 code_buffer_.push_back(entry->skeleton.prefix2); 758 } 759 } else { 760 DCHECK_EQ(0, entry->skeleton.prefix2); 761 } 762 if (reg == rAX && entry->skeleton.ax_opcode != 0) { 763 code_buffer_.push_back(entry->skeleton.ax_opcode); 764 } else { 765 EmitOpcode(entry); 766 if (X86_FPREG(reg)) { 767 reg = reg & X86_FP_REG_MASK; 768 } 769 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 770 code_buffer_.push_back(modrm); 771 } 772 EmitImm(entry, imm); 773} 774 775void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm) { 776 EmitPrefixAndOpcode(entry); 777 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 778 DCHECK_EQ(0, entry->skeleton.ax_opcode); 779 EmitImm(entry, imm); 780} 781 782void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) { 783 EmitPrefixAndOpcode(entry); 784 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 785 code_buffer_.push_back(modrm); 786 code_buffer_.push_back(disp & 0xFF); 787 code_buffer_.push_back((disp >> 8) & 0xFF); 788 code_buffer_.push_back((disp >> 16) & 0xFF); 789 code_buffer_.push_back((disp >> 24) & 0xFF); 790 EmitImm(entry, imm); 791 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 792} 793 794void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 795 DCHECK_LT(reg, 8); 796 code_buffer_.push_back(0xB8 + reg); 797 code_buffer_.push_back(imm & 0xFF); 798 code_buffer_.push_back((imm >> 8) & 0xFF); 799 code_buffer_.push_back((imm >> 16) & 0xFF); 800 code_buffer_.push_back((imm >> 24) & 0xFF); 801} 802 803void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 804 EmitPrefix(entry); 805 if (imm != 1) { 806 code_buffer_.push_back(entry->skeleton.opcode); 807 } else { 808 // Shorter encoding for 1 bit shift 809 code_buffer_.push_back(entry->skeleton.ax_opcode); 810 } 811 DCHECK_NE(0x0F, entry->skeleton.opcode); 812 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 813 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 814 if (reg >= 4) { 815 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 816 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 817 } 818 DCHECK_LT(reg, 8); 819 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 820 code_buffer_.push_back(modrm); 821 if (imm != 1) { 822 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 823 DCHECK(IS_SIMM8(imm)); 824 code_buffer_.push_back(imm & 0xFF); 825 } 826} 827 828void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) { 829 DCHECK_EQ(cl, static_cast<uint8_t>(rCX)); 830 EmitPrefix(entry); 831 code_buffer_.push_back(entry->skeleton.opcode); 832 DCHECK_NE(0x0F, entry->skeleton.opcode); 833 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 834 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 835 DCHECK_LT(reg, 8); 836 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 837 code_buffer_.push_back(modrm); 838 DCHECK_EQ(0, entry->skeleton.ax_opcode); 839 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 840} 841 842void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) { 843 if (entry->skeleton.prefix1 != 0) { 844 code_buffer_.push_back(entry->skeleton.prefix1); 845 if (entry->skeleton.prefix2 != 0) { 846 code_buffer_.push_back(entry->skeleton.prefix2); 847 } 848 } else { 849 DCHECK_EQ(0, entry->skeleton.prefix2); 850 } 851 DCHECK_EQ(0, entry->skeleton.ax_opcode); 852 DCHECK_EQ(0x0F, entry->skeleton.opcode); 853 code_buffer_.push_back(0x0F); 854 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 855 code_buffer_.push_back(0x90 | condition); 856 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 857 DCHECK_LT(reg, 8); 858 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 859 code_buffer_.push_back(modrm); 860 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 861} 862 863void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) { 864 if (entry->opcode == kX86Jmp8) { 865 DCHECK(IS_SIMM8(rel)); 866 code_buffer_.push_back(0xEB); 867 code_buffer_.push_back(rel & 0xFF); 868 } else if (entry->opcode == kX86Jmp32) { 869 code_buffer_.push_back(0xE9); 870 code_buffer_.push_back(rel & 0xFF); 871 code_buffer_.push_back((rel >> 8) & 0xFF); 872 code_buffer_.push_back((rel >> 16) & 0xFF); 873 code_buffer_.push_back((rel >> 24) & 0xFF); 874 } else { 875 DCHECK(entry->opcode == kX86JmpR); 876 code_buffer_.push_back(entry->skeleton.opcode); 877 uint8_t reg = static_cast<uint8_t>(rel); 878 DCHECK_LT(reg, 8); 879 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 880 code_buffer_.push_back(modrm); 881 } 882} 883 884void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) { 885 DCHECK_LT(cc, 16); 886 if (entry->opcode == kX86Jcc8) { 887 DCHECK(IS_SIMM8(rel)); 888 code_buffer_.push_back(0x70 | cc); 889 code_buffer_.push_back(rel & 0xFF); 890 } else { 891 DCHECK(entry->opcode == kX86Jcc32); 892 code_buffer_.push_back(0x0F); 893 code_buffer_.push_back(0x80 | cc); 894 code_buffer_.push_back(rel & 0xFF); 895 code_buffer_.push_back((rel >> 8) & 0xFF); 896 code_buffer_.push_back((rel >> 16) & 0xFF); 897 code_buffer_.push_back((rel >> 24) & 0xFF); 898 } 899} 900 901void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) { 902 EmitPrefixAndOpcode(entry); 903 EmitModrmDisp(entry->skeleton.modrm_opcode, base, disp); 904 DCHECK_EQ(0, entry->skeleton.ax_opcode); 905 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 906} 907 908void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) { 909 DCHECK_NE(entry->skeleton.prefix1, 0); 910 EmitPrefixAndOpcode(entry); 911 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 912 code_buffer_.push_back(modrm); 913 code_buffer_.push_back(disp & 0xFF); 914 code_buffer_.push_back((disp >> 8) & 0xFF); 915 code_buffer_.push_back((disp >> 16) & 0xFF); 916 code_buffer_.push_back((disp >> 24) & 0xFF); 917 DCHECK_EQ(0, entry->skeleton.ax_opcode); 918 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 919} 920 921void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg, 922 int base_or_table, uint8_t index, int scale, int table_or_disp) { 923 int disp; 924 if (entry->opcode == kX86PcRelLoadRA) { 925 Mir2Lir::EmbeddedData *tab_rec = 926 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 927 disp = tab_rec->offset; 928 } else { 929 DCHECK(entry->opcode == kX86PcRelAdr); 930 Mir2Lir::EmbeddedData *tab_rec = 931 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table)); 932 disp = tab_rec->offset; 933 } 934 EmitPrefix(entry); 935 if (X86_FPREG(reg)) { 936 reg = reg & X86_FP_REG_MASK; 937 } 938 DCHECK_LT(reg, 8); 939 if (entry->opcode == kX86PcRelLoadRA) { 940 code_buffer_.push_back(entry->skeleton.opcode); 941 DCHECK_NE(0x0F, entry->skeleton.opcode); 942 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 943 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 944 uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP; 945 code_buffer_.push_back(modrm); 946 DCHECK_LT(scale, 4); 947 DCHECK_LT(index, 8); 948 DCHECK_LT(base_or_table, 8); 949 uint8_t base = static_cast<uint8_t>(base_or_table); 950 uint8_t sib = (scale << 6) | (index << 3) | base; 951 code_buffer_.push_back(sib); 952 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 953 } else { 954 code_buffer_.push_back(entry->skeleton.opcode + reg); 955 } 956 code_buffer_.push_back(disp & 0xFF); 957 code_buffer_.push_back((disp >> 8) & 0xFF); 958 code_buffer_.push_back((disp >> 16) & 0xFF); 959 code_buffer_.push_back((disp >> 24) & 0xFF); 960 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 961 DCHECK_EQ(0, entry->skeleton.ax_opcode); 962} 963 964void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) { 965 DCHECK(entry->opcode == kX86StartOfMethod) << entry->name; 966 code_buffer_.push_back(0xE8); // call +0 967 code_buffer_.push_back(0); 968 code_buffer_.push_back(0); 969 code_buffer_.push_back(0); 970 code_buffer_.push_back(0); 971 972 DCHECK_LT(reg, 8); 973 code_buffer_.push_back(0x58 + reg); // pop reg 974 975 EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */); 976} 977 978void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 979 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 980 << BuildInsnString(entry->fmt, lir, 0); 981 for (int i = 0; i < GetInsnSize(lir); ++i) { 982 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 983 } 984} 985 986/* 987 * Assemble the LIR into binary instruction format. Note that we may 988 * discover that pc-relative displacements may not fit the selected 989 * instruction. In those cases we will try to substitute a new code 990 * sequence or request that the trace be shortened and retried. 991 */ 992AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 993 LIR *lir; 994 AssemblerStatus res = kSuccess; // Assume success 995 996 const bool kVerbosePcFixup = false; 997 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 998 if (IsPseudoLirOp(lir->opcode)) { 999 continue; 1000 } 1001 1002 if (lir->flags.is_nop) { 1003 continue; 1004 } 1005 1006 if (lir->flags.fixup != kFixupNone) { 1007 switch (lir->opcode) { 1008 case kX86Jcc8: { 1009 LIR *target_lir = lir->target; 1010 DCHECK(target_lir != NULL); 1011 int delta = 0; 1012 CodeOffset pc; 1013 if (IS_SIMM8(lir->operands[0])) { 1014 pc = lir->offset + 2 /* opcode + rel8 */; 1015 } else { 1016 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1017 } 1018 CodeOffset target = target_lir->offset; 1019 delta = target - pc; 1020 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1021 if (kVerbosePcFixup) { 1022 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1023 << " delta: " << delta << " old delta: " << lir->operands[0]; 1024 } 1025 lir->opcode = kX86Jcc32; 1026 SetupResourceMasks(lir); 1027 res = kRetryAll; 1028 } 1029 if (kVerbosePcFixup) { 1030 LOG(INFO) << "Source:"; 1031 DumpLIRInsn(lir, 0); 1032 LOG(INFO) << "Target:"; 1033 DumpLIRInsn(target_lir, 0); 1034 LOG(INFO) << "Delta " << delta; 1035 } 1036 lir->operands[0] = delta; 1037 break; 1038 } 1039 case kX86Jcc32: { 1040 LIR *target_lir = lir->target; 1041 DCHECK(target_lir != NULL); 1042 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1043 CodeOffset target = target_lir->offset; 1044 int delta = target - pc; 1045 if (kVerbosePcFixup) { 1046 LOG(INFO) << "Source:"; 1047 DumpLIRInsn(lir, 0); 1048 LOG(INFO) << "Target:"; 1049 DumpLIRInsn(target_lir, 0); 1050 LOG(INFO) << "Delta " << delta; 1051 } 1052 lir->operands[0] = delta; 1053 break; 1054 } 1055 case kX86Jmp8: { 1056 LIR *target_lir = lir->target; 1057 DCHECK(target_lir != NULL); 1058 int delta = 0; 1059 CodeOffset pc; 1060 if (IS_SIMM8(lir->operands[0])) { 1061 pc = lir->offset + 2 /* opcode + rel8 */; 1062 } else { 1063 pc = lir->offset + 5 /* opcode + rel32 */; 1064 } 1065 CodeOffset target = target_lir->offset; 1066 delta = target - pc; 1067 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1068 // Useless branch 1069 NopLIR(lir); 1070 if (kVerbosePcFixup) { 1071 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1072 } 1073 res = kRetryAll; 1074 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1075 if (kVerbosePcFixup) { 1076 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1077 } 1078 lir->opcode = kX86Jmp32; 1079 SetupResourceMasks(lir); 1080 res = kRetryAll; 1081 } 1082 lir->operands[0] = delta; 1083 break; 1084 } 1085 case kX86Jmp32: { 1086 LIR *target_lir = lir->target; 1087 DCHECK(target_lir != NULL); 1088 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1089 CodeOffset target = target_lir->offset; 1090 int delta = target - pc; 1091 lir->operands[0] = delta; 1092 break; 1093 } 1094 default: 1095 break; 1096 } 1097 } 1098 1099 /* 1100 * If one of the pc-relative instructions expanded we'll have 1101 * to make another pass. Don't bother to fully assemble the 1102 * instruction. 1103 */ 1104 if (res != kSuccess) { 1105 continue; 1106 } 1107 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1108 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1109 size_t starting_cbuf_size = code_buffer_.size(); 1110 switch (entry->kind) { 1111 case kData: // 4 bytes of data 1112 code_buffer_.push_back(lir->operands[0]); 1113 break; 1114 case kNullary: // 1 byte of opcode 1115 DCHECK_EQ(0, entry->skeleton.prefix1); 1116 DCHECK_EQ(0, entry->skeleton.prefix2); 1117 EmitOpcode(entry); 1118 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1119 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1120 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1121 break; 1122 case kRegOpcode: // lir operands - 0: reg 1123 EmitOpRegOpcode(entry, lir->operands[0]); 1124 break; 1125 case kReg: // lir operands - 0: reg 1126 EmitOpReg(entry, lir->operands[0]); 1127 break; 1128 case kMem: // lir operands - 0: base, 1: disp 1129 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1130 break; 1131 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 1132 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); 1133 break; 1134 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1135 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1136 break; 1137 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 1138 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1139 break; 1140 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1141 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1142 lir->operands[3], lir->operands[4]); 1143 break; 1144 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1145 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1146 break; 1147 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1148 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1149 lir->operands[3], lir->operands[4]); 1150 break; 1151 case kRegThread: // lir operands - 0: reg, 1: disp 1152 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1153 break; 1154 case kRegReg: // lir operands - 0: reg1, 1: reg2 1155 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1156 break; 1157 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1158 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1159 break; 1160 case kRegRegImm: 1161 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1162 break; 1163 case kRegImm: // lir operands - 0: reg, 1: immediate 1164 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1165 break; 1166 case kThreadImm: // lir operands - 0: disp, 1: immediate 1167 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1168 break; 1169 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1170 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1171 break; 1172 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1173 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1174 break; 1175 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1176 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1177 break; 1178 case kRegCond: // lir operands - 0: reg, 1: condition 1179 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1180 break; 1181 case kJmp: // lir operands - 0: rel 1182 EmitJmp(entry, lir->operands[0]); 1183 break; 1184 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1185 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1186 break; 1187 case kCall: 1188 switch (entry->opcode) { 1189 case kX86CallM: // lir operands - 0: base, 1: disp 1190 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1191 break; 1192 case kX86CallT: // lir operands - 0: disp 1193 EmitCallThread(entry, lir->operands[0]); 1194 break; 1195 default: 1196 EmitUnimplemented(entry, lir); 1197 break; 1198 } 1199 break; 1200 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1201 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1202 lir->operands[3], lir->operands[4]); 1203 break; 1204 case kMacro: 1205 EmitMacro(entry, lir->operands[0], lir->offset); 1206 break; 1207 default: 1208 EmitUnimplemented(entry, lir); 1209 break; 1210 } 1211 CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)), 1212 code_buffer_.size() - starting_cbuf_size) 1213 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1214 } 1215 return res; 1216} 1217 1218// LIR offset assignment. 1219// TODO: consolidate w/ Arm assembly mechanism. 1220int X86Mir2Lir::AssignInsnOffsets() { 1221 LIR* lir; 1222 int offset = 0; 1223 1224 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1225 lir->offset = offset; 1226 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1227 if (!lir->flags.is_nop) { 1228 offset += lir->flags.size; 1229 } 1230 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1231 if (offset & 0x2) { 1232 offset += 2; 1233 lir->operands[0] = 1; 1234 } else { 1235 lir->operands[0] = 0; 1236 } 1237 } 1238 /* Pseudo opcodes don't consume space */ 1239 } 1240 return offset; 1241} 1242 1243/* 1244 * Walk the compilation unit and assign offsets to instructions 1245 * and literals and compute the total size of the compiled unit. 1246 * TODO: consolidate w/ Arm assembly mechanism. 1247 */ 1248void X86Mir2Lir::AssignOffsets() { 1249 int offset = AssignInsnOffsets(); 1250 1251 /* Const values have to be word aligned */ 1252 offset = (offset + 3) & ~3; 1253 1254 /* Set up offsets for literals */ 1255 data_offset_ = offset; 1256 1257 offset = AssignLiteralOffset(offset); 1258 1259 offset = AssignSwitchTablesOffset(offset); 1260 1261 offset = AssignFillArrayDataOffset(offset); 1262 1263 total_size_ = offset; 1264} 1265 1266/* 1267 * Go over each instruction in the list and calculate the offset from the top 1268 * before sending them off to the assembler. If out-of-range branch distance is 1269 * seen rearrange the instructions a bit to correct it. 1270 * TODO: consolidate w/ Arm assembly mechanism. 1271 */ 1272void X86Mir2Lir::AssembleLIR() { 1273 cu_->NewTimingSplit("Assemble"); 1274 AssignOffsets(); 1275 int assembler_retries = 0; 1276 /* 1277 * Assemble here. Note that we generate code with optimistic assumptions 1278 * and if found now to work, we'll have to redo the sequence and retry. 1279 */ 1280 1281 while (true) { 1282 AssemblerStatus res = AssembleInstructions(0); 1283 if (res == kSuccess) { 1284 break; 1285 } else { 1286 assembler_retries++; 1287 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1288 CodegenDump(); 1289 LOG(FATAL) << "Assembler error - too many retries"; 1290 } 1291 // Redo offsets and try again 1292 AssignOffsets(); 1293 code_buffer_.clear(); 1294 } 1295 } 1296 1297 // Install literals 1298 InstallLiteralPools(); 1299 1300 // Install switch tables 1301 InstallSwitchTables(); 1302 1303 // Install fill array data 1304 InstallFillArrayData(); 1305 1306 // Create the mapping table and native offset to reference map. 1307 cu_->NewTimingSplit("PcMappingTable"); 1308 CreateMappingTables(); 1309 1310 cu_->NewTimingSplit("GcMap"); 1311 CreateNativeGcMap(); 1312} 1313 1314} // namespace art 1315