assemble_x86.cc revision c29bb614c60e0eb9a2bacf90f6dfce796344021e
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "x86_lir.h" 20 21namespace art { 22 23#define MAX_ASSEMBLER_RETRIES 50 24 25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0 }, "int 3", "" }, 28 { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, 29 30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8TR", "fs:[!0d],!1r" }, \ 40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RR", "!0r,!1r" }, \ 41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0 }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1 }, #opname "8RI", "!0r,!1d" }, \ 45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1 }, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0 }, #opname "16TR", "fs:[!0d],!1r" }, \ 52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RR", "!0r,!1r" }, \ 53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0 }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2 }, #opname "16RI", "!0r,!1d" }, \ 57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2 }, #opname "16TI", "fs:[!0d],!1d" }, \ 60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16RI8", "!0r,!1d" }, \ 61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0 }, #opname "32TR", "fs:[!0d],!1r" }, \ 68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RR", "!0r,!1r" }, \ 69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0 }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4 }, #opname "32RI", "!0r,!1d" }, \ 73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4 }, #opname "32TI", "fs:[!0d],!1d" }, \ 76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32RI8", "!0r,!1d" }, \ 77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1 }, #opname "32TI8", "fs:[!0d],!1d" } 80 81ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 82 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 83 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 84 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 85 0x80, 0x0 /* RegMem8/imm8 */, 86 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 87ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 88 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 89 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 90 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 91 0x80, 0x1 /* RegMem8/imm8 */, 92 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 93ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 94 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 95 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 96 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 97 0x80, 0x2 /* RegMem8/imm8 */, 98 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 99ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 100 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 101 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 102 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 103 0x80, 0x3 /* RegMem8/imm8 */, 104 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 105ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 106 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 107 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 108 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 109 0x80, 0x4 /* RegMem8/imm8 */, 110 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 111ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 112 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 113 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 114 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 115 0x80, 0x5 /* RegMem8/imm8 */, 116 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 117ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 118 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 119 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 120 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 121 0x80, 0x6 /* RegMem8/imm8 */, 122 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 123ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 124 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 125 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 126 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 127 0x80, 0x7 /* RegMem8/imm8 */, 128 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 129#undef ENCODING_MAP 130 131 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RRI", "!0r,!1r,!2d" }, 132 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 133 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2 }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 134 135 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RRI", "!0r,!1r,!2d" }, 136 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 137 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4 }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 138 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RRI8", "!0r,!1r,!2d" }, 139 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 140 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1 }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 141 142 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8MR", "[!0r+!1d],!2r" }, 143 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 144 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0 }, "Mov8TR", "fs:[!0d],!1r" }, 145 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RR", "!0r,!1r" }, 146 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RM", "!0r,[!1r+!2d]" }, 147 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 148 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0 }, "Mov8RT", "!0r,fs:[!1d]" }, 149 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1 }, "Mov8RI", "!0r,!1d" }, 150 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8MI", "[!0r+!1d],!2d" }, 151 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 152 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1 }, "Mov8TI", "fs:[!0d],!1d" }, 153 154 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16MR", "[!0r+!1d],!2r" }, 155 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 156 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0 }, "Mov16TR", "fs:[!0d],!1r" }, 157 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RR", "!0r,!1r" }, 158 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RM", "!0r,[!1r+!2d]" }, 159 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 160 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0 }, "Mov16RT", "!0r,fs:[!1d]" }, 161 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2 }, "Mov16RI", "!0r,!1d" }, 162 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16MI", "[!0r+!1d],!2d" }, 163 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2 }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 164 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2 }, "Mov16TI", "fs:[!0d],!1d" }, 165 166 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32MR", "[!0r+!1d],!2r" }, 167 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 168 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0 }, "Mov32TR", "fs:[!0d],!1r" }, 169 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RR", "!0r,!1r" }, 170 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RM", "!0r,[!1r+!2d]" }, 171 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 172 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0 }, "Mov32RT", "!0r,fs:[!1d]" }, 173 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "Mov32RI", "!0r,!1d" }, 174 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32MI", "[!0r+!1d],!2d" }, 175 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 176 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4 }, "Mov32TI", "fs:[!0d],!1d" }, 177 178 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0 }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 179 180#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 181{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8RI", "!0r,!1d" }, \ 182{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8MI", "[!0r+!1d],!2d" }, \ 183{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 184{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8RC", "!0r,cl" }, \ 185{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8MC", "[!0r+!1d],cl" }, \ 186{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1 }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 187 \ 188{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16RI", "!0r,!1d" }, \ 189{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16MI", "[!0r+!1d],!2d" }, \ 190{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 191{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16RC", "!0r,cl" }, \ 192{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16MC", "[!0r+!1d],cl" }, \ 193{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1 }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 194 \ 195{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32RI", "!0r,!1d" }, \ 196{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32MI", "[!0r+!1d],!2d" }, \ 197{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1 }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 198{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32RC", "!0r,cl" }, \ 199{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32MC", "[!0r+!1d],cl" }, \ 200{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0 }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" } 201 202 SHIFT_ENCODING_MAP(Rol, 0x0), 203 SHIFT_ENCODING_MAP(Ror, 0x1), 204 SHIFT_ENCODING_MAP(Rcl, 0x2), 205 SHIFT_ENCODING_MAP(Rcr, 0x3), 206 SHIFT_ENCODING_MAP(Sal, 0x4), 207 SHIFT_ENCODING_MAP(Shr, 0x5), 208 SHIFT_ENCODING_MAP(Sar, 0x7), 209#undef SHIFT_ENCODING_MAP 210 211 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0}, "Cmc", "" }, 212 213 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8RI", "!0r,!1d" }, 214 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8MI", "[!0r+!1d],!2d" }, 215 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1}, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 216 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16RI", "!0r,!1d" }, 217 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16MI", "[!0r+!1d],!2d" }, 218 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2}, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 219 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32RI", "!0r,!1d" }, 220 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32MI", "[!0r+!1d],!2d" }, 221 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4}, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 222 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0}, "Test32RR", "!0r,!1r" }, 223 224#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 225 reg, reg_kind, reg_flags, \ 226 mem, mem_kind, mem_flags, \ 227 arr, arr_kind, arr_flags, imm, \ 228 b_flags, hw_flags, w_flags, \ 229 b_format, hw_format, w_format) \ 230{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #reg, #b_format "!0r" }, \ 231{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #mem, #b_format "[!0r+!1d]" }, \ 232{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0}, #opname "8" #arr, #b_format "[!0r+!1r<<!2d+!3d]" }, \ 233{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #reg, #hw_format "!0r" }, \ 234{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #mem, #hw_format "[!0r+!1d]" }, \ 235{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1}, #opname "16" #arr, #hw_format "[!0r+!1r<<!2d+!3d]" }, \ 236{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #reg, #w_format "!0r" }, \ 237{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #mem, #w_format "[!0r+!1d]" }, \ 238{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2}, #opname "32" #arr, #w_format "[!0r+!1r<<!2d+!3d]" } 239 240 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 241 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 242 243 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 244 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 245 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 246 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kRegRegReg, IS_UNARY_OP | REG_USE0, DaM, kRegRegMem, IS_BINARY_OP | REG_USE0, DaA, kRegRegArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 247#undef UNARY_ENCODING_MAP 248 249 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0 }, "Bswap32R", "!0r" }, 250 251#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 252{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RR", "!0r,!1r" }, \ 253{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RM", "!0r,[!1r+!2d]" }, \ 254{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0 }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 255 256 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 257 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdMR", "[!0r+!1d],!2r" }, 258 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 259 260 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 261 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssMR", "[!0r+!1d],!2r" }, 262 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0 }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 263 264 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 265 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 266 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 267 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 268 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 269 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 270 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES), 271 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES), 272 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES), 273 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES), 274 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0), 275 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0), 276 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0), 277 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0), 278 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0), 279 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0), 280 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 281 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 282 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0), 283 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0), 284 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0), 285 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0), 286 287 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1 }, "PsrlqRI", "!0r,!1d" }, 288 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1 }, "PsllqRI", "!0r,!1d" }, 289 290 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 291 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxRR", "!0r,!1r" }, 292 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxMR", "[!0r+!1d],!2r" }, 293 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0 }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 294 295 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8R", "!1c !0r" }, 296 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8M", "!2c [!0r+!1d]" }, 297 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0 }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 298 299 // TODO: load/store? 300 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 301 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0 }, "Mfence", "" }, 302 303 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_DEF0 | SETS_CCODES), 304 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_DEF0 | SETS_CCODES), 305 306 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "!0r,!1r" }, 307 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1d],!2r" }, 308 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 309 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 310 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0 }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 311 312 EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 313 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 314 EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 315 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 316#undef EXT_0F_ENCODING_MAP 317 318 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0 }, "Jcc8", "!1c !0t" }, 319 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0 }, "Jcc32", "!1c !0t" }, 320 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0 }, "Jmp8", "!0t" }, 321 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0 }, "Jmp32", "!0t" }, 322 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0 }, "JmpR", "!0r" }, 323 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0 }, "CallR", "!0r" }, 324 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallM", "[!0r+!1d]" }, 325 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 326 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0 }, "CallT", "fs:[!0d]" }, 327 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0 }, "Ret", "" }, 328 329 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0 }, "StartOfMethod", "!0r" }, 330 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0 }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 331 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4 }, "PcRelAdr", "!0r,!1d" }, 332}; 333 334static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) { 335 size_t size = 0; 336 if (entry->skeleton.prefix1 > 0) { 337 ++size; 338 if (entry->skeleton.prefix2 > 0) { 339 ++size; 340 } 341 } 342 ++size; // opcode 343 if (entry->skeleton.opcode == 0x0F) { 344 ++size; 345 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 346 ++size; 347 } 348 } 349 ++size; // modrm 350 if (has_sib || base == rX86_SP) { 351 // SP requires a SIB byte. 352 ++size; 353 } 354 if (displacement != 0 || base == rBP) { 355 // BP requires an explicit displacement, even when it's 0. 356 if (entry->opcode != kX86Lea32RA) { 357 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0ULL) << entry->name; 358 } 359 size += IS_SIMM8(displacement) ? 1 : 4; 360 } 361 size += entry->skeleton.immediate_bytes; 362 return size; 363} 364 365int X86Mir2Lir::GetInsnSize(LIR* lir) { 366 DCHECK(!IsPseudoLirOp(lir->opcode)); 367 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 368 switch (entry->kind) { 369 case kData: 370 return 4; // 4 bytes of data 371 case kNop: 372 return lir->operands[0]; // length of nop is sole operand 373 case kNullary: 374 return 1; // 1 byte of opcode 375 case kRegOpcode: // lir operands - 0: reg 376 return ComputeSize(entry, 0, 0, false) - 1; // substract 1 for modrm 377 case kReg: // lir operands - 0: reg 378 return ComputeSize(entry, 0, 0, false); 379 case kMem: // lir operands - 0: base, 1: disp 380 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 381 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 382 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 383 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 384 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 385 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 386 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 387 case kThreadReg: // lir operands - 0: disp, 1: reg 388 return ComputeSize(entry, 0, lir->operands[0], false); 389 case kRegReg: 390 return ComputeSize(entry, 0, 0, false); 391 case kRegRegStore: 392 return ComputeSize(entry, 0, 0, false); 393 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 394 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 395 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 396 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 397 case kRegThread: // lir operands - 0: reg, 1: disp 398 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 399 case kRegImm: { // lir operands - 0: reg, 1: immediate 400 size_t size = ComputeSize(entry, 0, 0, false); 401 if (entry->skeleton.ax_opcode == 0) { 402 return size; 403 } else { 404 // AX opcodes don't require the modrm byte. 405 int reg = lir->operands[0]; 406 return size - (reg == rAX ? 1 : 0); 407 } 408 } 409 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 410 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 411 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 412 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 413 case kThreadImm: // lir operands - 0: disp, 1: imm 414 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 415 case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm 416 return ComputeSize(entry, 0, 0, false); 417 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 418 return ComputeSize(entry, lir->operands[1], lir->operands[2], false); 419 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 420 return ComputeSize(entry, lir->operands[1], lir->operands[4], true); 421 case kMovRegImm: // lir operands - 0: reg, 1: immediate 422 return 1 + entry->skeleton.immediate_bytes; 423 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 424 // Shift by immediate one has a shorter opcode. 425 return ComputeSize(entry, 0, 0, false) - (lir->operands[1] == 1 ? 1 : 0); 426 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 427 // Shift by immediate one has a shorter opcode. 428 return ComputeSize(entry, lir->operands[0], lir->operands[1], false) - 429 (lir->operands[2] == 1 ? 1 : 0); 430 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 431 // Shift by immediate one has a shorter opcode. 432 return ComputeSize(entry, lir->operands[0], lir->operands[3], true) - 433 (lir->operands[4] == 1 ? 1 : 0); 434 case kShiftRegCl: 435 return ComputeSize(entry, 0, 0, false); 436 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 437 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 438 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 439 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 440 case kRegCond: // lir operands - 0: reg, 1: cond 441 return ComputeSize(entry, 0, 0, false); 442 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 443 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 444 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 445 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 446 case kJcc: 447 if (lir->opcode == kX86Jcc8) { 448 return 2; // opcode + rel8 449 } else { 450 DCHECK(lir->opcode == kX86Jcc32); 451 return 6; // 2 byte opcode + rel32 452 } 453 case kJmp: 454 if (lir->opcode == kX86Jmp8) { 455 return 2; // opcode + rel8 456 } else if (lir->opcode == kX86Jmp32) { 457 return 5; // opcode + rel32 458 } else { 459 DCHECK(lir->opcode == kX86JmpR); 460 return 2; // opcode + modrm 461 } 462 case kCall: 463 switch (lir->opcode) { 464 case kX86CallR: return 2; // opcode modrm 465 case kX86CallM: // lir operands - 0: base, 1: disp 466 return ComputeSize(entry, lir->operands[0], lir->operands[1], false); 467 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 468 return ComputeSize(entry, lir->operands[0], lir->operands[3], true); 469 case kX86CallT: // lir operands - 0: disp 470 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit 471 default: 472 break; 473 } 474 break; 475 case kPcRel: 476 if (entry->opcode == kX86PcRelLoadRA) { 477 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 478 return ComputeSize(entry, lir->operands[1], 0x12345678, true); 479 } else { 480 DCHECK(entry->opcode == kX86PcRelAdr); 481 return 5; // opcode with reg + 4 byte immediate 482 } 483 case kMacro: 484 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 485 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 486 ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) - 487 (lir->operands[0] == rAX ? 1 : 0); // shorter ax encoding 488 default: 489 break; 490 } 491 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 492 return 0; 493} 494 495static uint8_t ModrmForDisp(int base, int disp) { 496 // BP requires an explicit disp, so do not omit it in the 0 case 497 if (disp == 0 && base != rBP) { 498 return 0; 499 } else if (IS_SIMM8(disp)) { 500 return 1; 501 } else { 502 return 2; 503 } 504} 505 506void X86Mir2Lir::EmitDisp(int base, int disp) { 507 // BP requires an explicit disp, so do not omit it in the 0 case 508 if (disp == 0 && base != rBP) { 509 return; 510 } else if (IS_SIMM8(disp)) { 511 code_buffer_.push_back(disp & 0xFF); 512 } else { 513 code_buffer_.push_back(disp & 0xFF); 514 code_buffer_.push_back((disp >> 8) & 0xFF); 515 code_buffer_.push_back((disp >> 16) & 0xFF); 516 code_buffer_.push_back((disp >> 24) & 0xFF); 517 } 518} 519 520void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg) { 521 if (entry->skeleton.prefix1 != 0) { 522 code_buffer_.push_back(entry->skeleton.prefix1); 523 if (entry->skeleton.prefix2 != 0) { 524 code_buffer_.push_back(entry->skeleton.prefix2); 525 } 526 } else { 527 DCHECK_EQ(0, entry->skeleton.prefix2); 528 } 529 code_buffer_.push_back(entry->skeleton.opcode); 530 if (entry->skeleton.opcode == 0x0F) { 531 code_buffer_.push_back(entry->skeleton.extra_opcode1); 532 // There's no 3-byte instruction with +rd 533 DCHECK_NE(0x38, entry->skeleton.extra_opcode1); 534 DCHECK_NE(0x3A, entry->skeleton.extra_opcode1); 535 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 536 } else { 537 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 538 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 539 } 540 DCHECK(!X86_FPREG(reg)); 541 DCHECK_LT(reg, 8); 542 code_buffer_.back() += reg; 543 DCHECK_EQ(0, entry->skeleton.ax_opcode); 544 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 545} 546 547void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, uint8_t reg) { 548 if (entry->skeleton.prefix1 != 0) { 549 code_buffer_.push_back(entry->skeleton.prefix1); 550 if (entry->skeleton.prefix2 != 0) { 551 code_buffer_.push_back(entry->skeleton.prefix2); 552 } 553 } else { 554 DCHECK_EQ(0, entry->skeleton.prefix2); 555 } 556 code_buffer_.push_back(entry->skeleton.opcode); 557 if (entry->skeleton.opcode == 0x0F) { 558 code_buffer_.push_back(entry->skeleton.extra_opcode1); 559 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 560 code_buffer_.push_back(entry->skeleton.extra_opcode2); 561 } else { 562 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 563 } 564 } else { 565 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 566 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 567 } 568 if (X86_FPREG(reg)) { 569 reg = reg & X86_FP_REG_MASK; 570 } 571 if (reg >= 4) { 572 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 573 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 574 } 575 DCHECK_LT(reg, 8); 576 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 577 code_buffer_.push_back(modrm); 578 DCHECK_EQ(0, entry->skeleton.ax_opcode); 579 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 580} 581 582void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) { 583 if (entry->skeleton.prefix1 != 0) { 584 code_buffer_.push_back(entry->skeleton.prefix1); 585 if (entry->skeleton.prefix2 != 0) { 586 code_buffer_.push_back(entry->skeleton.prefix2); 587 } 588 } else { 589 DCHECK_EQ(0, entry->skeleton.prefix2); 590 } 591 code_buffer_.push_back(entry->skeleton.opcode); 592 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 593 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 594 DCHECK_LT(entry->skeleton.modrm_opcode, 8); 595 DCHECK_LT(base, 8); 596 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base; 597 code_buffer_.push_back(modrm); 598 EmitDisp(base, disp); 599 DCHECK_EQ(0, entry->skeleton.ax_opcode); 600 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 601} 602 603void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, 604 uint8_t base, int disp, uint8_t reg) { 605 if (entry->skeleton.prefix1 != 0) { 606 code_buffer_.push_back(entry->skeleton.prefix1); 607 if (entry->skeleton.prefix2 != 0) { 608 code_buffer_.push_back(entry->skeleton.prefix2); 609 } 610 } else { 611 DCHECK_EQ(0, entry->skeleton.prefix2); 612 } 613 code_buffer_.push_back(entry->skeleton.opcode); 614 if (entry->skeleton.opcode == 0x0F) { 615 code_buffer_.push_back(entry->skeleton.extra_opcode1); 616 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 617 code_buffer_.push_back(entry->skeleton.extra_opcode2); 618 } else { 619 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 620 } 621 } else { 622 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 623 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 624 } 625 if (X86_FPREG(reg)) { 626 reg = reg & X86_FP_REG_MASK; 627 } 628 if (reg >= 4) { 629 DCHECK(strchr(entry->name, '8') == NULL || 630 entry->opcode == kX86Movzx8RM || entry->opcode == kX86Movsx8RM) 631 << entry->name << " " << static_cast<int>(reg) 632 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 633 } 634 DCHECK_LT(reg, 8); 635 DCHECK_LT(base, 8); 636 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | base; 637 code_buffer_.push_back(modrm); 638 if (base == rX86_SP) { 639 // Special SIB for SP base 640 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); 641 } 642 EmitDisp(base, disp); 643 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 644 DCHECK_EQ(0, entry->skeleton.ax_opcode); 645 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 646} 647 648void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, 649 uint8_t reg, uint8_t base, int disp) { 650 // Opcode will flip operands. 651 EmitMemReg(entry, base, disp, reg); 652} 653 654void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 655 int scale, int disp) { 656 if (entry->skeleton.prefix1 != 0) { 657 code_buffer_.push_back(entry->skeleton.prefix1); 658 if (entry->skeleton.prefix2 != 0) { 659 code_buffer_.push_back(entry->skeleton.prefix2); 660 } 661 } else { 662 DCHECK_EQ(0, entry->skeleton.prefix2); 663 } 664 code_buffer_.push_back(entry->skeleton.opcode); 665 if (entry->skeleton.opcode == 0x0F) { 666 code_buffer_.push_back(entry->skeleton.extra_opcode1); 667 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 668 code_buffer_.push_back(entry->skeleton.extra_opcode2); 669 } else { 670 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 671 } 672 } else { 673 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 674 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 675 } 676 if (X86_FPREG(reg)) { 677 reg = reg & X86_FP_REG_MASK; 678 } 679 DCHECK_LT(reg, 8); 680 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP; 681 code_buffer_.push_back(modrm); 682 DCHECK_LT(scale, 4); 683 DCHECK_LT(index, 8); 684 DCHECK_LT(base, 8); 685 uint8_t sib = (scale << 6) | (index << 3) | base; 686 code_buffer_.push_back(sib); 687 EmitDisp(base, disp); 688 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 689 DCHECK_EQ(0, entry->skeleton.ax_opcode); 690 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 691} 692 693void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 694 uint8_t reg) { 695 // Opcode will flip operands. 696 EmitRegArray(entry, reg, base, index, scale, disp); 697} 698 699void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) { 700 DCHECK_NE(entry->skeleton.prefix1, 0); 701 code_buffer_.push_back(entry->skeleton.prefix1); 702 if (entry->skeleton.prefix2 != 0) { 703 code_buffer_.push_back(entry->skeleton.prefix2); 704 } 705 code_buffer_.push_back(entry->skeleton.opcode); 706 if (entry->skeleton.opcode == 0x0F) { 707 code_buffer_.push_back(entry->skeleton.extra_opcode1); 708 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 709 code_buffer_.push_back(entry->skeleton.extra_opcode2); 710 } else { 711 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 712 } 713 } else { 714 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 715 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 716 } 717 if (X86_FPREG(reg)) { 718 reg = reg & X86_FP_REG_MASK; 719 } 720 if (reg >= 4) { 721 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 722 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 723 } 724 DCHECK_LT(reg, 8); 725 uint8_t modrm = (0 << 6) | (reg << 3) | rBP; 726 code_buffer_.push_back(modrm); 727 code_buffer_.push_back(disp & 0xFF); 728 code_buffer_.push_back((disp >> 8) & 0xFF); 729 code_buffer_.push_back((disp >> 16) & 0xFF); 730 code_buffer_.push_back((disp >> 24) & 0xFF); 731 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 732 DCHECK_EQ(0, entry->skeleton.ax_opcode); 733 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 734} 735 736void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { 737 if (entry->skeleton.prefix1 != 0) { 738 code_buffer_.push_back(entry->skeleton.prefix1); 739 if (entry->skeleton.prefix2 != 0) { 740 code_buffer_.push_back(entry->skeleton.prefix2); 741 } 742 } else { 743 DCHECK_EQ(0, entry->skeleton.prefix2); 744 } 745 code_buffer_.push_back(entry->skeleton.opcode); 746 if (entry->skeleton.opcode == 0x0F) { 747 code_buffer_.push_back(entry->skeleton.extra_opcode1); 748 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 749 code_buffer_.push_back(entry->skeleton.extra_opcode2); 750 } else { 751 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 752 } 753 } else { 754 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 755 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 756 } 757 if (X86_FPREG(reg1)) { 758 reg1 = reg1 & X86_FP_REG_MASK; 759 } 760 if (X86_FPREG(reg2)) { 761 reg2 = reg2 & X86_FP_REG_MASK; 762 } 763 DCHECK_LT(reg1, 8); 764 DCHECK_LT(reg2, 8); 765 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 766 code_buffer_.push_back(modrm); 767 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 768 DCHECK_EQ(0, entry->skeleton.ax_opcode); 769 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 770} 771 772void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, 773 uint8_t reg1, uint8_t reg2, int32_t imm) { 774 if (entry->skeleton.prefix1 != 0) { 775 code_buffer_.push_back(entry->skeleton.prefix1); 776 if (entry->skeleton.prefix2 != 0) { 777 code_buffer_.push_back(entry->skeleton.prefix2); 778 } 779 } else { 780 DCHECK_EQ(0, entry->skeleton.prefix2); 781 } 782 code_buffer_.push_back(entry->skeleton.opcode); 783 if (entry->skeleton.opcode == 0x0F) { 784 code_buffer_.push_back(entry->skeleton.extra_opcode1); 785 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 786 code_buffer_.push_back(entry->skeleton.extra_opcode2); 787 } else { 788 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 789 } 790 } else { 791 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 792 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 793 } 794 if (X86_FPREG(reg1)) { 795 reg1 = reg1 & X86_FP_REG_MASK; 796 } 797 if (X86_FPREG(reg2)) { 798 reg2 = reg2 & X86_FP_REG_MASK; 799 } 800 DCHECK_LT(reg1, 8); 801 DCHECK_LT(reg2, 8); 802 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; 803 code_buffer_.push_back(modrm); 804 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 805 DCHECK_EQ(0, entry->skeleton.ax_opcode); 806 switch (entry->skeleton.immediate_bytes) { 807 case 1: 808 DCHECK(IS_SIMM8(imm)); 809 code_buffer_.push_back(imm & 0xFF); 810 break; 811 case 2: 812 DCHECK(IS_SIMM16(imm)); 813 code_buffer_.push_back(imm & 0xFF); 814 code_buffer_.push_back((imm >> 8) & 0xFF); 815 break; 816 case 4: 817 code_buffer_.push_back(imm & 0xFF); 818 code_buffer_.push_back((imm >> 8) & 0xFF); 819 code_buffer_.push_back((imm >> 16) & 0xFF); 820 code_buffer_.push_back((imm >> 24) & 0xFF); 821 break; 822 default: 823 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 824 << ") for instruction: " << entry->name; 825 break; 826 } 827} 828 829void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 830 if (entry->skeleton.prefix1 != 0) { 831 code_buffer_.push_back(entry->skeleton.prefix1); 832 if (entry->skeleton.prefix2 != 0) { 833 code_buffer_.push_back(entry->skeleton.prefix2); 834 } 835 } else { 836 DCHECK_EQ(0, entry->skeleton.prefix2); 837 } 838 if (reg == rAX && entry->skeleton.ax_opcode != 0) { 839 code_buffer_.push_back(entry->skeleton.ax_opcode); 840 } else { 841 code_buffer_.push_back(entry->skeleton.opcode); 842 if (entry->skeleton.opcode == 0x0F) { 843 code_buffer_.push_back(entry->skeleton.extra_opcode1); 844 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 845 code_buffer_.push_back(entry->skeleton.extra_opcode2); 846 } else { 847 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 848 } 849 } else { 850 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 851 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 852 } 853 if (X86_FPREG(reg)) { 854 reg = reg & X86_FP_REG_MASK; 855 } 856 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 857 code_buffer_.push_back(modrm); 858 } 859 switch (entry->skeleton.immediate_bytes) { 860 case 1: 861 DCHECK(IS_SIMM8(imm)); 862 code_buffer_.push_back(imm & 0xFF); 863 break; 864 case 2: 865 DCHECK(IS_SIMM16(imm)); 866 code_buffer_.push_back(imm & 0xFF); 867 code_buffer_.push_back((imm >> 8) & 0xFF); 868 break; 869 case 4: 870 code_buffer_.push_back(imm & 0xFF); 871 code_buffer_.push_back((imm >> 8) & 0xFF); 872 code_buffer_.push_back((imm >> 16) & 0xFF); 873 code_buffer_.push_back((imm >> 24) & 0xFF); 874 break; 875 default: 876 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 877 << ") for instruction: " << entry->name; 878 break; 879 } 880} 881 882void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) { 883 if (entry->skeleton.prefix1 != 0) { 884 code_buffer_.push_back(entry->skeleton.prefix1); 885 if (entry->skeleton.prefix2 != 0) { 886 code_buffer_.push_back(entry->skeleton.prefix2); 887 } 888 } else { 889 DCHECK_EQ(0, entry->skeleton.prefix2); 890 } 891 code_buffer_.push_back(entry->skeleton.opcode); 892 if (entry->skeleton.opcode == 0x0F) { 893 code_buffer_.push_back(entry->skeleton.extra_opcode1); 894 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 895 code_buffer_.push_back(entry->skeleton.extra_opcode2); 896 } else { 897 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 898 } 899 } else { 900 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 901 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 902 } 903 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 904 code_buffer_.push_back(modrm); 905 code_buffer_.push_back(disp & 0xFF); 906 code_buffer_.push_back((disp >> 8) & 0xFF); 907 code_buffer_.push_back((disp >> 16) & 0xFF); 908 code_buffer_.push_back((disp >> 24) & 0xFF); 909 switch (entry->skeleton.immediate_bytes) { 910 case 1: 911 DCHECK(IS_SIMM8(imm)); 912 code_buffer_.push_back(imm & 0xFF); 913 break; 914 case 2: 915 DCHECK(IS_SIMM16(imm)); 916 code_buffer_.push_back(imm & 0xFF); 917 code_buffer_.push_back((imm >> 8) & 0xFF); 918 break; 919 case 4: 920 code_buffer_.push_back(imm & 0xFF); 921 code_buffer_.push_back((imm >> 8) & 0xFF); 922 code_buffer_.push_back((imm >> 16) & 0xFF); 923 code_buffer_.push_back((imm >> 24) & 0xFF); 924 break; 925 default: 926 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 927 << ") for instruction: " << entry->name; 928 break; 929 } 930 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 931} 932 933void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 934 DCHECK_LT(reg, 8); 935 code_buffer_.push_back(0xB8 + reg); 936 code_buffer_.push_back(imm & 0xFF); 937 code_buffer_.push_back((imm >> 8) & 0xFF); 938 code_buffer_.push_back((imm >> 16) & 0xFF); 939 code_buffer_.push_back((imm >> 24) & 0xFF); 940} 941 942void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm) { 943 if (entry->skeleton.prefix1 != 0) { 944 code_buffer_.push_back(entry->skeleton.prefix1); 945 if (entry->skeleton.prefix2 != 0) { 946 code_buffer_.push_back(entry->skeleton.prefix2); 947 } 948 } else { 949 DCHECK_EQ(0, entry->skeleton.prefix2); 950 } 951 if (imm != 1) { 952 code_buffer_.push_back(entry->skeleton.opcode); 953 } else { 954 // Shorter encoding for 1 bit shift 955 code_buffer_.push_back(entry->skeleton.ax_opcode); 956 } 957 if (entry->skeleton.opcode == 0x0F) { 958 code_buffer_.push_back(entry->skeleton.extra_opcode1); 959 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 960 code_buffer_.push_back(entry->skeleton.extra_opcode2); 961 } else { 962 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 963 } 964 } else { 965 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 966 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 967 } 968 if (reg >= 4) { 969 DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << static_cast<int>(reg) 970 << " in " << PrettyMethod(cu_->method_idx, *cu_->dex_file); 971 } 972 DCHECK_LT(reg, 8); 973 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 974 code_buffer_.push_back(modrm); 975 if (imm != 1) { 976 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 977 DCHECK(IS_SIMM8(imm)); 978 code_buffer_.push_back(imm & 0xFF); 979 } 980} 981 982void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl) { 983 DCHECK_EQ(cl, static_cast<uint8_t>(rCX)); 984 if (entry->skeleton.prefix1 != 0) { 985 code_buffer_.push_back(entry->skeleton.prefix1); 986 if (entry->skeleton.prefix2 != 0) { 987 code_buffer_.push_back(entry->skeleton.prefix2); 988 } 989 } else { 990 DCHECK_EQ(0, entry->skeleton.prefix2); 991 } 992 code_buffer_.push_back(entry->skeleton.opcode); 993 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 994 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 995 DCHECK_LT(reg, 8); 996 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 997 code_buffer_.push_back(modrm); 998 DCHECK_EQ(0, entry->skeleton.ax_opcode); 999 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1000} 1001 1002void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition) { 1003 if (entry->skeleton.prefix1 != 0) { 1004 code_buffer_.push_back(entry->skeleton.prefix1); 1005 if (entry->skeleton.prefix2 != 0) { 1006 code_buffer_.push_back(entry->skeleton.prefix2); 1007 } 1008 } else { 1009 DCHECK_EQ(0, entry->skeleton.prefix2); 1010 } 1011 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1012 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1013 code_buffer_.push_back(0x0F); 1014 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1015 code_buffer_.push_back(0x90 | condition); 1016 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1017 DCHECK_LT(reg, 8); 1018 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 1019 code_buffer_.push_back(modrm); 1020 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1021} 1022 1023void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int rel) { 1024 if (entry->opcode == kX86Jmp8) { 1025 DCHECK(IS_SIMM8(rel)); 1026 code_buffer_.push_back(0xEB); 1027 code_buffer_.push_back(rel & 0xFF); 1028 } else if (entry->opcode == kX86Jmp32) { 1029 code_buffer_.push_back(0xE9); 1030 code_buffer_.push_back(rel & 0xFF); 1031 code_buffer_.push_back((rel >> 8) & 0xFF); 1032 code_buffer_.push_back((rel >> 16) & 0xFF); 1033 code_buffer_.push_back((rel >> 24) & 0xFF); 1034 } else { 1035 DCHECK(entry->opcode == kX86JmpR); 1036 code_buffer_.push_back(entry->skeleton.opcode); 1037 uint8_t reg = static_cast<uint8_t>(rel); 1038 DCHECK_LT(reg, 8); 1039 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; 1040 code_buffer_.push_back(modrm); 1041 } 1042} 1043 1044void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc) { 1045 DCHECK_LT(cc, 16); 1046 if (entry->opcode == kX86Jcc8) { 1047 DCHECK(IS_SIMM8(rel)); 1048 code_buffer_.push_back(0x70 | cc); 1049 code_buffer_.push_back(rel & 0xFF); 1050 } else { 1051 DCHECK(entry->opcode == kX86Jcc32); 1052 code_buffer_.push_back(0x0F); 1053 code_buffer_.push_back(0x80 | cc); 1054 code_buffer_.push_back(rel & 0xFF); 1055 code_buffer_.push_back((rel >> 8) & 0xFF); 1056 code_buffer_.push_back((rel >> 16) & 0xFF); 1057 code_buffer_.push_back((rel >> 24) & 0xFF); 1058 } 1059} 1060 1061void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) { 1062 if (entry->skeleton.prefix1 != 0) { 1063 code_buffer_.push_back(entry->skeleton.prefix1); 1064 if (entry->skeleton.prefix2 != 0) { 1065 code_buffer_.push_back(entry->skeleton.prefix2); 1066 } 1067 } else { 1068 DCHECK_EQ(0, entry->skeleton.prefix2); 1069 } 1070 code_buffer_.push_back(entry->skeleton.opcode); 1071 if (entry->skeleton.opcode == 0x0F) { 1072 code_buffer_.push_back(entry->skeleton.extra_opcode1); 1073 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 1074 code_buffer_.push_back(entry->skeleton.extra_opcode2); 1075 } else { 1076 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1077 } 1078 } else { 1079 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1080 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1081 } 1082 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base; 1083 code_buffer_.push_back(modrm); 1084 if (base == rX86_SP) { 1085 // Special SIB for SP base 1086 code_buffer_.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP); 1087 } 1088 EmitDisp(base, disp); 1089 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1090 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1091} 1092 1093void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int disp) { 1094 DCHECK_NE(entry->skeleton.prefix1, 0); 1095 code_buffer_.push_back(entry->skeleton.prefix1); 1096 if (entry->skeleton.prefix2 != 0) { 1097 code_buffer_.push_back(entry->skeleton.prefix2); 1098 } 1099 code_buffer_.push_back(entry->skeleton.opcode); 1100 if (entry->skeleton.opcode == 0x0F) { 1101 code_buffer_.push_back(entry->skeleton.extra_opcode1); 1102 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 1103 code_buffer_.push_back(entry->skeleton.extra_opcode2); 1104 } else { 1105 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1106 } 1107 } else { 1108 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1109 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1110 } 1111 uint8_t modrm = (0 << 6) | (entry->skeleton.modrm_opcode << 3) | rBP; 1112 code_buffer_.push_back(modrm); 1113 code_buffer_.push_back(disp & 0xFF); 1114 code_buffer_.push_back((disp >> 8) & 0xFF); 1115 code_buffer_.push_back((disp >> 16) & 0xFF); 1116 code_buffer_.push_back((disp >> 24) & 0xFF); 1117 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1118 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1119} 1120 1121void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, uint8_t reg, 1122 int base_or_table, uint8_t index, int scale, int table_or_disp) { 1123 int disp; 1124 if (entry->opcode == kX86PcRelLoadRA) { 1125 Mir2Lir::EmbeddedData *tab_rec = 1126 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 1127 disp = tab_rec->offset; 1128 } else { 1129 DCHECK(entry->opcode == kX86PcRelAdr); 1130 Mir2Lir::EmbeddedData *tab_rec = 1131 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(base_or_table)); 1132 disp = tab_rec->offset; 1133 } 1134 if (entry->skeleton.prefix1 != 0) { 1135 code_buffer_.push_back(entry->skeleton.prefix1); 1136 if (entry->skeleton.prefix2 != 0) { 1137 code_buffer_.push_back(entry->skeleton.prefix2); 1138 } 1139 } else { 1140 DCHECK_EQ(0, entry->skeleton.prefix2); 1141 } 1142 if (X86_FPREG(reg)) { 1143 reg = reg & X86_FP_REG_MASK; 1144 } 1145 DCHECK_LT(reg, 8); 1146 if (entry->opcode == kX86PcRelLoadRA) { 1147 code_buffer_.push_back(entry->skeleton.opcode); 1148 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1149 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1150 uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP; 1151 code_buffer_.push_back(modrm); 1152 DCHECK_LT(scale, 4); 1153 DCHECK_LT(index, 8); 1154 DCHECK_LT(base_or_table, 8); 1155 uint8_t base = static_cast<uint8_t>(base_or_table); 1156 uint8_t sib = (scale << 6) | (index << 3) | base; 1157 code_buffer_.push_back(sib); 1158 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1159 } else { 1160 code_buffer_.push_back(entry->skeleton.opcode + reg); 1161 } 1162 code_buffer_.push_back(disp & 0xFF); 1163 code_buffer_.push_back((disp >> 8) & 0xFF); 1164 code_buffer_.push_back((disp >> 16) & 0xFF); 1165 code_buffer_.push_back((disp >> 24) & 0xFF); 1166 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1167 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1168} 1169 1170void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset) { 1171 DCHECK(entry->opcode == kX86StartOfMethod) << entry->name; 1172 code_buffer_.push_back(0xE8); // call +0 1173 code_buffer_.push_back(0); 1174 code_buffer_.push_back(0); 1175 code_buffer_.push_back(0); 1176 code_buffer_.push_back(0); 1177 1178 DCHECK_LT(reg, 8); 1179 code_buffer_.push_back(0x58 + reg); // pop reg 1180 1181 EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */); 1182} 1183 1184void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 1185 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 1186 << BuildInsnString(entry->fmt, lir, 0); 1187 for (int i = 0; i < GetInsnSize(lir); ++i) { 1188 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 1189 } 1190} 1191 1192/* 1193 * Assemble the LIR into binary instruction format. Note that we may 1194 * discover that pc-relative displacements may not fit the selected 1195 * instruction. In those cases we will try to substitute a new code 1196 * sequence or request that the trace be shortened and retried. 1197 */ 1198AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 1199 LIR *lir; 1200 AssemblerStatus res = kSuccess; // Assume success 1201 1202 const bool kVerbosePcFixup = false; 1203 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1204 if (IsPseudoLirOp(lir->opcode)) { 1205 continue; 1206 } 1207 1208 if (lir->flags.is_nop) { 1209 continue; 1210 } 1211 1212 if (lir->flags.fixup != kFixupNone) { 1213 switch (lir->opcode) { 1214 case kX86Jcc8: { 1215 LIR *target_lir = lir->target; 1216 DCHECK(target_lir != NULL); 1217 int delta = 0; 1218 CodeOffset pc; 1219 if (IS_SIMM8(lir->operands[0])) { 1220 pc = lir->offset + 2 /* opcode + rel8 */; 1221 } else { 1222 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1223 } 1224 CodeOffset target = target_lir->offset; 1225 delta = target - pc; 1226 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1227 if (kVerbosePcFixup) { 1228 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1229 << " delta: " << delta << " old delta: " << lir->operands[0]; 1230 } 1231 lir->opcode = kX86Jcc32; 1232 SetupResourceMasks(lir); 1233 res = kRetryAll; 1234 } 1235 if (kVerbosePcFixup) { 1236 LOG(INFO) << "Source:"; 1237 DumpLIRInsn(lir, 0); 1238 LOG(INFO) << "Target:"; 1239 DumpLIRInsn(target_lir, 0); 1240 LOG(INFO) << "Delta " << delta; 1241 } 1242 lir->operands[0] = delta; 1243 break; 1244 } 1245 case kX86Jcc32: { 1246 LIR *target_lir = lir->target; 1247 DCHECK(target_lir != NULL); 1248 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1249 CodeOffset target = target_lir->offset; 1250 int delta = target - pc; 1251 if (kVerbosePcFixup) { 1252 LOG(INFO) << "Source:"; 1253 DumpLIRInsn(lir, 0); 1254 LOG(INFO) << "Target:"; 1255 DumpLIRInsn(target_lir, 0); 1256 LOG(INFO) << "Delta " << delta; 1257 } 1258 lir->operands[0] = delta; 1259 break; 1260 } 1261 case kX86Jmp8: { 1262 LIR *target_lir = lir->target; 1263 DCHECK(target_lir != NULL); 1264 int delta = 0; 1265 CodeOffset pc; 1266 if (IS_SIMM8(lir->operands[0])) { 1267 pc = lir->offset + 2 /* opcode + rel8 */; 1268 } else { 1269 pc = lir->offset + 5 /* opcode + rel32 */; 1270 } 1271 CodeOffset target = target_lir->offset; 1272 delta = target - pc; 1273 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1274 // Useless branch 1275 NopLIR(lir); 1276 if (kVerbosePcFixup) { 1277 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1278 } 1279 res = kRetryAll; 1280 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1281 if (kVerbosePcFixup) { 1282 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1283 } 1284 lir->opcode = kX86Jmp32; 1285 SetupResourceMasks(lir); 1286 res = kRetryAll; 1287 } 1288 lir->operands[0] = delta; 1289 break; 1290 } 1291 case kX86Jmp32: { 1292 LIR *target_lir = lir->target; 1293 DCHECK(target_lir != NULL); 1294 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1295 CodeOffset target = target_lir->offset; 1296 int delta = target - pc; 1297 lir->operands[0] = delta; 1298 break; 1299 } 1300 default: 1301 break; 1302 } 1303 } 1304 1305 /* 1306 * If one of the pc-relative instructions expanded we'll have 1307 * to make another pass. Don't bother to fully assemble the 1308 * instruction. 1309 */ 1310 if (res != kSuccess) { 1311 continue; 1312 } 1313 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1314 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1315 size_t starting_cbuf_size = code_buffer_.size(); 1316 switch (entry->kind) { 1317 case kData: // 4 bytes of data 1318 code_buffer_.push_back(lir->operands[0]); 1319 break; 1320 case kNullary: // 1 byte of opcode 1321 DCHECK_EQ(0, entry->skeleton.prefix1); 1322 DCHECK_EQ(0, entry->skeleton.prefix2); 1323 code_buffer_.push_back(entry->skeleton.opcode); 1324 if (entry->skeleton.extra_opcode1 != 0) { 1325 code_buffer_.push_back(entry->skeleton.extra_opcode1); 1326 if (entry->skeleton.extra_opcode2 != 0) { 1327 code_buffer_.push_back(entry->skeleton.extra_opcode2); 1328 } 1329 } else { 1330 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1331 } 1332 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1333 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1334 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1335 break; 1336 case kRegOpcode: // lir operands - 0: reg 1337 EmitOpRegOpcode(entry, lir->operands[0]); 1338 break; 1339 case kReg: // lir operands - 0: reg 1340 EmitOpReg(entry, lir->operands[0]); 1341 break; 1342 case kMem: // lir operands - 0: base, 1: disp 1343 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1344 break; 1345 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1346 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1347 break; 1348 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1349 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1350 lir->operands[3], lir->operands[4]); 1351 break; 1352 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1353 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1354 break; 1355 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1356 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1357 lir->operands[3], lir->operands[4]); 1358 break; 1359 case kRegThread: // lir operands - 0: reg, 1: disp 1360 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1361 break; 1362 case kRegReg: // lir operands - 0: reg1, 1: reg2 1363 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1364 break; 1365 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1366 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1367 break; 1368 case kRegRegImm: 1369 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1370 break; 1371 case kRegImm: // lir operands - 0: reg, 1: immediate 1372 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1373 break; 1374 case kThreadImm: // lir operands - 0: disp, 1: immediate 1375 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1376 break; 1377 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1378 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1379 break; 1380 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1381 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1382 break; 1383 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1384 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1385 break; 1386 case kRegCond: // lir operands - 0: reg, 1: condition 1387 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1388 break; 1389 case kJmp: // lir operands - 0: rel 1390 EmitJmp(entry, lir->operands[0]); 1391 break; 1392 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1393 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1394 break; 1395 case kCall: 1396 switch (entry->opcode) { 1397 case kX86CallM: // lir operands - 0: base, 1: disp 1398 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1399 break; 1400 case kX86CallT: // lir operands - 0: disp 1401 EmitCallThread(entry, lir->operands[0]); 1402 break; 1403 default: 1404 EmitUnimplemented(entry, lir); 1405 break; 1406 } 1407 break; 1408 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1409 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1410 lir->operands[3], lir->operands[4]); 1411 break; 1412 case kMacro: 1413 EmitMacro(entry, lir->operands[0], lir->offset); 1414 break; 1415 default: 1416 EmitUnimplemented(entry, lir); 1417 break; 1418 } 1419 CHECK_EQ(static_cast<size_t>(GetInsnSize(lir)), 1420 code_buffer_.size() - starting_cbuf_size) 1421 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1422 } 1423 return res; 1424} 1425 1426// LIR offset assignment. 1427// TODO: consolidate w/ Arm assembly mechanism. 1428int X86Mir2Lir::AssignInsnOffsets() { 1429 LIR* lir; 1430 int offset = 0; 1431 1432 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1433 lir->offset = offset; 1434 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1435 if (!lir->flags.is_nop) { 1436 offset += lir->flags.size; 1437 } 1438 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1439 if (offset & 0x2) { 1440 offset += 2; 1441 lir->operands[0] = 1; 1442 } else { 1443 lir->operands[0] = 0; 1444 } 1445 } 1446 /* Pseudo opcodes don't consume space */ 1447 } 1448 return offset; 1449} 1450 1451/* 1452 * Walk the compilation unit and assign offsets to instructions 1453 * and literals and compute the total size of the compiled unit. 1454 * TODO: consolidate w/ Arm assembly mechanism. 1455 */ 1456void X86Mir2Lir::AssignOffsets() { 1457 int offset = AssignInsnOffsets(); 1458 1459 /* Const values have to be word aligned */ 1460 offset = (offset + 3) & ~3; 1461 1462 /* Set up offsets for literals */ 1463 data_offset_ = offset; 1464 1465 offset = AssignLiteralOffset(offset); 1466 1467 offset = AssignSwitchTablesOffset(offset); 1468 1469 offset = AssignFillArrayDataOffset(offset); 1470 1471 total_size_ = offset; 1472} 1473 1474/* 1475 * Go over each instruction in the list and calculate the offset from the top 1476 * before sending them off to the assembler. If out-of-range branch distance is 1477 * seen rearrange the instructions a bit to correct it. 1478 * TODO: consolidate w/ Arm assembly mechanism. 1479 */ 1480void X86Mir2Lir::AssembleLIR() { 1481 cu_->NewTimingSplit("Assemble"); 1482 AssignOffsets(); 1483 int assembler_retries = 0; 1484 /* 1485 * Assemble here. Note that we generate code with optimistic assumptions 1486 * and if found now to work, we'll have to redo the sequence and retry. 1487 */ 1488 1489 while (true) { 1490 AssemblerStatus res = AssembleInstructions(0); 1491 if (res == kSuccess) { 1492 break; 1493 } else { 1494 assembler_retries++; 1495 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1496 CodegenDump(); 1497 LOG(FATAL) << "Assembler error - too many retries"; 1498 } 1499 // Redo offsets and try again 1500 AssignOffsets(); 1501 code_buffer_.clear(); 1502 } 1503 } 1504 1505 // Install literals 1506 InstallLiteralPools(); 1507 1508 // Install switch tables 1509 InstallSwitchTables(); 1510 1511 // Install fill array data 1512 InstallFillArrayData(); 1513 1514 // Create the mapping table and native offset to reference map. 1515 cu_->NewTimingSplit("PcMappingTable"); 1516 CreateMappingTables(); 1517 1518 cu_->NewTimingSplit("GcMap"); 1519 CreateNativeGcMap(); 1520} 1521 1522} // namespace art 1523