assemble_x86.cc revision e63d9d4e42e659a365a9a06b910852ebc297f457
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "x86_lir.h" 20 21namespace art { 22 23#define MAX_ASSEMBLER_RETRIES 50 24 25const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { 26 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" }, 27 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" }, 28 { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" }, 29 30#define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \ 31 rm8_r8, rm32_r32, \ 32 r8_rm8, r32_rm32, \ 33 ax8_i8, ax32_i32, \ 34 rm8_i8, rm8_i8_modrm, \ 35 rm32_i32, rm32_i32_modrm, \ 36 rm32_i8, rm32_i8_modrm) \ 37{ kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \ 38{ kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true}, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 39{ kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \ 40{ kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \ 41{ kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \ 42{ kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 43{ kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \ 44{ kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \ 45{ kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ 46{ kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 47{ kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, true }, #opname "8TI", "fs:[!0d],!1d" }, \ 48 \ 49{ kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \ 50{ kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 51{ kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \ 52{ kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \ 53{ kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \ 54{ kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 55{ kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \ 56{ kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \ 57{ kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 58{ kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 59{ kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \ 60{ kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \ 61{ kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \ 62{ kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 63{ kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \ 64 \ 65{ kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \ 66{ kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 67{ kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \ 68{ kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \ 69{ kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \ 70{ kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 71{ kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \ 72{ kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \ 73{ kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 74{ kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 75{ kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \ 76{ kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \ 77{ kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \ 78{ kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 79{ kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \ 80 \ 81{ kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \ 82{ kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \ 83{ kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \ 84{ kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \ 85{ kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \ 86{ kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \ 87{ kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \ 88{ kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \ 89{ kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 90{ kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 91{ kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \ 92{ kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \ 93{ kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \ 94{ kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \ 95{ kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" } 96 97ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0, 98 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */, 99 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */, 100 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */, 101 0x80, 0x0 /* RegMem8/imm8 */, 102 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */), 103ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0, 104 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */, 105 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */, 106 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */, 107 0x80, 0x1 /* RegMem8/imm8 */, 108 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */), 109ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 110 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */, 111 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */, 112 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */, 113 0x80, 0x2 /* RegMem8/imm8 */, 114 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */), 115ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES, 116 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */, 117 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */, 118 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */, 119 0x80, 0x3 /* RegMem8/imm8 */, 120 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */), 121ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0, 122 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */, 123 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */, 124 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */, 125 0x80, 0x4 /* RegMem8/imm8 */, 126 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */), 127ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0, 128 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */, 129 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */, 130 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */, 131 0x80, 0x5 /* RegMem8/imm8 */, 132 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */), 133ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0, 134 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */, 135 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */, 136 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */, 137 0x80, 0x6 /* RegMem8/imm8 */, 138 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */), 139ENCODING_MAP(Cmp, IS_LOAD, 0, 0, 140 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */, 141 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */, 142 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */, 143 0x80, 0x7 /* RegMem8/imm8 */, 144 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */), 145#undef ENCODING_MAP 146 147 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" }, 148 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" }, 149 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 150 151 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" }, 152 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" }, 153 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 154 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" }, 155 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" }, 156 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 157 158 { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" }, 159 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" }, 160 { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 161 { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" }, 162 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" }, 163 { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" }, 164 165 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" }, 166 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" }, 167 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" }, 168 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" }, 169 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" }, 170 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 171 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" }, 172 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" }, 173 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8MI", "[!0r+!1d],!2d" }, 174 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 175 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, true }, "Mov8TI", "fs:[!0d],!1d" }, 176 177 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" }, 178 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" }, 179 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" }, 180 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" }, 181 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" }, 182 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 183 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" }, 184 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" }, 185 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" }, 186 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 187 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" }, 188 189 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, 190 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, 191 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, 192 { kX86Mov32RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, 193 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, 194 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 195 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" }, 196 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" }, 197 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" }, 198 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 199 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" }, 200 201 { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" }, 202 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 203 204 { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, 205 { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, 206 { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, 207 { kX86Mov64RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, 208 { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, 209 { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 210 { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" }, 211 { kX86Mov64RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI", "!0r,!1d" }, 212 { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" }, 213 { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 214 { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" }, 215 216 { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | IS_LOAD | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" }, 217 { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, 218 219 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" }, 220 { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" }, 221 222 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" }, 223 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" }, 224 225#define SHIFT_ENCODING_MAP(opname, modrm_opcode) \ 226{ kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \ 227{ kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \ 228{ kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 229{ kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \ 230{ kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \ 231{ kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 232 \ 233{ kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \ 234{ kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \ 235{ kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 236{ kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \ 237{ kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \ 238{ kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 239 \ 240{ kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \ 241{ kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \ 242{ kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 243{ kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \ 244{ kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \ 245{ kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \ 246 \ 247{ kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \ 248{ kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \ 249{ kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \ 250{ kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \ 251{ kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \ 252{ kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" } 253 254 SHIFT_ENCODING_MAP(Rol, 0x0), 255 SHIFT_ENCODING_MAP(Ror, 0x1), 256 SHIFT_ENCODING_MAP(Rcl, 0x2), 257 SHIFT_ENCODING_MAP(Rcr, 0x3), 258 SHIFT_ENCODING_MAP(Sal, 0x4), 259 SHIFT_ENCODING_MAP(Shr, 0x5), 260 SHIFT_ENCODING_MAP(Sar, 0x7), 261#undef SHIFT_ENCODING_MAP 262 263 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" }, 264 { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" }, 265 { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" }, 266 { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" }, 267 { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" }, 268 { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" }, 269 { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" }, 270 { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" }, 271 { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" }, 272 273 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" }, 274 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" }, 275 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" }, 276 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" }, 277 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" }, 278 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" }, 279 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" }, 280 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" }, 281 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" }, 282 { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" }, 283 { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" }, 284 { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" }, 285 286 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" }, 287 { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" }, 288 289#define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \ 290 reg, reg_kind, reg_flags, \ 291 mem, mem_kind, mem_flags, \ 292 arr, arr_kind, arr_flags, imm, \ 293 b_flags, hw_flags, w_flags, \ 294 b_format, hw_format, w_format) \ 295{ kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \ 296{ kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \ 297{ kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \ 298{ kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \ 299{ kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \ 300{ kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \ 301{ kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \ 302{ kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \ 303{ kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \ 304{ kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \ 305{ kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \ 306{ kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" } 307 308 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 309 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""), 310 311 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 312 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"), 313 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 314 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"), 315#undef UNARY_ENCODING_MAP 316 317 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" }, 318 { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" }, 319 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" }, 320 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" }, 321 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" }, 322 323#define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 324{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 325{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 326{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 327 328#define EXT_0F_REX_NO_PREFIX_ENCODING_MAP(opname, opcode, reg_def) \ 329{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { REX, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 330{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { REX, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 331{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { REX, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 332 333#define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \ 334{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 335{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 336{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 337 338#define EXT_0F_REX_W_NO_PREFIX_ENCODING_MAP(opname, opcode, reg_def) \ 339{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { REX_W, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 340{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { REX_W, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 341{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { REX_W, 0x00, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 342 343#define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \ 344{ kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \ 345{ kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \ 346{ kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" } 347 348 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0), 349 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" }, 350 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" }, 351 352 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0), 353 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" }, 354 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" }, 355 356 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0), 357 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0), 358 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0), 359 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0), 360 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0), 361 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0), 362 EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0), 363 EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0), 364 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0), 365 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0), 366 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0), 367 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0), 368 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0), 369 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0), 370 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0), 371 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0), 372 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0), 373 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0), 374 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0), 375 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0), 376 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0), 377 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0), 378 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0), 379 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0), 380 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0), 381 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0), 382 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0), 383 EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0), 384 EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0), 385 EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0), 386 EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0), 387 EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0), 388 EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0), 389 EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0), 390 EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0), 391 EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0), 392 EXT_0F_ENCODING_MAP(Addpd, 0xF2, 0x58, REG_DEF0_USE0), 393 EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0), 394 EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0), 395 EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0), 396 EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0), 397 EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0), 398 EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0), 399 EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0), 400 EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0), 401 EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0), 402 EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0), 403 404 { kX86PextrbRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" }, 405 { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" }, 406 { kX86PextrdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" }, 407 408 { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" }, 409 { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" }, 410 411 { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" }, 412 { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" }, 413 { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" }, 414 { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" }, 415 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" }, 416 { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" }, 417 { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" }, 418 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" }, 419 420 { kX86Fild32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" }, 421 { kX86Fild64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" }, 422 { kX86Fld32M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" }, 423 { kX86Fld64M, kMem, IS_LOAD | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" }, 424 { kX86Fstp32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" }, 425 { kX86Fstp64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" }, 426 { kX86Fst32M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" }, 427 { kX86Fst64M, kMem, IS_STORE | IS_UNARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" }, 428 { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" }, 429 { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" }, 430 { kX86Fstsw16R, kNullary, NO_OPERAND | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" }, 431 432 EXT_0F_ENCODING_MAP(Mova128, 0x66, 0x6F, REG_DEF0), 433 { kX86Mova128MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128MR", "[!0r+!1d],!2r" }, 434 { kX86Mova128AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "Mova128AR", "[!0r+!1r<<!2d+!3d],!4r" }, 435 436 437 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0), 438 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" }, 439 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 440 441 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0), 442 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" }, 443 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 444 445 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" }, 446 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 447 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" }, 448 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 449 450 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" }, 451 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 452 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" }, 453 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" }, 454 455 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0), 456 EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0), 457 { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" }, 458 { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" }, 459 { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 460 461 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" }, 462 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" }, 463 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" }, 464 465 { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" }, 466 { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" }, 467 { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" }, 468 469 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" }, 470 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" }, 471 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" }, 472 473 // TODO: load/store? 474 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly. 475 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" }, 476 477 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 478 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 479 EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES), 480 481 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" }, 482 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" }, 483 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 484 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" }, 485 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" }, 486 { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" }, 487 { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" }, 488 { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" }, 489 490 EXT_0F_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0), 491 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0), 492 EXT_0F_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0), 493 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0), 494 EXT_0F_REX_NO_PREFIX_ENCODING_MAP(Movzx8q, 0xB6, REG_DEF0), 495 EXT_0F_REX_W_NO_PREFIX_ENCODING_MAP(Movzx16q, 0xB7, REG_DEF0), 496 EXT_0F_REX_NO_PREFIX_ENCODING_MAP(Movsx8q, 0xBE, REG_DEF0), 497 EXT_0F_REX_W_NO_PREFIX_ENCODING_MAP(Movsx16q, 0xBF, REG_DEF0), 498#undef EXT_0F_ENCODING_MAP 499 500 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" }, 501 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" }, 502 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" }, 503 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" }, 504 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" }, 505 { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" }, 506 { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" }, 507 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" }, 508 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" }, 509 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" }, 510 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" }, 511 { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" }, 512 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" }, 513 514 { kX86StartOfMethod, kMacro, IS_UNARY_OP | SETS_CCODES, { 0, 0, 0, 0, 0, 0, 0, 0, false }, "StartOfMethod", "!0r" }, 515 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" }, 516 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1d" }, 517 { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" }, 518}; 519 520static bool NeedsRex(int32_t raw_reg) { 521 return RegStorage::RegNum(raw_reg) > 7; 522} 523 524static uint8_t LowRegisterBits(int32_t raw_reg) { 525 uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits 526 DCHECK_LT(low_reg, 8); 527 return low_reg; 528} 529 530static bool HasModrm(const X86EncodingMap* entry) { 531 switch (entry->kind) { 532 case kNullary: return false; 533 case kRegOpcode: return false; 534 default: return true; 535 } 536} 537 538static bool HasSib(const X86EncodingMap* entry) { 539 switch (entry->kind) { 540 case kArray: return true; 541 case kArrayReg: return true; 542 case kRegArray: return true; 543 case kArrayImm: return true; 544 case kRegArrayImm: return true; 545 case kShiftArrayImm: return true; 546 case kShiftArrayCl: return true; 547 case kArrayCond: return true; 548 case kCall: 549 switch (entry->opcode) { 550 case kX86CallA: return true; 551 default: return false; 552 } 553 case kPcRel: return true; 554 switch (entry->opcode) { 555 case kX86PcRelLoadRA: return true; 556 default: return false; 557 } 558 default: return false; 559 } 560} 561 562static bool ModrmIsRegReg(const X86EncodingMap* entry) { 563 switch (entry->kind) { 564 // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the 565 // modrm: 566 case kNullary: return true; 567 case kRegOpcode: return true; 568 case kMovRegImm: return true; 569 // Regular modrm value of 3 cases, when there is one register the other register holds an 570 // opcode so the base register is special. 571 case kReg: return true; 572 case kRegReg: return true; 573 case kRegRegStore: return true; 574 case kRegImm: return true; 575 case kRegRegImm: return true; 576 case kRegRegImmStore: return true; 577 case kShiftRegImm: return true; 578 case kShiftRegCl: return true; 579 case kRegCond: return true; 580 case kRegRegCond: return true; 581 case kJmp: 582 switch (entry->opcode) { 583 case kX86JmpR: return true; 584 default: return false; 585 } 586 case kCall: 587 switch (entry->opcode) { 588 case kX86CallR: return true; 589 default: return false; 590 } 591 default: return false; 592 } 593} 594 595size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 596 int32_t raw_base, int32_t displacement) { 597 bool has_modrm = HasModrm(entry); 598 bool has_sib = HasSib(entry); 599 bool r8_form = entry->skeleton.r8_form; 600 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 601 if (has_sib) { 602 DCHECK(!modrm_is_reg_reg); 603 } 604 size_t size = 0; 605 if (entry->skeleton.prefix1 > 0) { 606 ++size; 607 if (entry->skeleton.prefix2 > 0) { 608 ++size; 609 } 610 } 611 if (Gen64Bit() || kIsDebugBuild) { 612 bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base); 613 if (r8_form) { 614 // Do we need an empty REX prefix to normalize byte registers? 615 registers_need_rex_prefix = registers_need_rex_prefix || (RegStorage::RegNum(raw_reg) >= 4); 616 registers_need_rex_prefix = registers_need_rex_prefix || 617 (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4)); 618 } 619 if (registers_need_rex_prefix) { 620 DCHECK(Gen64Bit()) << "Attempt to use a 64-bit only addressable register " 621 << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name; 622 if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W) { 623 ++size; // rex 624 } 625 } 626 } 627 ++size; // opcode 628 if (entry->skeleton.opcode == 0x0F) { 629 ++size; 630 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 631 ++size; 632 } 633 } 634 if (has_modrm) { 635 ++size; // modrm 636 } 637 if (!modrm_is_reg_reg) { 638 if (has_sib || LowRegisterBits(raw_base) == rs_rX86_SP.GetRegNum() 639 || (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX)) { 640 // SP requires a SIB byte. 641 // GS access also needs a SIB byte for absolute adressing in 64-bit mode. 642 ++size; 643 } 644 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { 645 // BP requires an explicit displacement, even when it's 0. 646 if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA) { 647 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name; 648 } 649 size += IS_SIMM8(displacement) ? 1 : 4; 650 } 651 } 652 size += entry->skeleton.immediate_bytes; 653 return size; 654} 655 656size_t X86Mir2Lir::GetInsnSize(LIR* lir) { 657 DCHECK(!IsPseudoLirOp(lir->opcode)); 658 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 659 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name; 660 661 switch (entry->kind) { 662 case kData: 663 return 4; // 4 bytes of data. 664 case kNop: 665 return lir->operands[0]; // Length of nop is sole operand. 666 case kNullary: 667 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0); 668 case kRegOpcode: // lir operands - 0: reg 669 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 670 case kReg: // lir operands - 0: reg 671 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 672 case kMem: // lir operands - 0: base, 1: disp 673 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 674 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 675 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 676 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 677 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 678 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 679 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]); 680 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 681 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 682 lir->operands[3]); 683 case kThreadReg: // lir operands - 0: disp, 1: reg 684 // Thread displacement size is always 32bit. 685 return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678); 686 case kRegReg: // lir operands - 0: reg1, 1: reg2 687 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 688 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 689 return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0); 690 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 691 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 692 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 693 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 694 lir->operands[4]); 695 case kRegThread: // lir operands - 0: reg, 1: disp 696 // Thread displacement size is always 32bit. 697 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678); 698 case kRegImm: { // lir operands - 0: reg, 1: immediate 699 size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 700 // AX opcodes don't require the modrm byte. 701 if (entry->skeleton.ax_opcode == 0) { 702 return size; 703 } else { 704 return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 705 } 706 } 707 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 708 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 709 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 710 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 711 case kThreadImm: // lir operands - 0: disp, 1: imm 712 // Thread displacement size is always 32bit. 713 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 714 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 715 // Note: RegRegImm form passes reg2 as index but encodes it using base. 716 return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0); 717 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 718 // Note: RegRegImmStore form passes reg1 as index but encodes it using base. 719 return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0); 720 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 721 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 722 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm 723 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 724 lir->operands[4]); 725 case kMovRegImm: // lir operands - 0: reg, 1: immediate 726 return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 + 727 entry->skeleton.immediate_bytes; 728 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 729 // Shift by immediate one has a shorter opcode. 730 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) - 731 (lir->operands[1] == 1 ? 1 : 0); 732 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate 733 // Shift by immediate one has a shorter opcode. 734 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) - 735 (lir->operands[2] == 1 ? 1 : 0); 736 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate 737 // Shift by immediate one has a shorter opcode. 738 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) - 739 (lir->operands[4] == 1 ? 1 : 0); 740 case kShiftRegCl: // lir operands - 0: reg, 1: cl 741 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1])); 742 // Note: ShiftRegCl form passes reg as reg but encodes it using base. 743 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0); 744 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl 745 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2])); 746 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 747 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl 748 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4])); 749 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0], 750 lir->operands[3]); 751 case kRegCond: // lir operands - 0: reg, 1: cond 752 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0); 753 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond 754 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 755 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond 756 DCHECK_EQ(false, entry->skeleton.r8_form); 757 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 758 case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond 759 DCHECK_EQ(false, entry->skeleton.r8_form); 760 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0); 761 case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond 762 DCHECK_EQ(false, entry->skeleton.r8_form); 763 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]); 764 case kJcc: 765 if (lir->opcode == kX86Jcc8) { 766 return 2; // opcode + rel8 767 } else { 768 DCHECK(lir->opcode == kX86Jcc32); 769 return 6; // 2 byte opcode + rel32 770 } 771 case kJmp: 772 if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) { 773 return 2; // opcode + rel8 774 } else if (lir->opcode == kX86Jmp32) { 775 return 5; // opcode + rel32 776 } else if (lir->opcode == kX86JmpT) { 777 // Thread displacement size is always 32bit. 778 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 779 } else { 780 DCHECK(lir->opcode == kX86JmpR); 781 if (NeedsRex(lir->operands[0])) { 782 return 3; // REX.B + opcode + modrm 783 } else { 784 return 2; // opcode + modrm 785 } 786 } 787 case kCall: 788 switch (lir->opcode) { 789 case kX86CallI: return 5; // opcode 0:disp 790 case kX86CallR: return 2; // opcode modrm 791 case kX86CallM: // lir operands - 0: base, 1: disp 792 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]); 793 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp 794 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]); 795 case kX86CallT: // lir operands - 0: disp 796 // Thread displacement size is always 32bit. 797 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678); 798 default: 799 break; 800 } 801 break; 802 case kPcRel: 803 if (entry->opcode == kX86PcRelLoadRA) { 804 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 805 // Force the displacement size to 32bit, it will hold a computed offset later. 806 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1], 807 0x12345678); 808 } else { 809 DCHECK_EQ(entry->opcode, kX86PcRelAdr); 810 return 5; // opcode with reg + 4 byte immediate 811 } 812 case kMacro: // lir operands - 0: reg 813 DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod)); 814 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ + 815 ComputeSize(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], 816 lir->operands[0], NO_REG, NO_REG, 0) - 817 // Shorter ax encoding. 818 (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0); 819 case kUnimplemented: 820 break; 821 } 822 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; 823 return 0; 824} 825 826static uint8_t ModrmForDisp(int base, int disp) { 827 // BP requires an explicit disp, so do not omit it in the 0 case 828 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 829 return 0; 830 } else if (IS_SIMM8(disp)) { 831 return 1; 832 } else { 833 return 2; 834 } 835} 836 837void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { 838 if (kIsDebugBuild) { 839 // Sanity check r8_form is correctly specified. 840 if (entry->skeleton.r8_form) { 841 CHECK(strchr(entry->name, '8') != nullptr) << entry->name; 842 } else { 843 if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions. 844 if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8") 845 && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) { 846 CHECK(strchr(entry->name, '8') == nullptr) << entry->name; 847 } 848 } 849 } 850 if (RegStorage::RegNum(raw_reg) >= 4) { 851 // ah, bh, ch and dh are not valid registers in 32-bit. 852 CHECK(Gen64Bit() || !entry->skeleton.r8_form) 853 << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg)) 854 << " for instruction " << entry->name << " in " 855 << PrettyMethod(cu_->method_idx, *cu_->dex_file); 856 } 857 } 858} 859 860void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, 861 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 862 // REX.WRXB 863 // W - 64-bit operand 864 // R - MODRM.reg 865 // X - SIB.index 866 // B - MODRM.rm/SIB.base 867 bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W); 868 bool r = NeedsRex(raw_reg_r); 869 bool x = NeedsRex(raw_reg_x); 870 bool b = NeedsRex(raw_reg_b); 871 bool r8_form = entry->skeleton.r8_form; 872 bool modrm_is_reg_reg = ModrmIsRegReg(entry); 873 874 uint8_t rex = 0; 875 if (r8_form) { 876 // Do we need an empty REX prefix to normalize byte register addressing? 877 if (RegStorage::RegNum(raw_reg_r) >= 4) { 878 rex |= 0x40; // REX.0000 879 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) { 880 rex |= 0x40; // REX.0000 881 } 882 } 883 if (w) { 884 rex |= 0x48; // REX.W000 885 } 886 if (r) { 887 rex |= 0x44; // REX.0R00 888 } 889 if (x) { 890 rex |= 0x42; // REX.00X0 891 } 892 if (b) { 893 rex |= 0x41; // REX.000B 894 } 895 if (entry->skeleton.prefix1 != 0) { 896 if (Gen64Bit() && entry->skeleton.prefix1 == THREAD_PREFIX) { 897 // 64 bit addresses by GS, not FS. 898 code_buffer_.push_back(THREAD_PREFIX_GS); 899 } else { 900 if (entry->skeleton.prefix1 == REX_W) { 901 rex |= entry->skeleton.prefix1; 902 code_buffer_.push_back(rex); 903 rex = 0; 904 } else { 905 code_buffer_.push_back(entry->skeleton.prefix1); 906 } 907 } 908 if (entry->skeleton.prefix2 != 0) { 909 if (entry->skeleton.prefix2 == REX_W) { 910 rex |= entry->skeleton.prefix2; 911 code_buffer_.push_back(rex); 912 rex = 0; 913 } else { 914 code_buffer_.push_back(entry->skeleton.prefix2); 915 } 916 } 917 } else { 918 DCHECK_EQ(0, entry->skeleton.prefix2); 919 } 920 if (rex != 0) { 921 DCHECK(Gen64Bit()); 922 code_buffer_.push_back(rex); 923 } 924} 925 926void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { 927 code_buffer_.push_back(entry->skeleton.opcode); 928 if (entry->skeleton.opcode == 0x0F) { 929 code_buffer_.push_back(entry->skeleton.extra_opcode1); 930 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { 931 code_buffer_.push_back(entry->skeleton.extra_opcode2); 932 } else { 933 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 934 } 935 } else { 936 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 937 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 938 } 939} 940 941void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, 942 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) { 943 EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b); 944 EmitOpcode(entry); 945} 946 947void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { 948 // BP requires an explicit disp, so do not omit it in the 0 case 949 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) { 950 return; 951 } else if (IS_SIMM8(disp)) { 952 code_buffer_.push_back(disp & 0xFF); 953 } else { 954 code_buffer_.push_back(disp & 0xFF); 955 code_buffer_.push_back((disp >> 8) & 0xFF); 956 code_buffer_.push_back((disp >> 16) & 0xFF); 957 code_buffer_.push_back((disp >> 24) & 0xFF); 958 } 959} 960 961void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) { 962 if (Gen64Bit()) { 963 // Absolute adressing for GS access. 964 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP.GetRegNum(); 965 code_buffer_.push_back(modrm); 966 uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP.GetRegNum() << 3) | rs_rBP.GetRegNum(); 967 code_buffer_.push_back(sib); 968 } else { 969 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum(); 970 code_buffer_.push_back(modrm); 971 } 972} 973 974void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) { 975 DCHECK_LT(reg_or_opcode, 8); 976 DCHECK_LT(base, 8); 977 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base; 978 code_buffer_.push_back(modrm); 979 if (base == rs_rX86_SP.GetRegNum()) { 980 // Special SIB for SP base 981 code_buffer_.push_back(0 << 6 | rs_rX86_SP.GetRegNum() << 3 | rs_rX86_SP.GetRegNum()); 982 } 983 EmitDisp(base, disp); 984} 985 986void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, 987 int scale, int32_t disp) { 988 DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8); 989 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 | 990 rs_rX86_SP.GetRegNum(); 991 code_buffer_.push_back(modrm); 992 DCHECK_LT(scale, 4); 993 DCHECK_LT(RegStorage::RegNum(index), 8); 994 DCHECK_LT(RegStorage::RegNum(base), 8); 995 uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base); 996 code_buffer_.push_back(sib); 997 EmitDisp(base, disp); 998} 999 1000void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) { 1001 switch (entry->skeleton.immediate_bytes) { 1002 case 1: 1003 DCHECK(IS_SIMM8(imm)); 1004 code_buffer_.push_back(imm & 0xFF); 1005 break; 1006 case 2: 1007 DCHECK(IS_SIMM16(imm)); 1008 code_buffer_.push_back(imm & 0xFF); 1009 code_buffer_.push_back((imm >> 8) & 0xFF); 1010 break; 1011 case 4: 1012 DCHECK(IS_SIMM32(imm)); 1013 code_buffer_.push_back(imm & 0xFF); 1014 code_buffer_.push_back((imm >> 8) & 0xFF); 1015 code_buffer_.push_back((imm >> 16) & 0xFF); 1016 code_buffer_.push_back((imm >> 24) & 0xFF); 1017 break; 1018 case 8: 1019 code_buffer_.push_back(imm & 0xFF); 1020 code_buffer_.push_back((imm >> 8) & 0xFF); 1021 code_buffer_.push_back((imm >> 16) & 0xFF); 1022 code_buffer_.push_back((imm >> 24) & 0xFF); 1023 code_buffer_.push_back((imm >> 32) & 0xFF); 1024 code_buffer_.push_back((imm >> 40) & 0xFF); 1025 code_buffer_.push_back((imm >> 48) & 0xFF); 1026 code_buffer_.push_back((imm >> 56) & 0xFF); 1027 break; 1028 default: 1029 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes 1030 << ") for instruction: " << entry->name; 1031 break; 1032 } 1033} 1034 1035void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) { 1036 DCHECK_EQ(false, entry->skeleton.r8_form); 1037 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1038 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1039 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1040 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1041} 1042 1043void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) { 1044 DCHECK_EQ(false, entry->skeleton.r8_form); 1045 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1046 // There's no 3-byte instruction with +rd 1047 DCHECK(entry->skeleton.opcode != 0x0F || 1048 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A)); 1049 DCHECK(!RegStorage::IsFloat(raw_reg)); 1050 uint8_t low_reg = LowRegisterBits(raw_reg); 1051 code_buffer_.back() += low_reg; 1052 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1053 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1054} 1055 1056void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) { 1057 CheckValidByteRegister(entry, raw_reg); 1058 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg); 1059 uint8_t low_reg = LowRegisterBits(raw_reg); 1060 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1061 code_buffer_.push_back(modrm); 1062 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1063 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1064} 1065 1066void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1067 DCHECK_EQ(false, entry->skeleton.r8_form); 1068 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1069 code_buffer_.push_back(entry->skeleton.opcode); 1070 DCHECK_NE(0x0F, entry->skeleton.opcode); 1071 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1072 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1073 uint8_t low_base = LowRegisterBits(raw_base); 1074 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1075 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1076 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1077} 1078 1079void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1080 int scale, int32_t disp) { 1081 DCHECK_EQ(false, entry->skeleton.r8_form); 1082 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1083 uint8_t low_index = LowRegisterBits(raw_index); 1084 uint8_t low_base = LowRegisterBits(raw_base); 1085 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1086 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1087 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1088} 1089 1090void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1091 int32_t raw_reg) { 1092 CheckValidByteRegister(entry, raw_reg); 1093 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1094 uint8_t low_reg = LowRegisterBits(raw_reg); 1095 uint8_t low_base = LowRegisterBits(raw_base); 1096 EmitModrmDisp(low_reg, low_base, disp); 1097 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1098 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1099 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1100} 1101 1102void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1103 int32_t disp) { 1104 // Opcode will flip operands. 1105 EmitMemReg(entry, raw_base, disp, raw_reg); 1106} 1107 1108void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 1109 int32_t raw_index, int scale, int32_t disp) { 1110 CheckValidByteRegister(entry, raw_reg); 1111 EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base); 1112 uint8_t low_reg = LowRegisterBits(raw_reg); 1113 uint8_t low_index = LowRegisterBits(raw_index); 1114 uint8_t low_base = LowRegisterBits(raw_base); 1115 EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp); 1116 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1117 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1118 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1119} 1120 1121void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, 1122 int scale, int32_t disp, int32_t raw_reg) { 1123 // Opcode will flip operands. 1124 EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp); 1125} 1126 1127void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1128 int32_t imm) { 1129 DCHECK_EQ(false, entry->skeleton.r8_form); 1130 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1131 uint8_t low_base = LowRegisterBits(raw_base); 1132 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1133 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1134 EmitImm(entry, imm); 1135} 1136 1137void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry, 1138 int32_t raw_base, int32_t raw_index, int scale, int32_t disp, 1139 int32_t imm) { 1140 DCHECK_EQ(false, entry->skeleton.r8_form); 1141 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base); 1142 uint8_t low_index = LowRegisterBits(raw_index); 1143 uint8_t low_base = LowRegisterBits(raw_base); 1144 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp); 1145 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1146 EmitImm(entry, imm); 1147} 1148 1149void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) { 1150 DCHECK_EQ(false, entry->skeleton.r8_form); 1151 DCHECK_NE(entry->skeleton.prefix1, 0); 1152 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG); 1153 uint8_t low_reg = LowRegisterBits(raw_reg); 1154 EmitModrmThread(low_reg); 1155 code_buffer_.push_back(disp & 0xFF); 1156 code_buffer_.push_back((disp >> 8) & 0xFF); 1157 code_buffer_.push_back((disp >> 16) & 0xFF); 1158 code_buffer_.push_back((disp >> 24) & 0xFF); 1159 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1160 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1161 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1162} 1163 1164void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) { 1165 CheckValidByteRegister(entry, raw_reg1); 1166 CheckValidByteRegister(entry, raw_reg2); 1167 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1168 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1169 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1170 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1171 code_buffer_.push_back(modrm); 1172 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1173 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1174 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1175} 1176 1177void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1178 int32_t imm) { 1179 DCHECK_EQ(false, entry->skeleton.r8_form); 1180 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1181 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1182 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1183 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2; 1184 code_buffer_.push_back(modrm); 1185 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1186 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1187 EmitImm(entry, imm); 1188} 1189 1190void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry, 1191 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) { 1192 DCHECK(!RegStorage::IsFloat(raw_reg)); 1193 CheckValidByteRegister(entry, raw_reg); 1194 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base); 1195 uint8_t low_reg = LowRegisterBits(raw_reg); 1196 uint8_t low_base = LowRegisterBits(raw_base); 1197 EmitModrmDisp(low_reg, low_base, disp); 1198 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1199 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1200 EmitImm(entry, imm); 1201} 1202 1203void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry, 1204 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) { 1205 // Opcode will flip operands. 1206 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm); 1207} 1208 1209void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1210 CheckValidByteRegister(entry, raw_reg); 1211 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1212 if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) { 1213 code_buffer_.push_back(entry->skeleton.ax_opcode); 1214 } else { 1215 uint8_t low_reg = LowRegisterBits(raw_reg); 1216 EmitOpcode(entry); 1217 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1218 code_buffer_.push_back(modrm); 1219 } 1220 EmitImm(entry, imm); 1221} 1222 1223void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) { 1224 DCHECK_EQ(false, entry->skeleton.r8_form); 1225 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1226 EmitModrmThread(entry->skeleton.modrm_opcode); 1227 code_buffer_.push_back(disp & 0xFF); 1228 code_buffer_.push_back((disp >> 8) & 0xFF); 1229 code_buffer_.push_back((disp >> 16) & 0xFF); 1230 code_buffer_.push_back((disp >> 24) & 0xFF); 1231 EmitImm(entry, imm); 1232 DCHECK_EQ(entry->skeleton.ax_opcode, 0); 1233} 1234 1235void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) { 1236 DCHECK_EQ(false, entry->skeleton.r8_form); 1237 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1238 uint8_t low_reg = LowRegisterBits(raw_reg); 1239 code_buffer_.push_back(0xB8 + low_reg); 1240 switch (entry->skeleton.immediate_bytes) { 1241 case 4: 1242 code_buffer_.push_back(imm & 0xFF); 1243 code_buffer_.push_back((imm >> 8) & 0xFF); 1244 code_buffer_.push_back((imm >> 16) & 0xFF); 1245 code_buffer_.push_back((imm >> 24) & 0xFF); 1246 break; 1247 case 8: 1248 code_buffer_.push_back(imm & 0xFF); 1249 code_buffer_.push_back((imm >> 8) & 0xFF); 1250 code_buffer_.push_back((imm >> 16) & 0xFF); 1251 code_buffer_.push_back((imm >> 24) & 0xFF); 1252 code_buffer_.push_back((imm >> 32) & 0xFF); 1253 code_buffer_.push_back((imm >> 40) & 0xFF); 1254 code_buffer_.push_back((imm >> 48) & 0xFF); 1255 code_buffer_.push_back((imm >> 56) & 0xFF); 1256 break; 1257 default: 1258 LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: " 1259 << static_cast<uint32_t>(entry->skeleton.immediate_bytes); 1260 } 1261} 1262 1263void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) { 1264 CheckValidByteRegister(entry, raw_reg); 1265 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1266 if (imm != 1) { 1267 code_buffer_.push_back(entry->skeleton.opcode); 1268 } else { 1269 // Shorter encoding for 1 bit shift 1270 code_buffer_.push_back(entry->skeleton.ax_opcode); 1271 } 1272 DCHECK_NE(0x0F, entry->skeleton.opcode); 1273 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1274 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1275 uint8_t low_reg = LowRegisterBits(raw_reg); 1276 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1277 code_buffer_.push_back(modrm); 1278 if (imm != 1) { 1279 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1280 DCHECK(IS_SIMM8(imm)); 1281 code_buffer_.push_back(imm & 0xFF); 1282 } 1283} 1284 1285void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) { 1286 CheckValidByteRegister(entry, raw_reg); 1287 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1288 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1289 code_buffer_.push_back(entry->skeleton.opcode); 1290 DCHECK_NE(0x0F, entry->skeleton.opcode); 1291 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1292 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1293 uint8_t low_reg = LowRegisterBits(raw_reg); 1294 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1295 code_buffer_.push_back(modrm); 1296 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1297 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1298} 1299 1300void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, 1301 int32_t displacement, int32_t raw_cl) { 1302 DCHECK_EQ(false, entry->skeleton.r8_form); 1303 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl)); 1304 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1305 code_buffer_.push_back(entry->skeleton.opcode); 1306 DCHECK_NE(0x0F, entry->skeleton.opcode); 1307 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1308 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1309 uint8_t low_base = LowRegisterBits(raw_base); 1310 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); 1311 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1312 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1313} 1314 1315void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1316 int32_t imm) { 1317 DCHECK_EQ(false, entry->skeleton.r8_form); 1318 EmitPrefix(entry, NO_REG, NO_REG, raw_base); 1319 if (imm != 1) { 1320 code_buffer_.push_back(entry->skeleton.opcode); 1321 } else { 1322 // Shorter encoding for 1 bit shift 1323 code_buffer_.push_back(entry->skeleton.ax_opcode); 1324 } 1325 DCHECK_NE(0x0F, entry->skeleton.opcode); 1326 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1327 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1328 uint8_t low_base = LowRegisterBits(raw_base); 1329 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1330 if (imm != 1) { 1331 DCHECK_EQ(entry->skeleton.immediate_bytes, 1); 1332 DCHECK(IS_SIMM8(imm)); 1333 code_buffer_.push_back(imm & 0xFF); 1334 } 1335} 1336 1337void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) { 1338 CheckValidByteRegister(entry, raw_reg); 1339 EmitPrefix(entry, NO_REG, NO_REG, raw_reg); 1340 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1341 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1342 code_buffer_.push_back(0x0F); 1343 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1344 DCHECK_GE(cc, 0); 1345 DCHECK_LT(cc, 16); 1346 code_buffer_.push_back(0x90 | cc); 1347 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1348 uint8_t low_reg = LowRegisterBits(raw_reg); 1349 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1350 code_buffer_.push_back(modrm); 1351 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1352} 1353 1354void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, 1355 int32_t cc) { 1356 DCHECK_EQ(false, entry->skeleton.r8_form); 1357 if (entry->skeleton.prefix1 != 0) { 1358 code_buffer_.push_back(entry->skeleton.prefix1); 1359 if (entry->skeleton.prefix2 != 0) { 1360 code_buffer_.push_back(entry->skeleton.prefix2); 1361 } 1362 } else { 1363 DCHECK_EQ(0, entry->skeleton.prefix2); 1364 } 1365 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1366 DCHECK_EQ(0x0F, entry->skeleton.opcode); 1367 code_buffer_.push_back(0x0F); 1368 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1); 1369 DCHECK_GE(cc, 0); 1370 DCHECK_LT(cc, 16); 1371 code_buffer_.push_back(0x90 | cc); 1372 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1373 uint8_t low_base = LowRegisterBits(raw_base); 1374 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1375 DCHECK_EQ(entry->skeleton.immediate_bytes, 0); 1376} 1377 1378void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 1379 int32_t cc) { 1380 // Generate prefix and opcode without the condition. 1381 DCHECK_EQ(false, entry->skeleton.r8_form); 1382 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2); 1383 1384 // Now add the condition. The last byte of opcode is the one that receives it. 1385 DCHECK_GE(cc, 0); 1386 DCHECK_LT(cc, 16); 1387 code_buffer_.back() += cc; 1388 1389 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1390 // two registers. 1391 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1392 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1393 1394 // For register to register encoding, the mod is 3. 1395 const uint8_t mod = (3 << 6); 1396 1397 // Encode the ModR/M byte now. 1398 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1399 uint8_t low_reg2 = LowRegisterBits(raw_reg2); 1400 const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2; 1401 code_buffer_.push_back(modrm); 1402} 1403 1404void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, 1405 int32_t disp, int32_t cc) { 1406 // Generate prefix and opcode without the condition. 1407 DCHECK_EQ(false, entry->skeleton.r8_form); 1408 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base); 1409 1410 // Now add the condition. The last byte of opcode is the one that receives it. 1411 DCHECK_GE(cc, 0); 1412 DCHECK_LT(cc, 16); 1413 code_buffer_.back() += cc; 1414 1415 // Not expecting to have to encode immediate or do anything special for ModR/M since there are 1416 // two registers. 1417 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1418 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1419 1420 uint8_t low_reg1 = LowRegisterBits(raw_reg1); 1421 uint8_t low_base = LowRegisterBits(raw_base); 1422 EmitModrmDisp(low_reg1, low_base, disp); 1423} 1424 1425void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) { 1426 if (entry->opcode == kX86Jmp8) { 1427 DCHECK(IS_SIMM8(rel)); 1428 code_buffer_.push_back(0xEB); 1429 code_buffer_.push_back(rel & 0xFF); 1430 } else if (entry->opcode == kX86Jmp32) { 1431 code_buffer_.push_back(0xE9); 1432 code_buffer_.push_back(rel & 0xFF); 1433 code_buffer_.push_back((rel >> 8) & 0xFF); 1434 code_buffer_.push_back((rel >> 16) & 0xFF); 1435 code_buffer_.push_back((rel >> 24) & 0xFF); 1436 } else if (entry->opcode == kX86Jecxz8) { 1437 DCHECK(IS_SIMM8(rel)); 1438 code_buffer_.push_back(0xE3); 1439 code_buffer_.push_back(rel & 0xFF); 1440 } else { 1441 DCHECK(entry->opcode == kX86JmpR); 1442 DCHECK_EQ(false, entry->skeleton.r8_form); 1443 EmitPrefix(entry, NO_REG, NO_REG, rel); 1444 code_buffer_.push_back(entry->skeleton.opcode); 1445 uint8_t low_reg = LowRegisterBits(rel); 1446 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg; 1447 code_buffer_.push_back(modrm); 1448 } 1449} 1450 1451void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) { 1452 DCHECK_GE(cc, 0); 1453 DCHECK_LT(cc, 16); 1454 if (entry->opcode == kX86Jcc8) { 1455 DCHECK(IS_SIMM8(rel)); 1456 code_buffer_.push_back(0x70 | cc); 1457 code_buffer_.push_back(rel & 0xFF); 1458 } else { 1459 DCHECK(entry->opcode == kX86Jcc32); 1460 code_buffer_.push_back(0x0F); 1461 code_buffer_.push_back(0x80 | cc); 1462 code_buffer_.push_back(rel & 0xFF); 1463 code_buffer_.push_back((rel >> 8) & 0xFF); 1464 code_buffer_.push_back((rel >> 16) & 0xFF); 1465 code_buffer_.push_back((rel >> 24) & 0xFF); 1466 } 1467} 1468 1469void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) { 1470 DCHECK_EQ(false, entry->skeleton.r8_form); 1471 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base); 1472 uint8_t low_base = LowRegisterBits(raw_base); 1473 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp); 1474 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1475 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1476} 1477 1478void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) { 1479 DCHECK_EQ(false, entry->skeleton.r8_form); 1480 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1481 DCHECK_EQ(4, entry->skeleton.immediate_bytes); 1482 code_buffer_.push_back(disp & 0xFF); 1483 code_buffer_.push_back((disp >> 8) & 0xFF); 1484 code_buffer_.push_back((disp >> 16) & 0xFF); 1485 code_buffer_.push_back((disp >> 24) & 0xFF); 1486 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1487} 1488 1489void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) { 1490 DCHECK_EQ(false, entry->skeleton.r8_form); 1491 DCHECK_NE(entry->skeleton.prefix1, 0); 1492 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG); 1493 EmitModrmThread(entry->skeleton.modrm_opcode); 1494 code_buffer_.push_back(disp & 0xFF); 1495 code_buffer_.push_back((disp >> 8) & 0xFF); 1496 code_buffer_.push_back((disp >> 16) & 0xFF); 1497 code_buffer_.push_back((disp >> 24) & 0xFF); 1498 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1499 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1500} 1501 1502void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 1503 int32_t raw_index, int scale, int32_t table_or_disp) { 1504 int disp; 1505 if (entry->opcode == kX86PcRelLoadRA) { 1506 Mir2Lir::EmbeddedData *tab_rec = 1507 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(table_or_disp)); 1508 disp = tab_rec->offset; 1509 } else { 1510 DCHECK(entry->opcode == kX86PcRelAdr); 1511 Mir2Lir::EmbeddedData *tab_rec = 1512 reinterpret_cast<Mir2Lir::EmbeddedData*>(UnwrapPointer(raw_base_or_table)); 1513 disp = tab_rec->offset; 1514 } 1515 if (entry->opcode == kX86PcRelLoadRA) { 1516 DCHECK_EQ(false, entry->skeleton.r8_form); 1517 EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table); 1518 code_buffer_.push_back(entry->skeleton.opcode); 1519 DCHECK_NE(0x0F, entry->skeleton.opcode); 1520 DCHECK_EQ(0, entry->skeleton.extra_opcode1); 1521 DCHECK_EQ(0, entry->skeleton.extra_opcode2); 1522 uint8_t low_reg = LowRegisterBits(raw_reg); 1523 uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP.GetRegNum(); 1524 code_buffer_.push_back(modrm); 1525 DCHECK_LT(scale, 4); 1526 uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table); 1527 uint8_t low_index = LowRegisterBits(raw_index); 1528 uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table; 1529 code_buffer_.push_back(sib); 1530 DCHECK_EQ(0, entry->skeleton.immediate_bytes); 1531 } else { 1532 uint8_t low_reg = LowRegisterBits(raw_reg); 1533 code_buffer_.push_back(entry->skeleton.opcode + low_reg); 1534 } 1535 code_buffer_.push_back(disp & 0xFF); 1536 code_buffer_.push_back((disp >> 8) & 0xFF); 1537 code_buffer_.push_back((disp >> 16) & 0xFF); 1538 code_buffer_.push_back((disp >> 24) & 0xFF); 1539 DCHECK_EQ(0, entry->skeleton.modrm_opcode); 1540 DCHECK_EQ(0, entry->skeleton.ax_opcode); 1541} 1542 1543void X86Mir2Lir::EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset) { 1544 DCHECK_EQ(entry->opcode, kX86StartOfMethod) << entry->name; 1545 DCHECK_EQ(false, entry->skeleton.r8_form); 1546 EmitPrefix(entry, raw_reg, NO_REG, NO_REG); 1547 code_buffer_.push_back(0xE8); // call +0 1548 code_buffer_.push_back(0); 1549 code_buffer_.push_back(0); 1550 code_buffer_.push_back(0); 1551 code_buffer_.push_back(0); 1552 1553 uint8_t low_reg = LowRegisterBits(raw_reg); 1554 code_buffer_.push_back(0x58 + low_reg); // pop reg 1555 1556 EmitRegImm(&X86Mir2Lir::EncodingMap[Gen64Bit() ? kX86Sub64RI : kX86Sub32RI], 1557 raw_reg, offset + 5 /* size of call +0 */); 1558} 1559 1560void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) { 1561 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " " 1562 << BuildInsnString(entry->fmt, lir, 0); 1563 for (size_t i = 0; i < GetInsnSize(lir); ++i) { 1564 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3 1565 } 1566} 1567 1568/* 1569 * Assemble the LIR into binary instruction format. Note that we may 1570 * discover that pc-relative displacements may not fit the selected 1571 * instruction. In those cases we will try to substitute a new code 1572 * sequence or request that the trace be shortened and retried. 1573 */ 1574AssemblerStatus X86Mir2Lir::AssembleInstructions(CodeOffset start_addr) { 1575 LIR *lir; 1576 AssemblerStatus res = kSuccess; // Assume success 1577 1578 const bool kVerbosePcFixup = false; 1579 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1580 if (IsPseudoLirOp(lir->opcode)) { 1581 continue; 1582 } 1583 1584 if (lir->flags.is_nop) { 1585 continue; 1586 } 1587 1588 if (lir->flags.fixup != kFixupNone) { 1589 switch (lir->opcode) { 1590 case kX86Jcc8: { 1591 LIR *target_lir = lir->target; 1592 DCHECK(target_lir != NULL); 1593 int delta = 0; 1594 CodeOffset pc; 1595 if (IS_SIMM8(lir->operands[0])) { 1596 pc = lir->offset + 2 /* opcode + rel8 */; 1597 } else { 1598 pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1599 } 1600 CodeOffset target = target_lir->offset; 1601 delta = target - pc; 1602 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1603 if (kVerbosePcFixup) { 1604 LOG(INFO) << "Retry for JCC growth at " << lir->offset 1605 << " delta: " << delta << " old delta: " << lir->operands[0]; 1606 } 1607 lir->opcode = kX86Jcc32; 1608 lir->flags.size = GetInsnSize(lir); 1609 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1610 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1611 res = kRetryAll; 1612 } 1613 if (kVerbosePcFixup) { 1614 LOG(INFO) << "Source:"; 1615 DumpLIRInsn(lir, 0); 1616 LOG(INFO) << "Target:"; 1617 DumpLIRInsn(target_lir, 0); 1618 LOG(INFO) << "Delta " << delta; 1619 } 1620 lir->operands[0] = delta; 1621 break; 1622 } 1623 case kX86Jcc32: { 1624 LIR *target_lir = lir->target; 1625 DCHECK(target_lir != NULL); 1626 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */; 1627 CodeOffset target = target_lir->offset; 1628 int delta = target - pc; 1629 if (kVerbosePcFixup) { 1630 LOG(INFO) << "Source:"; 1631 DumpLIRInsn(lir, 0); 1632 LOG(INFO) << "Target:"; 1633 DumpLIRInsn(target_lir, 0); 1634 LOG(INFO) << "Delta " << delta; 1635 } 1636 lir->operands[0] = delta; 1637 break; 1638 } 1639 case kX86Jecxz8: { 1640 LIR *target_lir = lir->target; 1641 DCHECK(target_lir != NULL); 1642 CodeOffset pc; 1643 pc = lir->offset + 2; // opcode + rel8 1644 CodeOffset target = target_lir->offset; 1645 int delta = target - pc; 1646 lir->operands[0] = delta; 1647 DCHECK(IS_SIMM8(delta)); 1648 break; 1649 } 1650 case kX86Jmp8: { 1651 LIR *target_lir = lir->target; 1652 DCHECK(target_lir != NULL); 1653 int delta = 0; 1654 CodeOffset pc; 1655 if (IS_SIMM8(lir->operands[0])) { 1656 pc = lir->offset + 2 /* opcode + rel8 */; 1657 } else { 1658 pc = lir->offset + 5 /* opcode + rel32 */; 1659 } 1660 CodeOffset target = target_lir->offset; 1661 delta = target - pc; 1662 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) { 1663 // Useless branch 1664 NopLIR(lir); 1665 if (kVerbosePcFixup) { 1666 LOG(INFO) << "Retry for useless branch at " << lir->offset; 1667 } 1668 res = kRetryAll; 1669 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) { 1670 if (kVerbosePcFixup) { 1671 LOG(INFO) << "Retry for JMP growth at " << lir->offset; 1672 } 1673 lir->opcode = kX86Jmp32; 1674 lir->flags.size = GetInsnSize(lir); 1675 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll)); 1676 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll)); 1677 res = kRetryAll; 1678 } 1679 lir->operands[0] = delta; 1680 break; 1681 } 1682 case kX86Jmp32: { 1683 LIR *target_lir = lir->target; 1684 DCHECK(target_lir != NULL); 1685 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */; 1686 CodeOffset target = target_lir->offset; 1687 int delta = target - pc; 1688 lir->operands[0] = delta; 1689 break; 1690 } 1691 default: 1692 if (lir->flags.fixup == kFixupLoad) { 1693 LIR *target_lir = lir->target; 1694 DCHECK(target_lir != NULL); 1695 CodeOffset target = target_lir->offset; 1696 lir->operands[2] = target; 1697 int newSize = GetInsnSize(lir); 1698 if (newSize != lir->flags.size) { 1699 lir->flags.size = newSize; 1700 res = kRetryAll; 1701 } 1702 } 1703 break; 1704 } 1705 } 1706 1707 /* 1708 * If one of the pc-relative instructions expanded we'll have 1709 * to make another pass. Don't bother to fully assemble the 1710 * instruction. 1711 */ 1712 if (res != kSuccess) { 1713 continue; 1714 } 1715 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size()); 1716 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode]; 1717 size_t starting_cbuf_size = code_buffer_.size(); 1718 switch (entry->kind) { 1719 case kData: // 4 bytes of data 1720 code_buffer_.push_back(lir->operands[0]); 1721 break; 1722 case kNullary: // 1 byte of opcode and possible prefixes. 1723 EmitNullary(entry); 1724 break; 1725 case kRegOpcode: // lir operands - 0: reg 1726 EmitOpRegOpcode(entry, lir->operands[0]); 1727 break; 1728 case kReg: // lir operands - 0: reg 1729 EmitOpReg(entry, lir->operands[0]); 1730 break; 1731 case kMem: // lir operands - 0: base, 1: disp 1732 EmitOpMem(entry, lir->operands[0], lir->operands[1]); 1733 break; 1734 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp 1735 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]); 1736 break; 1737 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg 1738 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1739 break; 1740 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate 1741 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1742 break; 1743 case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate 1744 EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1745 lir->operands[3], lir->operands[4]); 1746 break; 1747 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg 1748 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1749 lir->operands[3], lir->operands[4]); 1750 break; 1751 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp 1752 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1753 break; 1754 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp 1755 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1756 lir->operands[3], lir->operands[4]); 1757 break; 1758 case kRegThread: // lir operands - 0: reg, 1: disp 1759 EmitRegThread(entry, lir->operands[0], lir->operands[1]); 1760 break; 1761 case kRegReg: // lir operands - 0: reg1, 1: reg2 1762 EmitRegReg(entry, lir->operands[0], lir->operands[1]); 1763 break; 1764 case kRegRegStore: // lir operands - 0: reg2, 1: reg1 1765 EmitRegReg(entry, lir->operands[1], lir->operands[0]); 1766 break; 1767 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate 1768 EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1769 lir->operands[3]); 1770 break; 1771 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm 1772 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1773 break; 1774 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm 1775 EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]); 1776 break; 1777 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm 1778 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1779 lir->operands[3]); 1780 break; 1781 case kRegImm: // lir operands - 0: reg, 1: immediate 1782 EmitRegImm(entry, lir->operands[0], lir->operands[1]); 1783 break; 1784 case kThreadImm: // lir operands - 0: disp, 1: immediate 1785 EmitThreadImm(entry, lir->operands[0], lir->operands[1]); 1786 break; 1787 case kMovRegImm: // lir operands - 0: reg, 1: immediate 1788 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]); 1789 break; 1790 case kShiftRegImm: // lir operands - 0: reg, 1: immediate 1791 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]); 1792 break; 1793 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate 1794 EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1795 break; 1796 case kShiftRegCl: // lir operands - 0: reg, 1: cl 1797 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]); 1798 break; 1799 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl 1800 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1801 break; 1802 case kRegCond: // lir operands - 0: reg, 1: condition 1803 EmitRegCond(entry, lir->operands[0], lir->operands[1]); 1804 break; 1805 case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition 1806 EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1807 break; 1808 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition 1809 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]); 1810 break; 1811 case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition 1812 EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1813 lir->operands[3]); 1814 break; 1815 case kJmp: // lir operands - 0: rel 1816 if (entry->opcode == kX86JmpT) { 1817 // This works since the instruction format for jmp and call is basically the same and 1818 // EmitCallThread loads opcode info. 1819 EmitCallThread(entry, lir->operands[0]); 1820 } else { 1821 EmitJmp(entry, lir->operands[0]); 1822 } 1823 break; 1824 case kJcc: // lir operands - 0: rel, 1: CC, target assigned 1825 EmitJcc(entry, lir->operands[0], lir->operands[1]); 1826 break; 1827 case kCall: 1828 switch (entry->opcode) { 1829 case kX86CallI: // lir operands - 0: disp 1830 EmitCallImmediate(entry, lir->operands[0]); 1831 break; 1832 case kX86CallM: // lir operands - 0: base, 1: disp 1833 EmitCallMem(entry, lir->operands[0], lir->operands[1]); 1834 break; 1835 case kX86CallT: // lir operands - 0: disp 1836 EmitCallThread(entry, lir->operands[0]); 1837 break; 1838 default: 1839 EmitUnimplemented(entry, lir); 1840 break; 1841 } 1842 break; 1843 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table 1844 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2], 1845 lir->operands[3], lir->operands[4]); 1846 break; 1847 case kMacro: // lir operands - 0: reg 1848 EmitMacro(entry, lir->operands[0], lir->offset); 1849 break; 1850 case kNop: // TODO: these instruction kinds are missing implementations. 1851 case kThreadReg: 1852 case kRegArrayImm: 1853 case kShiftArrayImm: 1854 case kShiftArrayCl: 1855 case kArrayCond: 1856 case kUnimplemented: 1857 EmitUnimplemented(entry, lir); 1858 break; 1859 } 1860 DCHECK_EQ(lir->flags.size, GetInsnSize(lir)); 1861 CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size) 1862 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name; 1863 } 1864 return res; 1865} 1866 1867// LIR offset assignment. 1868// TODO: consolidate w/ Arm assembly mechanism. 1869int X86Mir2Lir::AssignInsnOffsets() { 1870 LIR* lir; 1871 int offset = 0; 1872 1873 for (lir = first_lir_insn_; lir != NULL; lir = NEXT_LIR(lir)) { 1874 lir->offset = offset; 1875 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { 1876 if (!lir->flags.is_nop) { 1877 offset += lir->flags.size; 1878 } 1879 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) { 1880 if (offset & 0x2) { 1881 offset += 2; 1882 lir->operands[0] = 1; 1883 } else { 1884 lir->operands[0] = 0; 1885 } 1886 } 1887 /* Pseudo opcodes don't consume space */ 1888 } 1889 return offset; 1890} 1891 1892/* 1893 * Walk the compilation unit and assign offsets to instructions 1894 * and literals and compute the total size of the compiled unit. 1895 * TODO: consolidate w/ Arm assembly mechanism. 1896 */ 1897void X86Mir2Lir::AssignOffsets() { 1898 int offset = AssignInsnOffsets(); 1899 1900 if (const_vectors_ != nullptr) { 1901 /* assign offsets to vector literals */ 1902 1903 // First, get offset to 12 mod 16 to align to 16 byte boundary. 1904 // This will ensure that the vector is 16 byte aligned, as the procedure is 1905 // always aligned at at 4 mod 16. 1906 int align_size = (16-4) - (offset & 0xF); 1907 if (align_size < 0) { 1908 align_size += 16; 1909 } 1910 1911 offset += align_size; 1912 1913 // Now assign each literal the right offset. 1914 for (LIR *p = const_vectors_; p != nullptr; p = p->next) { 1915 p->offset = offset; 1916 offset += 16; 1917 } 1918 } 1919 1920 /* Const values have to be word aligned */ 1921 offset = RoundUp(offset, 4); 1922 1923 /* Set up offsets for literals */ 1924 data_offset_ = offset; 1925 1926 offset = AssignLiteralOffset(offset); 1927 1928 offset = AssignSwitchTablesOffset(offset); 1929 1930 offset = AssignFillArrayDataOffset(offset); 1931 1932 total_size_ = offset; 1933} 1934 1935/* 1936 * Go over each instruction in the list and calculate the offset from the top 1937 * before sending them off to the assembler. If out-of-range branch distance is 1938 * seen rearrange the instructions a bit to correct it. 1939 * TODO: consolidate w/ Arm assembly mechanism. 1940 */ 1941void X86Mir2Lir::AssembleLIR() { 1942 cu_->NewTimingSplit("Assemble"); 1943 1944 // We will remove the method address if we never ended up using it 1945 if (store_method_addr_ && !store_method_addr_used_) { 1946 setup_method_address_[0]->flags.is_nop = true; 1947 setup_method_address_[1]->flags.is_nop = true; 1948 } 1949 1950 AssignOffsets(); 1951 int assembler_retries = 0; 1952 /* 1953 * Assemble here. Note that we generate code with optimistic assumptions 1954 * and if found now to work, we'll have to redo the sequence and retry. 1955 */ 1956 1957 while (true) { 1958 AssemblerStatus res = AssembleInstructions(0); 1959 if (res == kSuccess) { 1960 break; 1961 } else { 1962 assembler_retries++; 1963 if (assembler_retries > MAX_ASSEMBLER_RETRIES) { 1964 CodegenDump(); 1965 LOG(FATAL) << "Assembler error - too many retries"; 1966 } 1967 // Redo offsets and try again 1968 AssignOffsets(); 1969 code_buffer_.clear(); 1970 } 1971 } 1972 1973 // Install literals 1974 InstallLiteralPools(); 1975 1976 // Install switch tables 1977 InstallSwitchTables(); 1978 1979 // Install fill array data 1980 InstallFillArrayData(); 1981 1982 // Create the mapping table and native offset to reference map. 1983 cu_->NewTimingSplit("PcMappingTable"); 1984 CreateMappingTables(); 1985 1986 cu_->NewTimingSplit("GcMap"); 1987 CreateNativeGcMap(); 1988} 1989 1990} // namespace art 1991