codegen_x86.h revision 35e1e6ad4b50f1adbe9f93fe467766f042491896
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 40 protected: 41 Mir2Lir* ml_; 42 private: 43 int cur_core_reg_; 44 int cur_fp_reg_; 45 }; 46 47 class InToRegStorageMapping { 48 public: 49 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 50 initialized_(false) {} 51 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 52 int GetMaxMappedIn() { return max_mapped_in_; } 53 bool IsThereStackMapped() { return is_there_stack_mapped_; } 54 RegStorage Get(int in_position); 55 bool IsInitialized() { return initialized_; } 56 private: 57 std::map<int, RegStorage> mapping_; 58 int max_mapped_in_; 59 bool is_there_stack_mapped_; 60 bool initialized_; 61 }; 62 63 public: 64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 65 66 // Required for target - codegen helpers. 67 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 68 RegLocation rl_dest, int lit); 69 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 LIR* CheckSuspendUsingLoad() OVERRIDE; 71 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 73 OpSize size, VolatileKind is_volatile) OVERRIDE; 74 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 75 OpSize size) OVERRIDE; 76 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 77 RegStorage r_dest, OpSize size); 78 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 79 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 80 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 81 OpSize size, VolatileKind is_volatile) OVERRIDE; 82 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 83 OpSize size) OVERRIDE; 84 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 85 RegStorage r_src, OpSize size); 86 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 87 void GenImplicitNullCheck(RegStorage reg, int opt_flags); 88 89 // Required for target - register utilities. 90 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 91 RegStorage TargetReg32(SpecialTargetRegister reg); 92 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 93 if (wide_kind == kWide) { 94 if (cu_->target64) { 95 return As64BitReg(TargetReg32(symbolic_reg)); 96 } else { 97 // x86: construct a pair. 98 DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || 99 (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || 100 (kRet0 == symbolic_reg)); 101 return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), 102 TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); 103 } 104 } else if (wide_kind == kRef && cu_->target64) { 105 return As64BitReg(TargetReg32(symbolic_reg)); 106 } else { 107 return TargetReg32(symbolic_reg); 108 } 109 } 110 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 111 return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); 112 } 113 RegStorage GetArgMappingToPhysicalReg(int arg_num); 114 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 115 RegLocation GetReturnAlt(); 116 RegLocation GetReturnWideAlt(); 117 RegLocation LocCReturn(); 118 RegLocation LocCReturnRef(); 119 RegLocation LocCReturnDouble(); 120 RegLocation LocCReturnFloat(); 121 RegLocation LocCReturnWide(); 122 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 123 void AdjustSpillMask(); 124 void ClobberCallerSave(); 125 void FreeCallTemps(); 126 void LockCallTemps(); 127 void CompilerInitializeRegAlloc(); 128 int VectorRegisterSize(); 129 int NumReservableVectorRegisters(bool fp_used); 130 131 // Required for target - miscellaneous. 132 void AssembleLIR(); 133 int AssignInsnOffsets(); 134 void AssignOffsets(); 135 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 136 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 137 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 138 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 139 const char* GetTargetInstFmt(int opcode); 140 const char* GetTargetInstName(int opcode); 141 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 142 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 143 uint64_t GetTargetInstFlags(int opcode); 144 size_t GetInsnSize(LIR* lir) OVERRIDE; 145 bool IsUnconditionalBranch(LIR* lir); 146 147 // Get the register class for load/store of a field. 148 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 149 150 // Required for target - Dalvik-level generators. 151 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 152 RegLocation rl_src2); 153 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 154 RegLocation rl_dest, int scale); 155 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 156 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 157 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 158 RegLocation rl_src1, RegLocation rl_shift); 159 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 160 RegLocation rl_src2); 161 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 162 RegLocation rl_src2); 163 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 164 RegLocation rl_src2); 165 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 166 RegLocation rl_src2); 167 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 168 RegLocation rl_src2); 169 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 170 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 171 RegLocation rl_src2); 172 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 173 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 174 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 175 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double); 176 bool GenInlinedSqrt(CallInfo* info); 177 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 178 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 179 bool GenInlinedPeek(CallInfo* info, OpSize size); 180 bool GenInlinedPoke(CallInfo* info, OpSize size); 181 bool GenInlinedCharAt(CallInfo* info) OVERRIDE; 182 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 183 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 184 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 185 RegLocation rl_src2); 186 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 187 RegLocation rl_src2); 188 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 189 RegLocation rl_src2); 190 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 191 RegLocation rl_src2, bool is_div); 192 // TODO: collapse reg_lo, reg_hi 193 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 194 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 195 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 196 void GenDivZeroCheckWide(RegStorage reg); 197 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 198 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 199 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 200 void GenExitSequence(); 201 void GenSpecialExitSequence(); 202 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 203 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 204 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 205 void GenSelect(BasicBlock* bb, MIR* mir); 206 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 207 int32_t true_val, int32_t false_val, RegStorage rs_dest, 208 int dest_reg_class) OVERRIDE; 209 bool GenMemBarrier(MemBarrierKind barrier_kind); 210 void GenMoveException(RegLocation rl_dest); 211 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 212 int first_bit, int second_bit); 213 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 214 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 215 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 216 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 217 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 218 219 /* 220 * @brief Generate a two address long operation with a constant value 221 * @param rl_dest location of result 222 * @param rl_src constant source operand 223 * @param op Opcode to be generated 224 * @return success or not 225 */ 226 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 227 /* 228 * @brief Generate a three address long operation with a constant value 229 * @param rl_dest location of result 230 * @param rl_src1 source operand 231 * @param rl_src2 constant source operand 232 * @param op Opcode to be generated 233 * @return success or not 234 */ 235 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 236 Instruction::Code op); 237 238 /** 239 * @brief Generate a long arithmetic operation. 240 * @param rl_dest The destination. 241 * @param rl_src1 First operand. 242 * @param rl_src2 Second operand. 243 * @param op The DEX opcode for the operation. 244 * @param is_commutative The sources can be swapped if needed. 245 */ 246 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 247 Instruction::Code op, bool is_commutative); 248 249 /** 250 * @brief Generate a two operand long arithmetic operation. 251 * @param rl_dest The destination. 252 * @param rl_src Second operand. 253 * @param op The DEX opcode for the operation. 254 */ 255 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 256 257 /** 258 * @brief Generate a long operation. 259 * @param rl_dest The destination. Must be in a register 260 * @param rl_src The other operand. May be in a register or in memory. 261 * @param op The DEX opcode for the operation. 262 */ 263 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 264 265 /** 266 * @brief Implement instanceof a final class with x86 specific code. 267 * @param use_declaring_class 'true' if we can use the class itself. 268 * @param type_idx Type index to use if use_declaring_class is 'false'. 269 * @param rl_dest Result to be set to 0 or 1. 270 * @param rl_src Object to be tested. 271 */ 272 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 273 RegLocation rl_src); 274 275 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 276 RegLocation rl_src1, RegLocation rl_shift); 277 278 // Single operation generators. 279 LIR* OpUnconditionalBranch(LIR* target); 280 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 281 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 282 LIR* OpCondBranch(ConditionCode cc, LIR* target); 283 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 284 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 285 LIR* OpIT(ConditionCode cond, const char* guide); 286 void OpEndIT(LIR* it); 287 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 288 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 289 LIR* OpReg(OpKind op, RegStorage r_dest_src); 290 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 291 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 292 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 293 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 294 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 295 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 296 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 297 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 298 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 299 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 300 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 301 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 302 LIR* OpTestSuspend(LIR* target); 303 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); 304 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset); 305 LIR* OpVldm(RegStorage r_base, int count); 306 LIR* OpVstm(RegStorage r_base, int count); 307 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 308 void OpRegCopyWide(RegStorage dest, RegStorage src); 309 void OpTlsCmp(ThreadOffset<4> offset, int val); 310 void OpTlsCmp(ThreadOffset<8> offset, int val); 311 312 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 313 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 314 void SpillCoreRegs(); 315 void UnSpillCoreRegs(); 316 void UnSpillFPRegs(); 317 void SpillFPRegs(); 318 static const X86EncodingMap EncodingMap[kX86Last]; 319 bool InexpensiveConstantInt(int32_t value); 320 bool InexpensiveConstantFloat(int32_t value); 321 bool InexpensiveConstantLong(int64_t value); 322 bool InexpensiveConstantDouble(int64_t value); 323 324 /* 325 * @brief Should try to optimize for two address instructions? 326 * @return true if we try to avoid generating three operand instructions. 327 */ 328 virtual bool GenerateTwoOperandInstructions() const { return true; } 329 330 /* 331 * @brief x86 specific codegen for int operations. 332 * @param opcode Operation to perform. 333 * @param rl_dest Destination for the result. 334 * @param rl_lhs Left hand operand. 335 * @param rl_rhs Right hand operand. 336 */ 337 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 338 RegLocation rl_rhs); 339 340 /* 341 * @brief Dump a RegLocation using printf 342 * @param loc Register location to dump 343 */ 344 static void DumpRegLocation(RegLocation loc); 345 346 /* 347 * @brief Load the Method* of a dex method into the register. 348 * @param target_method The MethodReference of the method to be invoked. 349 * @param type How the method will be invoked. 350 * @param register that will contain the code address. 351 * @note register will be passed to TargetReg to get physical register. 352 */ 353 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 354 SpecialTargetRegister symbolic_reg); 355 356 /* 357 * @brief Load the Class* of a Dex Class type into the register. 358 * @param type How the method will be invoked. 359 * @param register that will contain the code address. 360 * @note register will be passed to TargetReg to get physical register. 361 */ 362 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 363 364 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 365 366 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 367 NextCallInsn next_call_insn, 368 const MethodReference& target_method, 369 uint32_t vtable_idx, 370 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 371 bool skip_this); 372 373 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 374 NextCallInsn next_call_insn, 375 const MethodReference& target_method, 376 uint32_t vtable_idx, 377 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 378 bool skip_this); 379 380 /* 381 * @brief Generate a relative call to the method that will be patched at link time. 382 * @param target_method The MethodReference of the method to be invoked. 383 * @param type How the method will be invoked. 384 * @returns Call instruction 385 */ 386 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 387 388 /* 389 * @brief Handle x86 specific literals 390 */ 391 void InstallLiteralPools(); 392 393 /* 394 * @brief Generate the debug_frame CFI information. 395 * @returns pointer to vector containing CFE information 396 */ 397 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(bool is_x86_64); 398 399 /* 400 * @brief Generate the debug_frame FDE information. 401 * @returns pointer to vector containing CFE information 402 */ 403 std::vector<uint8_t>* ReturnCallFrameInformation(); 404 405 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 406 407 protected: 408 // Casting of RegStorage 409 RegStorage As32BitReg(RegStorage reg) { 410 DCHECK(!reg.IsPair()); 411 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 412 if (kFailOnSizeError) { 413 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 414 } else { 415 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 416 return reg; 417 } 418 } 419 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 420 reg.GetRawBits() & RegStorage::kRegTypeMask); 421 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 422 ->GetReg().GetReg(), 423 ret_val.GetReg()); 424 return ret_val; 425 } 426 427 RegStorage As64BitReg(RegStorage reg) { 428 DCHECK(!reg.IsPair()); 429 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 430 if (kFailOnSizeError) { 431 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 432 } else { 433 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 434 return reg; 435 } 436 } 437 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 438 reg.GetRawBits() & RegStorage::kRegTypeMask); 439 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 440 ->GetReg().GetReg(), 441 ret_val.GetReg()); 442 return ret_val; 443 } 444 445 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 446 int32_t raw_base, int32_t displacement); 447 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 448 void EmitPrefix(const X86EncodingMap* entry, 449 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 450 void EmitOpcode(const X86EncodingMap* entry); 451 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 452 int32_t reg_r, int32_t reg_x, int32_t reg_b); 453 void EmitDisp(uint8_t base, int32_t disp); 454 void EmitModrmThread(uint8_t reg_or_opcode); 455 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 456 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 457 int32_t disp); 458 void EmitImm(const X86EncodingMap* entry, int64_t imm); 459 void EmitNullary(const X86EncodingMap* entry); 460 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 461 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 462 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 463 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 464 int32_t disp); 465 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 466 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 467 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 468 int32_t raw_index, int scale, int32_t disp); 469 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 470 int32_t disp, int32_t raw_reg); 471 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 472 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 473 int32_t raw_disp, int32_t imm); 474 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 475 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 476 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 477 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 478 int32_t imm); 479 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 480 int32_t imm); 481 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 482 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 483 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 484 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 485 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 486 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 487 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 488 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 489 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 490 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 491 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 492 int32_t cc); 493 494 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 495 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 496 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 497 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 498 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 499 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 500 int32_t raw_index, int scale, int32_t table_or_disp); 501 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 502 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 503 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 504 int64_t val, ConditionCode ccode); 505 void GenConstWide(RegLocation rl_dest, int64_t value); 506 void GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir); 507 void GenShiftByteVector(BasicBlock *bb, MIR *mir); 508 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 509 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 510 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); 511 512 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 513 514 /* 515 * @brief Ensure that a temporary register is byte addressable. 516 * @returns a temporary guarenteed to be byte addressable. 517 */ 518 virtual RegStorage AllocateByteRegister(); 519 520 /* 521 * @brief Use a wide temporary as a 128-bit register 522 * @returns a 128-bit temporary register. 523 */ 524 virtual RegStorage Get128BitRegister(RegStorage reg); 525 526 /* 527 * @brief Check if a register is byte addressable. 528 * @returns true if a register is byte addressable. 529 */ 530 bool IsByteRegister(RegStorage reg); 531 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; 532 533 /* 534 * @brief generate inline code for fast case of Strng.indexOf. 535 * @param info Call parameters 536 * @param zero_based 'true' if the index into the string is 0. 537 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 538 * generated. 539 */ 540 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 541 542 /** 543 * @brief Reserve a fixed number of vector registers from the register pool 544 * @details The mir->dalvikInsn.vA specifies an N such that vector registers 545 * [0..N-1] are removed from the temporary pool. The caller must call 546 * ReturnVectorRegisters before calling ReserveVectorRegisters again. 547 * Also sets the num_reserved_vector_regs_ to the specified value 548 * @param mir whose vA specifies the number of registers to reserve 549 */ 550 void ReserveVectorRegisters(MIR* mir); 551 552 /** 553 * @brief Return all the reserved vector registers to the temp pool 554 * @details Returns [0..num_reserved_vector_regs_] 555 */ 556 void ReturnVectorRegisters(); 557 558 /* 559 * @brief Load 128 bit constant into vector register. 560 * @param bb The basic block in which the MIR is from. 561 * @param mir The MIR whose opcode is kMirConstVector 562 * @note vA is the TypeSize for the register. 563 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 564 */ 565 void GenConst128(BasicBlock* bb, MIR* mir); 566 567 /* 568 * @brief MIR to move a vectorized register to another. 569 * @param bb The basic block in which the MIR is from. 570 * @param mir The MIR whose opcode is kMirConstVector. 571 * @note vA: TypeSize 572 * @note vB: destination 573 * @note vC: source 574 */ 575 void GenMoveVector(BasicBlock *bb, MIR *mir); 576 577 /* 578 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 579 * @param bb The basic block in which the MIR is from. 580 * @param mir The MIR whose opcode is kMirConstVector. 581 * @note vA: TypeSize 582 * @note vB: destination and source 583 * @note vC: source 584 */ 585 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 586 587 /* 588 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 589 * @param bb The basic block in which the MIR is from. 590 * @param mir The MIR whose opcode is kMirConstVector. 591 * @note vA: TypeSize 592 * @note vB: destination and source 593 * @note vC: source 594 */ 595 void GenAddVector(BasicBlock *bb, MIR *mir); 596 597 /* 598 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 599 * @param bb The basic block in which the MIR is from. 600 * @param mir The MIR whose opcode is kMirConstVector. 601 * @note vA: TypeSize 602 * @note vB: destination and source 603 * @note vC: source 604 */ 605 void GenSubtractVector(BasicBlock *bb, MIR *mir); 606 607 /* 608 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 609 * @param bb The basic block in which the MIR is from. 610 * @param mir The MIR whose opcode is kMirConstVector. 611 * @note vA: TypeSize 612 * @note vB: destination and source 613 * @note vC: immediate 614 */ 615 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 616 617 /* 618 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 619 * @param bb The basic block in which the MIR is from. 620 * @param mir The MIR whose opcode is kMirConstVector. 621 * @note vA: TypeSize 622 * @note vB: destination and source 623 * @note vC: immediate 624 */ 625 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 626 627 /* 628 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 629 * @param bb The basic block in which the MIR is from.. 630 * @param mir The MIR whose opcode is kMirConstVector. 631 * @note vA: TypeSize 632 * @note vB: destination and source 633 * @note vC: immediate 634 */ 635 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 636 637 /* 638 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 639 * @note vA: TypeSize 640 * @note vB: destination and source 641 * @note vC: source 642 */ 643 void GenAndVector(BasicBlock *bb, MIR *mir); 644 645 /* 646 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 647 * @param bb The basic block in which the MIR is from. 648 * @param mir The MIR whose opcode is kMirConstVector. 649 * @note vA: TypeSize 650 * @note vB: destination and source 651 * @note vC: source 652 */ 653 void GenOrVector(BasicBlock *bb, MIR *mir); 654 655 /* 656 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 657 * @param bb The basic block in which the MIR is from. 658 * @param mir The MIR whose opcode is kMirConstVector. 659 * @note vA: TypeSize 660 * @note vB: destination and source 661 * @note vC: source 662 */ 663 void GenXorVector(BasicBlock *bb, MIR *mir); 664 665 /* 666 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 667 * @param bb The basic block in which the MIR is from. 668 * @param mir The MIR whose opcode is kMirConstVector. 669 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 670 * @note vA: TypeSize 671 * @note vB: destination and source VR (not vector register) 672 * @note vC: source (vector register) 673 */ 674 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 675 676 /* 677 * @brief Extract a packed element into a single VR. 678 * @param bb The basic block in which the MIR is from. 679 * @param mir The MIR whose opcode is kMirConstVector. 680 * @note vA: TypeSize 681 * @note vB: destination VR (not vector register) 682 * @note vC: source (vector register) 683 * @note arg[0]: The index to use for extraction from vector register (which packed element). 684 */ 685 void GenReduceVector(BasicBlock *bb, MIR *mir); 686 687 /* 688 * @brief Create a vector value, with all TypeSize values equal to vC 689 * @param bb The basic block in which the MIR is from. 690 * @param mir The MIR whose opcode is kMirConstVector. 691 * @note vA: TypeSize. 692 * @note vB: destination vector register. 693 * @note vC: source VR (not vector register). 694 */ 695 void GenSetVector(BasicBlock *bb, MIR *mir); 696 697 /* 698 * @brief Generate code for a vector opcode. 699 * @param bb The basic block in which the MIR is from. 700 * @param mir The MIR whose opcode is a non-standard opcode. 701 */ 702 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 703 704 /* 705 * @brief Return the correct x86 opcode for the Dex operation 706 * @param op Dex opcode for the operation 707 * @param loc Register location of the operand 708 * @param is_high_op 'true' if this is an operation on the high word 709 * @param value Immediate value for the operation. Used for byte variants 710 * @returns the correct x86 opcode to perform the operation 711 */ 712 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 713 714 /* 715 * @brief Return the correct x86 opcode for the Dex operation 716 * @param op Dex opcode for the operation 717 * @param dest location of the destination. May be register or memory. 718 * @param rhs Location for the rhs of the operation. May be in register or memory. 719 * @param is_high_op 'true' if this is an operation on the high word 720 * @returns the correct x86 opcode to perform the operation 721 * @note at most one location may refer to memory 722 */ 723 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 724 bool is_high_op); 725 726 /* 727 * @brief Is this operation a no-op for this opcode and value 728 * @param op Dex opcode for the operation 729 * @param value Immediate value for the operation. 730 * @returns 'true' if the operation will have no effect 731 */ 732 bool IsNoOp(Instruction::Code op, int32_t value); 733 734 /** 735 * @brief Calculate magic number and shift for a given divisor 736 * @param divisor divisor number for calculation 737 * @param magic hold calculated magic number 738 * @param shift hold calculated shift 739 */ 740 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 741 742 /* 743 * @brief Generate an integer div or rem operation. 744 * @param rl_dest Destination Location. 745 * @param rl_src1 Numerator Location. 746 * @param rl_src2 Divisor Location. 747 * @param is_div 'true' if this is a division, 'false' for a remainder. 748 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 749 */ 750 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 751 bool is_div, bool check_zero); 752 753 /* 754 * @brief Generate an integer div or rem operation by a literal. 755 * @param rl_dest Destination Location. 756 * @param rl_src Numerator Location. 757 * @param lit Divisor. 758 * @param is_div 'true' if this is a division, 'false' for a remainder. 759 */ 760 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 761 762 /* 763 * Generate code to implement long shift operations. 764 * @param opcode The DEX opcode to specify the shift type. 765 * @param rl_dest The destination. 766 * @param rl_src The value to be shifted. 767 * @param shift_amount How much to shift. 768 * @returns the RegLocation of the result. 769 */ 770 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 771 RegLocation rl_src, int shift_amount); 772 /* 773 * Generate an imul of a register by a constant or a better sequence. 774 * @param dest Destination Register. 775 * @param src Source Register. 776 * @param val Constant multiplier. 777 */ 778 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 779 780 /* 781 * Generate an imul of a memory location by a constant or a better sequence. 782 * @param dest Destination Register. 783 * @param sreg Symbolic register. 784 * @param displacement Displacement on stack of Symbolic Register. 785 * @param val Constant multiplier. 786 */ 787 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 788 789 /* 790 * @brief Compare memory to immediate, and branch if condition true. 791 * @param cond The condition code that when true will branch to the target. 792 * @param temp_reg A temporary register that can be used if compare memory is not 793 * supported by the architecture. 794 * @param base_reg The register holding the base address. 795 * @param offset The offset from the base. 796 * @param check_value The immediate to compare to. 797 * @param target branch target (or nullptr) 798 * @param compare output for getting LIR for comparison (or nullptr) 799 */ 800 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 801 int offset, int check_value, LIR* target, LIR** compare); 802 803 /* 804 * Can this operation be using core registers without temporaries? 805 * @param rl_lhs Left hand operand. 806 * @param rl_rhs Right hand operand. 807 * @returns 'true' if the operation can proceed without needing temporary regs. 808 */ 809 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 810 811 /** 812 * @brief Generates inline code for conversion of long to FP by using x87/ 813 * @param rl_dest The destination of the FP. 814 * @param rl_src The source of the long. 815 * @param is_double 'true' if dealing with double, 'false' for float. 816 */ 817 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 818 819 /* 820 * @brief Perform MIR analysis before compiling method. 821 * @note Invokes Mir2LiR::Materialize after analysis. 822 */ 823 void Materialize(); 824 825 /* 826 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 827 * without regard to data type. In practice, this can result in UpdateLoc returning a 828 * location record for a Dalvik float value in a core register, and vis-versa. For targets 829 * which can inexpensively move data between core and float registers, this can often be a win. 830 * However, for x86 this is generally not a win. These variants of UpdateLoc() 831 * take a register class argument - and will return an in-register location record only if 832 * the value is live in a temp register of the correct class. Additionally, if the value is in 833 * a temp register of the wrong register class, it will be clobbered. 834 */ 835 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 836 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 837 838 /* 839 * @brief Analyze MIR before generating code, to prepare for the code generation. 840 */ 841 void AnalyzeMIR(); 842 843 /* 844 * @brief Analyze one basic block. 845 * @param bb Basic block to analyze. 846 */ 847 void AnalyzeBB(BasicBlock * bb); 848 849 /* 850 * @brief Analyze one extended MIR instruction 851 * @param opcode MIR instruction opcode. 852 * @param bb Basic block containing instruction. 853 * @param mir Extended instruction to analyze. 854 */ 855 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 856 857 /* 858 * @brief Analyze one MIR instruction 859 * @param opcode MIR instruction opcode. 860 * @param bb Basic block containing instruction. 861 * @param mir Instruction to analyze. 862 */ 863 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 864 865 /* 866 * @brief Analyze one MIR float/double instruction 867 * @param opcode MIR instruction opcode. 868 * @param bb Basic block containing instruction. 869 * @param mir Instruction to analyze. 870 */ 871 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 872 873 /* 874 * @brief Analyze one use of a double operand. 875 * @param rl_use Double RegLocation for the operand. 876 */ 877 void AnalyzeDoubleUse(RegLocation rl_use); 878 879 /* 880 * @brief Analyze one invoke-static MIR instruction 881 * @param opcode MIR instruction opcode. 882 * @param bb Basic block containing instruction. 883 * @param mir Instruction to analyze. 884 */ 885 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 886 887 // Information derived from analysis of MIR 888 889 // The compiler temporary for the code address of the method. 890 CompilerTemp *base_of_code_; 891 892 // Have we decided to compute a ptr to code and store in temporary VR? 893 bool store_method_addr_; 894 895 // Have we used the stored method address? 896 bool store_method_addr_used_; 897 898 // Instructions to remove if we didn't use the stored method address. 899 LIR* setup_method_address_[2]; 900 901 // Instructions needing patching with Method* values. 902 GrowableArray<LIR*> method_address_insns_; 903 904 // Instructions needing patching with Class Type* values. 905 GrowableArray<LIR*> class_type_address_insns_; 906 907 // Instructions needing patching with PC relative code addresses. 908 GrowableArray<LIR*> call_method_insns_; 909 910 // Prologue decrement of stack pointer. 911 LIR* stack_decrement_; 912 913 // Epilogue increment of stack pointer. 914 LIR* stack_increment_; 915 916 // The list of const vector literals. 917 LIR *const_vectors_; 918 919 /* 920 * @brief Search for a matching vector literal 921 * @param mir A kMirOpConst128b MIR instruction to match. 922 * @returns pointer to matching LIR constant, or nullptr if not found. 923 */ 924 LIR *ScanVectorLiteral(MIR *mir); 925 926 /* 927 * @brief Add a constant vector literal 928 * @param mir A kMirOpConst128b MIR instruction to match. 929 */ 930 LIR *AddVectorLiteral(MIR *mir); 931 932 InToRegStorageMapping in_to_reg_storage_mapping_; 933 934 bool WideGPRsAreAliases() OVERRIDE { 935 return cu_->target64; // On 64b, we have 64b GPRs. 936 } 937 bool WideFPRsAreAliases() OVERRIDE { 938 return true; // xmm registers have 64b views even on x86. 939 } 940 941 private: 942 // The number of vector registers [0..N] reserved by a call to ReserveVectorRegisters 943 int num_reserved_vector_regs_; 944}; 945 946} // namespace art 947 948#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 949