codegen_x86.h revision 3654a6f50a948ead89627f398aaf86a2c2db0088
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23namespace art { 24 25class X86Mir2Lir : public Mir2Lir { 26 public: 27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 LIR* CheckSuspendUsingLoad() OVERRIDE; 33 RegStorage LoadHelper(ThreadOffset offset); 34 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 35 int s_reg); 36 LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg); 37 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 38 OpSize size); 39 // TODO: collapse r_dest, r_dest_hi 40 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 41 RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg); 42 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 43 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 44 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 45 LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src); 46 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 47 OpSize size); 48 // TODO: collapse r_src, r_src_hi 49 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 50 RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg); 51 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 52 53 // Required for target - register utilities. 54 bool IsFpReg(int reg); 55 bool IsFpReg(RegStorage reg); 56 bool SameRegType(int reg1, int reg2); 57 RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 58 RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 59 int S2d(int low_reg, int high_reg); 60 RegStorage TargetReg(SpecialTargetRegister reg); 61 RegStorage GetArgMappingToPhysicalReg(int arg_num); 62 RegLocation GetReturnAlt(); 63 RegLocation GetReturnWideAlt(); 64 RegLocation LocCReturn(); 65 RegLocation LocCReturnDouble(); 66 RegLocation LocCReturnFloat(); 67 RegLocation LocCReturnWide(); 68 uint32_t FpRegMask(); 69 uint64_t GetRegMaskCommon(int reg); 70 void AdjustSpillMask(); 71 void ClobberCallerSave(); 72 void FlushReg(RegStorage reg); 73 void FlushRegWide(RegStorage reg); 74 void FreeCallTemps(); 75 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 76 void LockCallTemps(); 77 void MarkPreservedSingle(int v_reg, int reg); 78 void CompilerInitializeRegAlloc(); 79 80 // Required for target - miscellaneous. 81 void AssembleLIR(); 82 int AssignInsnOffsets(); 83 void AssignOffsets(); 84 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 85 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); 86 void SetupTargetResourceMasks(LIR* lir, uint64_t flags); 87 const char* GetTargetInstFmt(int opcode); 88 const char* GetTargetInstName(int opcode); 89 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 90 uint64_t GetPCUseDefEncoding(); 91 uint64_t GetTargetInstFlags(int opcode); 92 int GetInsnSize(LIR* lir); 93 bool IsUnconditionalBranch(LIR* lir); 94 95 // Required for target - Dalvik-level generators. 96 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 97 RegLocation rl_src2); 98 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 99 RegLocation rl_dest, int scale); 100 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 101 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 102 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 103 RegLocation rl_src1, RegLocation rl_shift); 104 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 105 RegLocation rl_src2); 106 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 107 RegLocation rl_src2); 108 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 109 RegLocation rl_src2); 110 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 111 RegLocation rl_src2); 112 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 113 RegLocation rl_src2); 114 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 115 RegLocation rl_src2); 116 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 117 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 118 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 119 bool GenInlinedSqrt(CallInfo* info); 120 bool GenInlinedPeek(CallInfo* info, OpSize size); 121 bool GenInlinedPoke(CallInfo* info, OpSize size); 122 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 123 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 124 RegLocation rl_src2); 125 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 126 RegLocation rl_src2); 127 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 128 RegLocation rl_src2); 129 LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset, 130 ThrowKind kind); 131 LIR* GenMemImmedCheck(ConditionCode c_code, RegStorage base, int offset, int check_value, 132 ThrowKind kind); 133 // TODO: collapse reg_lo, reg_hi 134 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 135 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 136 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 137 void GenDivZeroCheck(RegStorage reg); 138 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 139 void GenExitSequence(); 140 void GenSpecialExitSequence(); 141 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 142 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 143 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 144 void GenSelect(BasicBlock* bb, MIR* mir); 145 void GenMemBarrier(MemBarrierKind barrier_kind); 146 void GenMoveException(RegLocation rl_dest); 147 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 148 int first_bit, int second_bit); 149 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 150 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 151 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 152 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 153 154 /* 155 * @brief Generate a two address long operation with a constant value 156 * @param rl_dest location of result 157 * @param rl_src constant source operand 158 * @param op Opcode to be generated 159 */ 160 void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 161 /* 162 * @brief Generate a three address long operation with a constant value 163 * @param rl_dest location of result 164 * @param rl_src1 source operand 165 * @param rl_src2 constant source operand 166 * @param op Opcode to be generated 167 */ 168 void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 169 Instruction::Code op); 170 171 /** 172 * @brief Generate a long arithmetic operation. 173 * @param rl_dest The destination. 174 * @param rl_src1 First operand. 175 * @param rl_src2 Second operand. 176 * @param op The DEX opcode for the operation. 177 * @param is_commutative The sources can be swapped if needed. 178 */ 179 void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 180 Instruction::Code op, bool is_commutative); 181 182 /** 183 * @brief Generate a two operand long arithmetic operation. 184 * @param rl_dest The destination. 185 * @param rl_src Second operand. 186 * @param op The DEX opcode for the operation. 187 */ 188 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 189 190 /** 191 * @brief Generate a long operation. 192 * @param rl_dest The destination. Must be in a register 193 * @param rl_src The other operand. May be in a register or in memory. 194 * @param op The DEX opcode for the operation. 195 */ 196 void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 197 198 /** 199 * @brief Implement instanceof a final class with x86 specific code. 200 * @param use_declaring_class 'true' if we can use the class itself. 201 * @param type_idx Type index to use if use_declaring_class is 'false'. 202 * @param rl_dest Result to be set to 0 or 1. 203 * @param rl_src Object to be tested. 204 */ 205 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 206 RegLocation rl_src); 207 /* 208 * 209 * @brief Implement Set up instanceof a class with x86 specific code. 210 * @param needs_access_check 'true' if we must check the access. 211 * @param type_known_final 'true' if the type is known to be a final class. 212 * @param type_known_abstract 'true' if the type is known to be an abstract class. 213 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 214 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 215 * @param type_idx Type index to use if use_declaring_class is 'false'. 216 * @param rl_dest Result to be set to 0 or 1. 217 * @param rl_src Object to be tested. 218 */ 219 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 220 bool type_known_abstract, bool use_declaring_class, 221 bool can_assume_type_is_in_dex_cache, 222 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 223 224 // Single operation generators. 225 LIR* OpUnconditionalBranch(LIR* target); 226 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 227 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 228 LIR* OpCondBranch(ConditionCode cc, LIR* target); 229 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 230 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 231 LIR* OpIT(ConditionCode cond, const char* guide); 232 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 233 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 234 LIR* OpReg(OpKind op, RegStorage r_dest_src); 235 LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src); 236 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 237 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 238 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 239 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 240 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 241 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 242 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 243 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 244 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 245 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 246 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 247 LIR* OpTestSuspend(LIR* target); 248 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset); 249 LIR* OpVldm(RegStorage r_base, int count); 250 LIR* OpVstm(RegStorage r_base, int count); 251 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 252 void OpRegCopyWide(RegStorage dest, RegStorage src); 253 void OpTlsCmp(ThreadOffset offset, int val); 254 255 void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset); 256 void SpillCoreRegs(); 257 void UnSpillCoreRegs(); 258 static const X86EncodingMap EncodingMap[kX86Last]; 259 bool InexpensiveConstantInt(int32_t value); 260 bool InexpensiveConstantFloat(int32_t value); 261 bool InexpensiveConstantLong(int64_t value); 262 bool InexpensiveConstantDouble(int64_t value); 263 264 RegLocation UpdateLocWide(RegLocation loc); 265 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 266 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 267 RegStorage AllocTempDouble(); 268 void ResetDefLocWide(RegLocation rl); 269 270 /* 271 * @brief x86 specific codegen for int operations. 272 * @param opcode Operation to perform. 273 * @param rl_dest Destination for the result. 274 * @param rl_lhs Left hand operand. 275 * @param rl_rhs Right hand operand. 276 */ 277 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 278 RegLocation rl_rhs); 279 280 /* 281 * @brief Dump a RegLocation using printf 282 * @param loc Register location to dump 283 */ 284 static void DumpRegLocation(RegLocation loc); 285 286 /* 287 * @brief Load the Method* of a dex method into the register. 288 * @param target_method The MethodReference of the method to be invoked. 289 * @param type How the method will be invoked. 290 * @param register that will contain the code address. 291 * @note register will be passed to TargetReg to get physical register. 292 */ 293 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 294 SpecialTargetRegister symbolic_reg); 295 296 /* 297 * @brief Load the Class* of a Dex Class type into the register. 298 * @param type How the method will be invoked. 299 * @param register that will contain the code address. 300 * @note register will be passed to TargetReg to get physical register. 301 */ 302 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 303 304 /* 305 * @brief Generate a relative call to the method that will be patched at link time. 306 * @param target_method The MethodReference of the method to be invoked. 307 * @param type How the method will be invoked. 308 * @returns Call instruction 309 */ 310 LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 311 312 /* 313 * @brief Handle x86 specific literals 314 */ 315 void InstallLiteralPools(); 316 317 /* 318 * @brief Generate the debug_frame CFI information. 319 * @returns pointer to vector containing CFE information 320 */ 321 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 322 323 /* 324 * @brief Generate the debug_frame FDE information. 325 * @returns pointer to vector containing CFE information 326 */ 327 std::vector<uint8_t>* ReturnCallFrameInformation(); 328 329 private: 330 void EmitPrefix(const X86EncodingMap* entry); 331 void EmitOpcode(const X86EncodingMap* entry); 332 void EmitPrefixAndOpcode(const X86EncodingMap* entry); 333 void EmitDisp(uint8_t base, int disp); 334 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); 335 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); 336 void EmitImm(const X86EncodingMap* entry, int imm); 337 void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); 338 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); 339 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); 340 void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp); 341 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); 342 void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); 343 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); 344 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 345 int scale, int disp); 346 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 347 uint8_t reg); 348 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); 349 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); 350 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 351 void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 352 void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, 353 int32_t imm); 354 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 355 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); 356 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 357 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 358 void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); 359 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); 360 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); 361 362 /** 363 * @brief Used for encoding conditional register to register operation. 364 * @param entry The entry in the encoding map for the opcode. 365 * @param reg1 The first physical register. 366 * @param reg2 The second physical register. 367 * @param condition The condition code for operation. 368 */ 369 void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); 370 371 void EmitJmp(const X86EncodingMap* entry, int rel); 372 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); 373 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); 374 void EmitCallImmediate(const X86EncodingMap* entry, int disp); 375 void EmitCallThread(const X86EncodingMap* entry, int disp); 376 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, 377 int scale, int table_or_disp); 378 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); 379 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 380 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 381 int64_t val, ConditionCode ccode); 382 void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg); 383 void GenConstWide(RegLocation rl_dest, int64_t value); 384 385 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 386 387 /* 388 * @brief generate inline code for fast case of Strng.indexOf. 389 * @param info Call parameters 390 * @param zero_based 'true' if the index into the string is 0. 391 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 392 * generated. 393 */ 394 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 395 396 /* 397 * @brief Return the correct x86 opcode for the Dex operation 398 * @param op Dex opcode for the operation 399 * @param loc Register location of the operand 400 * @param is_high_op 'true' if this is an operation on the high word 401 * @param value Immediate value for the operation. Used for byte variants 402 * @returns the correct x86 opcode to perform the operation 403 */ 404 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 405 406 /* 407 * @brief Return the correct x86 opcode for the Dex operation 408 * @param op Dex opcode for the operation 409 * @param dest location of the destination. May be register or memory. 410 * @param rhs Location for the rhs of the operation. May be in register or memory. 411 * @param is_high_op 'true' if this is an operation on the high word 412 * @returns the correct x86 opcode to perform the operation 413 * @note at most one location may refer to memory 414 */ 415 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 416 bool is_high_op); 417 418 /* 419 * @brief Is this operation a no-op for this opcode and value 420 * @param op Dex opcode for the operation 421 * @param value Immediate value for the operation. 422 * @returns 'true' if the operation will have no effect 423 */ 424 bool IsNoOp(Instruction::Code op, int32_t value); 425 426 /** 427 * @brief Calculate magic number and shift for a given divisor 428 * @param divisor divisor number for calculation 429 * @param magic hold calculated magic number 430 * @param shift hold calculated shift 431 */ 432 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 433 434 /* 435 * @brief Generate an integer div or rem operation. 436 * @param rl_dest Destination Location. 437 * @param rl_src1 Numerator Location. 438 * @param rl_src2 Divisor Location. 439 * @param is_div 'true' if this is a division, 'false' for a remainder. 440 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 441 */ 442 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 443 bool is_div, bool check_zero); 444 445 /* 446 * @brief Generate an integer div or rem operation by a literal. 447 * @param rl_dest Destination Location. 448 * @param rl_src Numerator Location. 449 * @param lit Divisor. 450 * @param is_div 'true' if this is a division, 'false' for a remainder. 451 */ 452 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 453 454 /* 455 * Generate code to implement long shift operations. 456 * @param opcode The DEX opcode to specify the shift type. 457 * @param rl_dest The destination. 458 * @param rl_src The value to be shifted. 459 * @param shift_amount How much to shift. 460 * @returns the RegLocation of the result. 461 */ 462 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 463 RegLocation rl_src, int shift_amount); 464 /* 465 * Generate an imul of a register by a constant or a better sequence. 466 * @param dest Destination Register. 467 * @param src Source Register. 468 * @param val Constant multiplier. 469 */ 470 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 471 472 /* 473 * Generate an imul of a memory location by a constant or a better sequence. 474 * @param dest Destination Register. 475 * @param sreg Symbolic register. 476 * @param displacement Displacement on stack of Symbolic Register. 477 * @param val Constant multiplier. 478 */ 479 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 480 481 /* 482 * @brief Compare memory to immediate, and branch if condition true. 483 * @param cond The condition code that when true will branch to the target. 484 * @param temp_reg A temporary register that can be used if compare memory is not 485 * supported by the architecture. 486 * @param base_reg The register holding the base address. 487 * @param offset The offset from the base. 488 * @param check_value The immediate to compare to. 489 */ 490 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 491 int offset, int check_value, LIR* target); 492 493 /* 494 * Can this operation be using core registers without temporaries? 495 * @param rl_lhs Left hand operand. 496 * @param rl_rhs Right hand operand. 497 * @returns 'true' if the operation can proceed without needing temporary regs. 498 */ 499 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 500 501 /** 502 * @brief Generates inline code for conversion of long to FP by using x87/ 503 * @param rl_dest The destination of the FP. 504 * @param rl_src The source of the long. 505 * @param is_double 'true' if dealing with double, 'false' for float. 506 */ 507 void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 508 509 /* 510 * @brief Perform MIR analysis before compiling method. 511 * @note Invokes Mir2LiR::Materialize after analysis. 512 */ 513 void Materialize(); 514 515 /* 516 * @brief Analyze MIR before generating code, to prepare for the code generation. 517 */ 518 void AnalyzeMIR(); 519 520 /* 521 * @brief Analyze one basic block. 522 * @param bb Basic block to analyze. 523 */ 524 void AnalyzeBB(BasicBlock * bb); 525 526 /* 527 * @brief Analyze one extended MIR instruction 528 * @param opcode MIR instruction opcode. 529 * @param bb Basic block containing instruction. 530 * @param mir Extended instruction to analyze. 531 */ 532 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 533 534 /* 535 * @brief Analyze one MIR instruction 536 * @param opcode MIR instruction opcode. 537 * @param bb Basic block containing instruction. 538 * @param mir Instruction to analyze. 539 */ 540 void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 541 542 /* 543 * @brief Analyze one MIR float/double instruction 544 * @param opcode MIR instruction opcode. 545 * @param bb Basic block containing instruction. 546 * @param mir Instruction to analyze. 547 */ 548 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 549 550 /* 551 * @brief Analyze one use of a double operand. 552 * @param rl_use Double RegLocation for the operand. 553 */ 554 void AnalyzeDoubleUse(RegLocation rl_use); 555 556 // Information derived from analysis of MIR 557 558 // The compiler temporary for the code address of the method. 559 CompilerTemp *base_of_code_; 560 561 // Have we decided to compute a ptr to code and store in temporary VR? 562 bool store_method_addr_; 563 564 // Have we used the stored method address? 565 bool store_method_addr_used_; 566 567 // Instructions to remove if we didn't use the stored method address. 568 LIR* setup_method_address_[2]; 569 570 // Instructions needing patching with Method* values. 571 GrowableArray<LIR*> method_address_insns_; 572 573 // Instructions needing patching with Class Type* values. 574 GrowableArray<LIR*> class_type_address_insns_; 575 576 // Instructions needing patching with PC relative code addresses. 577 GrowableArray<LIR*> call_method_insns_; 578 579 // Prologue decrement of stack pointer. 580 LIR* stack_decrement_; 581 582 // Epilogue increment of stack pointer. 583 LIR* stack_increment_; 584}; 585 586} // namespace art 587 588#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 589