codegen_x86.h revision 3bc01748ef1c3e43361bdf520947a9d656658bf8
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23namespace art { 24 25class X86Mir2Lir : public Mir2Lir { 26 public: 27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 int LoadHelper(ThreadOffset offset); 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg); 34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 35 int s_reg); 36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size); 37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 38 int r_dest, int r_dest_hi, OpSize size, int s_reg); 39 LIR* LoadConstantNoClobber(int r_dest, int value); 40 LIR* LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value); 41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi); 43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 45 int r_src, int r_src_hi, OpSize size, int s_reg); 46 void MarkGCCard(int val_reg, int tgt_addr_reg); 47 48 // Required for target - register utilities. 49 bool IsFpReg(int reg); 50 bool SameRegType(int reg1, int reg2); 51 int AllocTypedTemp(bool fp_hint, int reg_class); 52 int AllocTypedTempPair(bool fp_hint, int reg_class); 53 int S2d(int low_reg, int high_reg); 54 int TargetReg(SpecialTargetRegister reg); 55 int GetArgMappingToPhysicalReg(int arg_num); 56 RegLocation GetReturnAlt(); 57 RegLocation GetReturnWideAlt(); 58 RegLocation LocCReturn(); 59 RegLocation LocCReturnDouble(); 60 RegLocation LocCReturnFloat(); 61 RegLocation LocCReturnWide(); 62 uint32_t FpRegMask(); 63 uint64_t GetRegMaskCommon(int reg); 64 void AdjustSpillMask(); 65 void ClobberCallerSave(); 66 void FlushReg(int reg); 67 void FlushRegWide(int reg1, int reg2); 68 void FreeCallTemps(); 69 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 70 void LockCallTemps(); 71 void MarkPreservedSingle(int v_reg, int reg); 72 void CompilerInitializeRegAlloc(); 73 74 // Required for target - miscellaneous. 75 void AssembleLIR(); 76 int AssignInsnOffsets(); 77 void AssignOffsets(); 78 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 79 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); 80 void SetupTargetResourceMasks(LIR* lir, uint64_t flags); 81 const char* GetTargetInstFmt(int opcode); 82 const char* GetTargetInstName(int opcode); 83 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 84 uint64_t GetPCUseDefEncoding(); 85 uint64_t GetTargetInstFlags(int opcode); 86 int GetInsnSize(LIR* lir); 87 bool IsUnconditionalBranch(LIR* lir); 88 89 // Required for target - Dalvik-level generators. 90 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 91 RegLocation rl_src1, RegLocation rl_src2); 92 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 93 RegLocation rl_index, RegLocation rl_dest, int scale); 94 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 95 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 96 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 97 RegLocation rl_src1, RegLocation rl_shift); 98 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 99 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 100 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 101 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, 102 RegLocation rl_src1, RegLocation rl_src2); 103 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, 104 RegLocation rl_src1, RegLocation rl_src2); 105 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 106 RegLocation rl_src2); 107 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 108 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 109 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 110 bool GenInlinedSqrt(CallInfo* info); 111 bool GenInlinedPeek(CallInfo* info, OpSize size); 112 bool GenInlinedPoke(CallInfo* info, OpSize size); 113 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 114 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 115 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 116 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 117 LIR* GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset, 118 ThrowKind kind); 119 LIR* GenMemImmedCheck(ConditionCode c_code, int base, int offset, int check_value, 120 ThrowKind kind); 121 RegLocation GenDivRem(RegLocation rl_dest, int reg_lo, int reg_hi, bool is_div); 122 RegLocation GenDivRemLit(RegLocation rl_dest, int reg_lo, int lit, bool is_div); 123 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 124 void GenDivZeroCheck(int reg_lo, int reg_hi); 125 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 126 void GenExitSequence(); 127 void GenSpecialExitSequence(); 128 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 129 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 130 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 131 void GenSelect(BasicBlock* bb, MIR* mir); 132 void GenMemBarrier(MemBarrierKind barrier_kind); 133 void GenMoveException(RegLocation rl_dest); 134 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, 135 int lit, int first_bit, int second_bit); 136 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 137 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 138 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 139 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 140 141 /* 142 * @brief Generate a two address long operation with a constant value 143 * @param rl_dest location of result 144 * @param rl_src constant source operand 145 * @param op Opcode to be generated 146 */ 147 void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 148 /* 149 * @brief Generate a three address long operation with a constant value 150 * @param rl_dest location of result 151 * @param rl_src1 source operand 152 * @param rl_src2 constant source operand 153 * @param op Opcode to be generated 154 */ 155 void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, 156 RegLocation rl_src2, Instruction::Code op); 157 158 /** 159 * @brief Generate a long arithmetic operation. 160 * @param rl_dest The destination. 161 * @param rl_src1 First operand. 162 * @param rl_src2 Second operand. 163 * @param op The DEX opcode for the operation. 164 * @param is_commutative The sources can be swapped if needed. 165 */ 166 void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, 167 RegLocation rl_src2, Instruction::Code op, bool is_commutative); 168 169 /** 170 * @brief Generate a two operand long arithmetic operation. 171 * @param rl_dest The destination. 172 * @param rl_src Second operand. 173 * @param op The DEX opcode for the operation. 174 */ 175 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 176 177 /** 178 * @brief Generate a long operation. 179 * @param rl_dest The destination. Must be in a register 180 * @param rl_src The other operand. May be in a register or in memory. 181 * @param op The DEX opcode for the operation. 182 */ 183 void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 184 185 /** 186 * @brief Implement instanceof a final class with x86 specific code. 187 * @param use_declaring_class 'true' if we can use the class itself. 188 * @param type_idx Type index to use if use_declaring_class is 'false'. 189 * @param rl_dest Result to be set to 0 or 1. 190 * @param rl_src Object to be tested. 191 */ 192 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 193 RegLocation rl_dest, RegLocation rl_src); 194 /* 195 * 196 * @brief Implement Set up instanceof a class with x86 specific code. 197 * @param needs_access_check 'true' if we must check the access. 198 * @param type_known_final 'true' if the type is known to be a final class. 199 * @param type_known_abstract 'true' if the type is known to be an abstract class. 200 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 201 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 202 * @param type_idx Type index to use if use_declaring_class is 'false'. 203 * @param rl_dest Result to be set to 0 or 1. 204 * @param rl_src Object to be tested. 205 */ 206 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 207 bool type_known_abstract, bool use_declaring_class, 208 bool can_assume_type_is_in_dex_cache, 209 uint32_t type_idx, RegLocation rl_dest, 210 RegLocation rl_src); 211 212 // Single operation generators. 213 LIR* OpUnconditionalBranch(LIR* target); 214 LIR* OpCmpBranch(ConditionCode cond, int src1, int src2, LIR* target); 215 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target); 216 LIR* OpCondBranch(ConditionCode cc, LIR* target); 217 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target); 218 LIR* OpFpRegCopy(int r_dest, int r_src); 219 LIR* OpIT(ConditionCode cond, const char* guide); 220 LIR* OpMem(OpKind op, int rBase, int disp); 221 LIR* OpPcRelLoad(int reg, LIR* target); 222 LIR* OpReg(OpKind op, int r_dest_src); 223 LIR* OpRegCopy(int r_dest, int r_src); 224 LIR* OpRegCopyNoInsert(int r_dest, int r_src); 225 LIR* OpRegImm(OpKind op, int r_dest_src1, int value); 226 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset); 227 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 228 LIR* OpRegMem(OpKind op, int r_dest, RegLocation value); 229 LIR* OpRegReg(OpKind op, int r_dest_src1, int r_src2); 230 LIR* OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type); 231 LIR* OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type); 232 LIR* OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src); 233 LIR* OpRegRegImm(OpKind op, int r_dest, int r_src1, int value); 234 LIR* OpRegRegReg(OpKind op, int r_dest, int r_src1, int r_src2); 235 LIR* OpTestSuspend(LIR* target); 236 LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset); 237 LIR* OpVldm(int rBase, int count); 238 LIR* OpVstm(int rBase, int count); 239 void OpLea(int rBase, int reg1, int reg2, int scale, int offset); 240 void OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, int src_hi); 241 void OpTlsCmp(ThreadOffset offset, int val); 242 243 void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset); 244 void SpillCoreRegs(); 245 void UnSpillCoreRegs(); 246 static const X86EncodingMap EncodingMap[kX86Last]; 247 bool InexpensiveConstantInt(int32_t value); 248 bool InexpensiveConstantFloat(int32_t value); 249 bool InexpensiveConstantLong(int64_t value); 250 bool InexpensiveConstantDouble(int64_t value); 251 252 RegLocation UpdateLocWide(RegLocation loc); 253 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 254 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 255 int AllocTempDouble(); 256 void ResetDefLocWide(RegLocation rl); 257 258 /* 259 * @brief x86 specific codegen for int operations. 260 * @param opcode Operation to perform. 261 * @param rl_dest Destination for the result. 262 * @param rl_lhs Left hand operand. 263 * @param rl_rhs Right hand operand. 264 */ 265 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 266 RegLocation rl_lhs, RegLocation rl_rhs); 267 268 /* 269 * @brief Dump a RegLocation using printf 270 * @param loc Register location to dump 271 */ 272 static void DumpRegLocation(RegLocation loc); 273 274 /* 275 * @brief Load the Method* of a dex method into the register. 276 * @param dex_method_index The index of the method to be invoked. 277 * @param type How the method will be invoked. 278 * @param register that will contain the code address. 279 * @note register will be passed to TargetReg to get physical register. 280 */ 281 void LoadMethodAddress(int dex_method_index, InvokeType type, 282 SpecialTargetRegister symbolic_reg); 283 284 /* 285 * @brief Load the Class* of a Dex Class type into the register. 286 * @param type How the method will be invoked. 287 * @param register that will contain the code address. 288 * @note register will be passed to TargetReg to get physical register. 289 */ 290 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 291 292 /* 293 * @brief Generate a relative call to the method that will be patched at link time. 294 * @param dex_method_index The index of the method to be invoked. 295 * @param type How the method will be invoked. 296 * @returns Call instruction 297 */ 298 LIR * CallWithLinkerFixup(int dex_method_index, InvokeType type); 299 300 /* 301 * @brief Handle x86 specific literals 302 */ 303 void InstallLiteralPools(); 304 305 private: 306 void EmitPrefix(const X86EncodingMap* entry); 307 void EmitOpcode(const X86EncodingMap* entry); 308 void EmitPrefixAndOpcode(const X86EncodingMap* entry); 309 void EmitDisp(uint8_t base, int disp); 310 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); 311 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); 312 void EmitImm(const X86EncodingMap* entry, int imm); 313 void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); 314 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); 315 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); 316 void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, 317 int scale, int disp); 318 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); 319 void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); 320 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); 321 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 322 int scale, int disp); 323 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 324 uint8_t reg); 325 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); 326 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); 327 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 328 void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 329 void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, int32_t imm); 330 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 331 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); 332 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 333 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 334 void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); 335 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); 336 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); 337 338 /** 339 * @brief Used for encoding conditional register to register operation. 340 * @param entry The entry in the encoding map for the opcode. 341 * @param reg1 The first physical register. 342 * @param reg2 The second physical register. 343 * @param condition The condition code for operation. 344 */ 345 void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); 346 347 void EmitJmp(const X86EncodingMap* entry, int rel); 348 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); 349 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); 350 void EmitCallImmediate(const X86EncodingMap* entry, int disp); 351 void EmitCallThread(const X86EncodingMap* entry, int disp); 352 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, 353 int scale, int table_or_disp); 354 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); 355 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 356 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 357 int64_t val, ConditionCode ccode); 358 void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg); 359 void GenConstWide(RegLocation rl_dest, int64_t value); 360 361 /* 362 * @brief Return the correct x86 opcode for the Dex operation 363 * @param op Dex opcode for the operation 364 * @param loc Register location of the operand 365 * @param is_high_op 'true' if this is an operation on the high word 366 * @param value Immediate value for the operation. Used for byte variants 367 * @returns the correct x86 opcode to perform the operation 368 */ 369 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 370 371 /* 372 * @brief Return the correct x86 opcode for the Dex operation 373 * @param op Dex opcode for the operation 374 * @param dest location of the destination. May be register or memory. 375 * @param rhs Location for the rhs of the operation. May be in register or memory. 376 * @param is_high_op 'true' if this is an operation on the high word 377 * @returns the correct x86 opcode to perform the operation 378 * @note at most one location may refer to memory 379 */ 380 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 381 bool is_high_op); 382 383 /* 384 * @brief Is this operation a no-op for this opcode and value 385 * @param op Dex opcode for the operation 386 * @param value Immediate value for the operation. 387 * @returns 'true' if the operation will have no effect 388 */ 389 bool IsNoOp(Instruction::Code op, int32_t value); 390 391 /** 392 * @brief Calculate magic number and shift for a given divisor 393 * @param divisor divisor number for calculation 394 * @param magic hold calculated magic number 395 * @param shift hold calculated shift 396 */ 397 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 398 399 /* 400 * @brief Generate an integer div or rem operation. 401 * @param rl_dest Destination Location. 402 * @param rl_src1 Numerator Location. 403 * @param rl_src2 Divisor Location. 404 * @param is_div 'true' if this is a division, 'false' for a remainder. 405 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 406 */ 407 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 408 RegLocation rl_src2, bool is_div, bool check_zero); 409 410 /* 411 * @brief Generate an integer div or rem operation by a literal. 412 * @param rl_dest Destination Location. 413 * @param rl_src Numerator Location. 414 * @param lit Divisor. 415 * @param is_div 'true' if this is a division, 'false' for a remainder. 416 */ 417 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 418 419 /* 420 * Generate code to implement long shift operations. 421 * @param opcode The DEX opcode to specify the shift type. 422 * @param rl_dest The destination. 423 * @param rl_src The value to be shifted. 424 * @param shift_amount How much to shift. 425 * @returns the RegLocation of the result. 426 */ 427 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 428 RegLocation rl_src, int shift_amount); 429 /* 430 * Generate an imul of a register by a constant or a better sequence. 431 * @param dest Destination Register. 432 * @param src Source Register. 433 * @param val Constant multiplier. 434 */ 435 void GenImulRegImm(int dest, int src, int val); 436 437 /* 438 * Generate an imul of a memory location by a constant or a better sequence. 439 * @param dest Destination Register. 440 * @param sreg Symbolic register. 441 * @param displacement Displacement on stack of Symbolic Register. 442 * @param val Constant multiplier. 443 */ 444 void GenImulMemImm(int dest, int sreg, int displacement, int val); 445 446 /* 447 * @brief Compare memory to immediate, and branch if condition true. 448 * @param cond The condition code that when true will branch to the target. 449 * @param temp_reg A temporary register that can be used if compare memory is not 450 * supported by the architecture. 451 * @param base_reg The register holding the base address. 452 * @param offset The offset from the base. 453 * @param check_value The immediate to compare to. 454 */ 455 LIR* OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, 456 int offset, int check_value, LIR* target); 457 458 /* 459 * Can this operation be using core registers without temporaries? 460 * @param rl_lhs Left hand operand. 461 * @param rl_rhs Right hand operand. 462 * @returns 'true' if the operation can proceed without needing temporary regs. 463 */ 464 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 465 466 /** 467 * @brief Generates inline code for conversion of long to FP by using x87/ 468 * @param rl_dest The destination of the FP. 469 * @param rl_src The source of the long. 470 * @param is_double 'true' if dealing with double, 'false' for float. 471 */ 472 void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 473 474 /* 475 * @brief Perform MIR analysis before compiling method. 476 * @note Invokes Mir2LiR::Materialize after analysis. 477 */ 478 void Materialize(); 479 480 /* 481 * @brief Analyze MIR before generating code, to prepare for the code generation. 482 */ 483 void AnalyzeMIR(); 484 485 /* 486 * @brief Analyze one basic block. 487 * @param bb Basic block to analyze. 488 */ 489 void AnalyzeBB(BasicBlock * bb); 490 491 /* 492 * @brief Analyze one extended MIR instruction 493 * @param opcode MIR instruction opcode. 494 * @param bb Basic block containing instruction. 495 * @param mir Extended instruction to analyze. 496 */ 497 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 498 499 /* 500 * @brief Analyze one MIR instruction 501 * @param opcode MIR instruction opcode. 502 * @param bb Basic block containing instruction. 503 * @param mir Instruction to analyze. 504 */ 505 void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 506 507 /* 508 * @brief Analyze one MIR float/double instruction 509 * @param opcode MIR instruction opcode. 510 * @param bb Basic block containing instruction. 511 * @param mir Instruction to analyze. 512 */ 513 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 514 515 /* 516 * @brief Analyze one use of a double operand. 517 * @param rl_use Double RegLocation for the operand. 518 */ 519 void AnalyzeDoubleUse(RegLocation rl_use); 520 521 // Information derived from analysis of MIR 522 523 // The compiler temporary for the code address of the method. 524 CompilerTemp *base_of_code_; 525 526 // Have we decided to compute a ptr to code and store in temporary VR? 527 bool store_method_addr_; 528 529 // Have we used the stored method address? 530 bool store_method_addr_used_; 531 532 // Instructions to remove if we didn't use the stored method address. 533 LIR* setup_method_address_[2]; 534 535 // Instructions needing patching with Method* values. 536 GrowableArray<LIR*> method_address_insns_; 537 538 // Instructions needing patching with Class Type* values. 539 GrowableArray<LIR*> class_type_address_insns_; 540 541 // Instructions needing patching with PC relative code addresses. 542 GrowableArray<LIR*> call_method_insns_; 543}; 544 545} // namespace art 546 547#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 548