codegen_x86.h revision 59a42afc2b23d2e241a7e301e2cd68a94fba51e5
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 40 protected: 41 Mir2Lir* ml_; 42 private: 43 int cur_core_reg_; 44 int cur_fp_reg_; 45 }; 46 47 class InToRegStorageMapping { 48 public: 49 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 50 initialized_(false) {} 51 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 52 int GetMaxMappedIn() { return max_mapped_in_; } 53 bool IsThereStackMapped() { return is_there_stack_mapped_; } 54 RegStorage Get(int in_position); 55 bool IsInitialized() { return initialized_; } 56 private: 57 std::map<int, RegStorage> mapping_; 58 int max_mapped_in_; 59 bool is_there_stack_mapped_; 60 bool initialized_; 61 }; 62 63 public: 64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 65 66 // Required for target - codegen helpers. 67 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 68 RegLocation rl_dest, int lit); 69 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 LIR* CheckSuspendUsingLoad() OVERRIDE; 71 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 72 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 73 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 74 OpSize size, VolatileKind is_volatile) OVERRIDE; 75 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 76 OpSize size) OVERRIDE; 77 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 78 RegStorage r_dest, OpSize size) OVERRIDE; 79 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 80 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 81 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 82 OpSize size, VolatileKind is_volatile) OVERRIDE; 83 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 84 OpSize size) OVERRIDE; 85 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 86 RegStorage r_src, OpSize size) OVERRIDE; 87 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 88 89 // Required for target - register utilities. 90 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 91 RegStorage TargetReg32(SpecialTargetRegister reg); 92 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, bool is_wide) OVERRIDE { 93 RegStorage reg = TargetReg32(symbolic_reg); 94 if (is_wide) { 95 return (reg.Is64Bit()) ? reg : As64BitReg(reg); 96 } else { 97 return (reg.Is32Bit()) ? reg : As32BitReg(reg); 98 } 99 } 100 RegStorage TargetRefReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 101 return TargetReg(symbolic_reg, cu_->target64); 102 } 103 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 104 return TargetReg(symbolic_reg, cu_->target64); 105 } 106 RegStorage GetArgMappingToPhysicalReg(int arg_num); 107 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 108 RegLocation GetReturnAlt(); 109 RegLocation GetReturnWideAlt(); 110 RegLocation LocCReturn(); 111 RegLocation LocCReturnRef(); 112 RegLocation LocCReturnDouble(); 113 RegLocation LocCReturnFloat(); 114 RegLocation LocCReturnWide(); 115 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 116 void AdjustSpillMask(); 117 void ClobberCallerSave(); 118 void FreeCallTemps(); 119 void LockCallTemps(); 120 void CompilerInitializeRegAlloc(); 121 int VectorRegisterSize(); 122 int NumReservableVectorRegisters(bool fp_used); 123 124 // Required for target - miscellaneous. 125 void AssembleLIR(); 126 int AssignInsnOffsets(); 127 void AssignOffsets(); 128 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 129 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 130 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 131 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 132 const char* GetTargetInstFmt(int opcode); 133 const char* GetTargetInstName(int opcode); 134 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 135 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 136 uint64_t GetTargetInstFlags(int opcode); 137 size_t GetInsnSize(LIR* lir) OVERRIDE; 138 bool IsUnconditionalBranch(LIR* lir); 139 140 // Check support for volatile load/store of a given size. 141 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 142 // Get the register class for load/store of a field. 143 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 144 145 // Required for target - Dalvik-level generators. 146 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 147 RegLocation rl_src2); 148 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 149 RegLocation rl_dest, int scale); 150 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 151 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 152 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 153 RegLocation rl_src1, RegLocation rl_shift); 154 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 155 RegLocation rl_src2); 156 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 157 RegLocation rl_src2); 158 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 159 RegLocation rl_src2); 160 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 161 RegLocation rl_src2); 162 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 163 RegLocation rl_src2); 164 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 165 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 166 RegLocation rl_src2); 167 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 168 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 169 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 170 bool GenInlinedSqrt(CallInfo* info); 171 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 172 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 173 bool GenInlinedPeek(CallInfo* info, OpSize size); 174 bool GenInlinedPoke(CallInfo* info, OpSize size); 175 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 176 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 177 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 178 RegLocation rl_src2); 179 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 180 RegLocation rl_src2); 181 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 182 RegLocation rl_src2); 183 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 184 RegLocation rl_src2, bool is_div); 185 // TODO: collapse reg_lo, reg_hi 186 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 187 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 188 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 189 void GenDivZeroCheckWide(RegStorage reg); 190 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 191 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 192 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 193 void GenExitSequence(); 194 void GenSpecialExitSequence(); 195 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 196 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 197 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 198 void GenSelect(BasicBlock* bb, MIR* mir); 199 bool GenMemBarrier(MemBarrierKind barrier_kind); 200 void GenMoveException(RegLocation rl_dest); 201 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 202 int first_bit, int second_bit); 203 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 204 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 205 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 206 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 207 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 208 209 /* 210 * @brief Generate a two address long operation with a constant value 211 * @param rl_dest location of result 212 * @param rl_src constant source operand 213 * @param op Opcode to be generated 214 * @return success or not 215 */ 216 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 217 /* 218 * @brief Generate a three address long operation with a constant value 219 * @param rl_dest location of result 220 * @param rl_src1 source operand 221 * @param rl_src2 constant source operand 222 * @param op Opcode to be generated 223 * @return success or not 224 */ 225 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 226 Instruction::Code op); 227 228 /** 229 * @brief Generate a long arithmetic operation. 230 * @param rl_dest The destination. 231 * @param rl_src1 First operand. 232 * @param rl_src2 Second operand. 233 * @param op The DEX opcode for the operation. 234 * @param is_commutative The sources can be swapped if needed. 235 */ 236 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 237 Instruction::Code op, bool is_commutative); 238 239 /** 240 * @brief Generate a two operand long arithmetic operation. 241 * @param rl_dest The destination. 242 * @param rl_src Second operand. 243 * @param op The DEX opcode for the operation. 244 */ 245 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 246 247 /** 248 * @brief Generate a long operation. 249 * @param rl_dest The destination. Must be in a register 250 * @param rl_src The other operand. May be in a register or in memory. 251 * @param op The DEX opcode for the operation. 252 */ 253 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 254 255 /** 256 * @brief Implement instanceof a final class with x86 specific code. 257 * @param use_declaring_class 'true' if we can use the class itself. 258 * @param type_idx Type index to use if use_declaring_class is 'false'. 259 * @param rl_dest Result to be set to 0 or 1. 260 * @param rl_src Object to be tested. 261 */ 262 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 263 RegLocation rl_src); 264 /* 265 * 266 * @brief Implement Set up instanceof a class with x86 specific code. 267 * @param needs_access_check 'true' if we must check the access. 268 * @param type_known_final 'true' if the type is known to be a final class. 269 * @param type_known_abstract 'true' if the type is known to be an abstract class. 270 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 271 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 272 * @param type_idx Type index to use if use_declaring_class is 'false'. 273 * @param rl_dest Result to be set to 0 or 1. 274 * @param rl_src Object to be tested. 275 */ 276 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 277 bool type_known_abstract, bool use_declaring_class, 278 bool can_assume_type_is_in_dex_cache, 279 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 280 281 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 282 RegLocation rl_src1, RegLocation rl_shift); 283 284 // Single operation generators. 285 LIR* OpUnconditionalBranch(LIR* target); 286 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 287 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 288 LIR* OpCondBranch(ConditionCode cc, LIR* target); 289 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 290 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 291 LIR* OpIT(ConditionCode cond, const char* guide); 292 void OpEndIT(LIR* it); 293 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 294 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 295 LIR* OpReg(OpKind op, RegStorage r_dest_src); 296 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 297 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 298 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 299 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 300 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 301 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 302 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 303 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 304 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 305 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 306 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 307 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 308 LIR* OpTestSuspend(LIR* target); 309 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 310 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 311 LIR* OpVldm(RegStorage r_base, int count); 312 LIR* OpVstm(RegStorage r_base, int count); 313 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 314 void OpRegCopyWide(RegStorage dest, RegStorage src); 315 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 316 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 317 318 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 319 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 320 void SpillCoreRegs(); 321 void UnSpillCoreRegs(); 322 void UnSpillFPRegs(); 323 void SpillFPRegs(); 324 static const X86EncodingMap EncodingMap[kX86Last]; 325 bool InexpensiveConstantInt(int32_t value); 326 bool InexpensiveConstantFloat(int32_t value); 327 bool InexpensiveConstantLong(int64_t value); 328 bool InexpensiveConstantDouble(int64_t value); 329 330 /* 331 * @brief Should try to optimize for two address instructions? 332 * @return true if we try to avoid generating three operand instructions. 333 */ 334 virtual bool GenerateTwoOperandInstructions() const { return true; } 335 336 /* 337 * @brief x86 specific codegen for int operations. 338 * @param opcode Operation to perform. 339 * @param rl_dest Destination for the result. 340 * @param rl_lhs Left hand operand. 341 * @param rl_rhs Right hand operand. 342 */ 343 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 344 RegLocation rl_rhs); 345 346 /* 347 * @brief Dump a RegLocation using printf 348 * @param loc Register location to dump 349 */ 350 static void DumpRegLocation(RegLocation loc); 351 352 /* 353 * @brief Load the Method* of a dex method into the register. 354 * @param target_method The MethodReference of the method to be invoked. 355 * @param type How the method will be invoked. 356 * @param register that will contain the code address. 357 * @note register will be passed to TargetReg to get physical register. 358 */ 359 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 360 SpecialTargetRegister symbolic_reg); 361 362 /* 363 * @brief Load the Class* of a Dex Class type into the register. 364 * @param type How the method will be invoked. 365 * @param register that will contain the code address. 366 * @note register will be passed to TargetReg to get physical register. 367 */ 368 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 369 370 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 371 372 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 373 NextCallInsn next_call_insn, 374 const MethodReference& target_method, 375 uint32_t vtable_idx, 376 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 377 bool skip_this); 378 379 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 380 NextCallInsn next_call_insn, 381 const MethodReference& target_method, 382 uint32_t vtable_idx, 383 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 384 bool skip_this); 385 386 /* 387 * @brief Generate a relative call to the method that will be patched at link time. 388 * @param target_method The MethodReference of the method to be invoked. 389 * @param type How the method will be invoked. 390 * @returns Call instruction 391 */ 392 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 393 394 /* 395 * @brief Handle x86 specific literals 396 */ 397 void InstallLiteralPools(); 398 399 /* 400 * @brief Generate the debug_frame CFI information. 401 * @returns pointer to vector containing CFE information 402 */ 403 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 404 405 /* 406 * @brief Generate the debug_frame FDE information. 407 * @returns pointer to vector containing CFE information 408 */ 409 std::vector<uint8_t>* ReturnCallFrameInformation(); 410 411 protected: 412 // Casting of RegStorage 413 RegStorage As32BitReg(RegStorage reg) { 414 DCHECK(!reg.IsPair()); 415 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 416 if (kFailOnSizeError) { 417 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 418 } else { 419 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 420 return reg; 421 } 422 } 423 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 424 reg.GetRawBits() & RegStorage::kRegTypeMask); 425 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 426 ->GetReg().GetReg(), 427 ret_val.GetReg()); 428 return ret_val; 429 } 430 431 RegStorage As64BitReg(RegStorage reg) { 432 DCHECK(!reg.IsPair()); 433 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 434 if (kFailOnSizeError) { 435 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 436 } else { 437 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 438 return reg; 439 } 440 } 441 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 442 reg.GetRawBits() & RegStorage::kRegTypeMask); 443 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 444 ->GetReg().GetReg(), 445 ret_val.GetReg()); 446 return ret_val; 447 } 448 449 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 450 int32_t raw_base, int32_t displacement); 451 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 452 void EmitPrefix(const X86EncodingMap* entry, 453 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 454 void EmitOpcode(const X86EncodingMap* entry); 455 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 456 int32_t reg_r, int32_t reg_x, int32_t reg_b); 457 void EmitDisp(uint8_t base, int32_t disp); 458 void EmitModrmThread(uint8_t reg_or_opcode); 459 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 460 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 461 int32_t disp); 462 void EmitImm(const X86EncodingMap* entry, int64_t imm); 463 void EmitNullary(const X86EncodingMap* entry); 464 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 465 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 466 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 467 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 468 int32_t disp); 469 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 470 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 471 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 472 int32_t raw_index, int scale, int32_t disp); 473 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 474 int32_t disp, int32_t raw_reg); 475 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 476 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 477 int32_t raw_disp, int32_t imm); 478 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 479 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 480 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 481 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 482 int32_t imm); 483 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 484 int32_t imm); 485 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 486 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 487 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 488 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 489 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 490 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 491 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 492 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 493 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 494 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 495 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 496 int32_t cc); 497 498 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 499 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 500 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 501 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 502 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 503 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 504 int32_t raw_index, int scale, int32_t table_or_disp); 505 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 506 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 507 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 508 int64_t val, ConditionCode ccode); 509 void GenConstWide(RegLocation rl_dest, int64_t value); 510 void GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir); 511 void GenShiftByteVector(BasicBlock *bb, MIR *mir); 512 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 513 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 514 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); 515 516 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 517 518 /* 519 * @brief Ensure that a temporary register is byte addressable. 520 * @returns a temporary guarenteed to be byte addressable. 521 */ 522 virtual RegStorage AllocateByteRegister(); 523 524 /* 525 * @brief Use a wide temporary as a 128-bit register 526 * @returns a 128-bit temporary register. 527 */ 528 virtual RegStorage Get128BitRegister(RegStorage reg); 529 530 /* 531 * @brief Check if a register is byte addressable. 532 * @returns true if a register is byte addressable. 533 */ 534 bool IsByteRegister(RegStorage reg); 535 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; 536 537 /* 538 * @brief generate inline code for fast case of Strng.indexOf. 539 * @param info Call parameters 540 * @param zero_based 'true' if the index into the string is 0. 541 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 542 * generated. 543 */ 544 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 545 546 /** 547 * @brief Reserve a fixed number of vector registers from the register pool 548 * @details The mir->dalvikInsn.vA specifies an N such that vector registers 549 * [0..N-1] are removed from the temporary pool. The caller must call 550 * ReturnVectorRegisters before calling ReserveVectorRegisters again. 551 * Also sets the num_reserved_vector_regs_ to the specified value 552 * @param mir whose vA specifies the number of registers to reserve 553 */ 554 void ReserveVectorRegisters(MIR* mir); 555 556 /** 557 * @brief Return all the reserved vector registers to the temp pool 558 * @details Returns [0..num_reserved_vector_regs_] 559 */ 560 void ReturnVectorRegisters(); 561 562 /* 563 * @brief Load 128 bit constant into vector register. 564 * @param bb The basic block in which the MIR is from. 565 * @param mir The MIR whose opcode is kMirConstVector 566 * @note vA is the TypeSize for the register. 567 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 568 */ 569 void GenConst128(BasicBlock* bb, MIR* mir); 570 571 /* 572 * @brief MIR to move a vectorized register to another. 573 * @param bb The basic block in which the MIR is from. 574 * @param mir The MIR whose opcode is kMirConstVector. 575 * @note vA: TypeSize 576 * @note vB: destination 577 * @note vC: source 578 */ 579 void GenMoveVector(BasicBlock *bb, MIR *mir); 580 581 /* 582 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 583 * @param bb The basic block in which the MIR is from. 584 * @param mir The MIR whose opcode is kMirConstVector. 585 * @note vA: TypeSize 586 * @note vB: destination and source 587 * @note vC: source 588 */ 589 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 590 591 /* 592 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 593 * @param bb The basic block in which the MIR is from. 594 * @param mir The MIR whose opcode is kMirConstVector. 595 * @note vA: TypeSize 596 * @note vB: destination and source 597 * @note vC: source 598 */ 599 void GenAddVector(BasicBlock *bb, MIR *mir); 600 601 /* 602 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 603 * @param bb The basic block in which the MIR is from. 604 * @param mir The MIR whose opcode is kMirConstVector. 605 * @note vA: TypeSize 606 * @note vB: destination and source 607 * @note vC: source 608 */ 609 void GenSubtractVector(BasicBlock *bb, MIR *mir); 610 611 /* 612 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 613 * @param bb The basic block in which the MIR is from. 614 * @param mir The MIR whose opcode is kMirConstVector. 615 * @note vA: TypeSize 616 * @note vB: destination and source 617 * @note vC: immediate 618 */ 619 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 620 621 /* 622 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 623 * @param bb The basic block in which the MIR is from. 624 * @param mir The MIR whose opcode is kMirConstVector. 625 * @note vA: TypeSize 626 * @note vB: destination and source 627 * @note vC: immediate 628 */ 629 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 630 631 /* 632 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 633 * @param bb The basic block in which the MIR is from.. 634 * @param mir The MIR whose opcode is kMirConstVector. 635 * @note vA: TypeSize 636 * @note vB: destination and source 637 * @note vC: immediate 638 */ 639 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 640 641 /* 642 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 643 * @note vA: TypeSize 644 * @note vB: destination and source 645 * @note vC: source 646 */ 647 void GenAndVector(BasicBlock *bb, MIR *mir); 648 649 /* 650 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 651 * @param bb The basic block in which the MIR is from. 652 * @param mir The MIR whose opcode is kMirConstVector. 653 * @note vA: TypeSize 654 * @note vB: destination and source 655 * @note vC: source 656 */ 657 void GenOrVector(BasicBlock *bb, MIR *mir); 658 659 /* 660 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 661 * @param bb The basic block in which the MIR is from. 662 * @param mir The MIR whose opcode is kMirConstVector. 663 * @note vA: TypeSize 664 * @note vB: destination and source 665 * @note vC: source 666 */ 667 void GenXorVector(BasicBlock *bb, MIR *mir); 668 669 /* 670 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 671 * @param bb The basic block in which the MIR is from. 672 * @param mir The MIR whose opcode is kMirConstVector. 673 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 674 * @note vA: TypeSize 675 * @note vB: destination and source VR (not vector register) 676 * @note vC: source (vector register) 677 */ 678 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 679 680 /* 681 * @brief Extract a packed element into a single VR. 682 * @param bb The basic block in which the MIR is from. 683 * @param mir The MIR whose opcode is kMirConstVector. 684 * @note vA: TypeSize 685 * @note vB: destination VR (not vector register) 686 * @note vC: source (vector register) 687 * @note arg[0]: The index to use for extraction from vector register (which packed element). 688 */ 689 void GenReduceVector(BasicBlock *bb, MIR *mir); 690 691 /* 692 * @brief Create a vector value, with all TypeSize values equal to vC 693 * @param bb The basic block in which the MIR is from. 694 * @param mir The MIR whose opcode is kMirConstVector. 695 * @note vA: TypeSize. 696 * @note vB: destination vector register. 697 * @note vC: source VR (not vector register). 698 */ 699 void GenSetVector(BasicBlock *bb, MIR *mir); 700 701 /* 702 * @brief Generate code for a vector opcode. 703 * @param bb The basic block in which the MIR is from. 704 * @param mir The MIR whose opcode is a non-standard opcode. 705 */ 706 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 707 708 /* 709 * @brief Return the correct x86 opcode for the Dex operation 710 * @param op Dex opcode for the operation 711 * @param loc Register location of the operand 712 * @param is_high_op 'true' if this is an operation on the high word 713 * @param value Immediate value for the operation. Used for byte variants 714 * @returns the correct x86 opcode to perform the operation 715 */ 716 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 717 718 /* 719 * @brief Return the correct x86 opcode for the Dex operation 720 * @param op Dex opcode for the operation 721 * @param dest location of the destination. May be register or memory. 722 * @param rhs Location for the rhs of the operation. May be in register or memory. 723 * @param is_high_op 'true' if this is an operation on the high word 724 * @returns the correct x86 opcode to perform the operation 725 * @note at most one location may refer to memory 726 */ 727 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 728 bool is_high_op); 729 730 /* 731 * @brief Is this operation a no-op for this opcode and value 732 * @param op Dex opcode for the operation 733 * @param value Immediate value for the operation. 734 * @returns 'true' if the operation will have no effect 735 */ 736 bool IsNoOp(Instruction::Code op, int32_t value); 737 738 /** 739 * @brief Calculate magic number and shift for a given divisor 740 * @param divisor divisor number for calculation 741 * @param magic hold calculated magic number 742 * @param shift hold calculated shift 743 */ 744 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 745 746 /* 747 * @brief Generate an integer div or rem operation. 748 * @param rl_dest Destination Location. 749 * @param rl_src1 Numerator Location. 750 * @param rl_src2 Divisor Location. 751 * @param is_div 'true' if this is a division, 'false' for a remainder. 752 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 753 */ 754 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 755 bool is_div, bool check_zero); 756 757 /* 758 * @brief Generate an integer div or rem operation by a literal. 759 * @param rl_dest Destination Location. 760 * @param rl_src Numerator Location. 761 * @param lit Divisor. 762 * @param is_div 'true' if this is a division, 'false' for a remainder. 763 */ 764 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 765 766 /* 767 * Generate code to implement long shift operations. 768 * @param opcode The DEX opcode to specify the shift type. 769 * @param rl_dest The destination. 770 * @param rl_src The value to be shifted. 771 * @param shift_amount How much to shift. 772 * @returns the RegLocation of the result. 773 */ 774 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 775 RegLocation rl_src, int shift_amount); 776 /* 777 * Generate an imul of a register by a constant or a better sequence. 778 * @param dest Destination Register. 779 * @param src Source Register. 780 * @param val Constant multiplier. 781 */ 782 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 783 784 /* 785 * Generate an imul of a memory location by a constant or a better sequence. 786 * @param dest Destination Register. 787 * @param sreg Symbolic register. 788 * @param displacement Displacement on stack of Symbolic Register. 789 * @param val Constant multiplier. 790 */ 791 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 792 793 /* 794 * @brief Compare memory to immediate, and branch if condition true. 795 * @param cond The condition code that when true will branch to the target. 796 * @param temp_reg A temporary register that can be used if compare memory is not 797 * supported by the architecture. 798 * @param base_reg The register holding the base address. 799 * @param offset The offset from the base. 800 * @param check_value The immediate to compare to. 801 */ 802 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 803 int offset, int check_value, LIR* target); 804 805 /* 806 * Can this operation be using core registers without temporaries? 807 * @param rl_lhs Left hand operand. 808 * @param rl_rhs Right hand operand. 809 * @returns 'true' if the operation can proceed without needing temporary regs. 810 */ 811 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 812 813 /** 814 * @brief Generates inline code for conversion of long to FP by using x87/ 815 * @param rl_dest The destination of the FP. 816 * @param rl_src The source of the long. 817 * @param is_double 'true' if dealing with double, 'false' for float. 818 */ 819 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 820 821 /* 822 * @brief Perform MIR analysis before compiling method. 823 * @note Invokes Mir2LiR::Materialize after analysis. 824 */ 825 void Materialize(); 826 827 /* 828 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 829 * without regard to data type. In practice, this can result in UpdateLoc returning a 830 * location record for a Dalvik float value in a core register, and vis-versa. For targets 831 * which can inexpensively move data between core and float registers, this can often be a win. 832 * However, for x86 this is generally not a win. These variants of UpdateLoc() 833 * take a register class argument - and will return an in-register location record only if 834 * the value is live in a temp register of the correct class. Additionally, if the value is in 835 * a temp register of the wrong register class, it will be clobbered. 836 */ 837 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 838 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 839 840 /* 841 * @brief Analyze MIR before generating code, to prepare for the code generation. 842 */ 843 void AnalyzeMIR(); 844 845 /* 846 * @brief Analyze one basic block. 847 * @param bb Basic block to analyze. 848 */ 849 void AnalyzeBB(BasicBlock * bb); 850 851 /* 852 * @brief Analyze one extended MIR instruction 853 * @param opcode MIR instruction opcode. 854 * @param bb Basic block containing instruction. 855 * @param mir Extended instruction to analyze. 856 */ 857 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 858 859 /* 860 * @brief Analyze one MIR instruction 861 * @param opcode MIR instruction opcode. 862 * @param bb Basic block containing instruction. 863 * @param mir Instruction to analyze. 864 */ 865 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 866 867 /* 868 * @brief Analyze one MIR float/double instruction 869 * @param opcode MIR instruction opcode. 870 * @param bb Basic block containing instruction. 871 * @param mir Instruction to analyze. 872 */ 873 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 874 875 /* 876 * @brief Analyze one use of a double operand. 877 * @param rl_use Double RegLocation for the operand. 878 */ 879 void AnalyzeDoubleUse(RegLocation rl_use); 880 881 /* 882 * @brief Analyze one invoke-static MIR instruction 883 * @param opcode MIR instruction opcode. 884 * @param bb Basic block containing instruction. 885 * @param mir Instruction to analyze. 886 */ 887 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 888 889 // Information derived from analysis of MIR 890 891 // The compiler temporary for the code address of the method. 892 CompilerTemp *base_of_code_; 893 894 // Have we decided to compute a ptr to code and store in temporary VR? 895 bool store_method_addr_; 896 897 // Have we used the stored method address? 898 bool store_method_addr_used_; 899 900 // Instructions to remove if we didn't use the stored method address. 901 LIR* setup_method_address_[2]; 902 903 // Instructions needing patching with Method* values. 904 GrowableArray<LIR*> method_address_insns_; 905 906 // Instructions needing patching with Class Type* values. 907 GrowableArray<LIR*> class_type_address_insns_; 908 909 // Instructions needing patching with PC relative code addresses. 910 GrowableArray<LIR*> call_method_insns_; 911 912 // Prologue decrement of stack pointer. 913 LIR* stack_decrement_; 914 915 // Epilogue increment of stack pointer. 916 LIR* stack_increment_; 917 918 // The list of const vector literals. 919 LIR *const_vectors_; 920 921 /* 922 * @brief Search for a matching vector literal 923 * @param mir A kMirOpConst128b MIR instruction to match. 924 * @returns pointer to matching LIR constant, or nullptr if not found. 925 */ 926 LIR *ScanVectorLiteral(MIR *mir); 927 928 /* 929 * @brief Add a constant vector literal 930 * @param mir A kMirOpConst128b MIR instruction to match. 931 */ 932 LIR *AddVectorLiteral(MIR *mir); 933 934 InToRegStorageMapping in_to_reg_storage_mapping_; 935 936 bool WideGPRsAreAliases() OVERRIDE { 937 return cu_->target64; // On 64b, we have 64b GPRs. 938 } 939 bool WideFPRsAreAliases() OVERRIDE { 940 return true; // xmm registers have 64b views even on x86. 941 } 942 943 private: 944 // The number of vector registers [0..N] reserved by a call to ReserveVectorRegisters 945 int num_reserved_vector_regs_; 946}; 947 948} // namespace art 949 950#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 951