codegen_x86.h revision 90969af6deb19b1dbe356d62fe68d8f5698d3d8f
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 40 protected: 41 Mir2Lir* ml_; 42 private: 43 int cur_core_reg_; 44 int cur_fp_reg_; 45 }; 46 47 class InToRegStorageMapping { 48 public: 49 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 50 initialized_(false) {} 51 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 52 int GetMaxMappedIn() { return max_mapped_in_; } 53 bool IsThereStackMapped() { return is_there_stack_mapped_; } 54 RegStorage Get(int in_position); 55 bool IsInitialized() { return initialized_; } 56 private: 57 std::map<int, RegStorage> mapping_; 58 int max_mapped_in_; 59 bool is_there_stack_mapped_; 60 bool initialized_; 61 }; 62 63 public: 64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 65 66 // Required for target - codegen helpers. 67 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 68 RegLocation rl_dest, int lit); 69 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 LIR* CheckSuspendUsingLoad() OVERRIDE; 71 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 72 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 73 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 74 OpSize size, VolatileKind is_volatile) OVERRIDE; 75 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 76 OpSize size) OVERRIDE; 77 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 78 RegStorage r_dest, OpSize size) OVERRIDE; 79 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 80 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 81 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 82 OpSize size, VolatileKind is_volatile) OVERRIDE; 83 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 84 OpSize size) OVERRIDE; 85 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 86 RegStorage r_src, OpSize size) OVERRIDE; 87 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 88 89 // Required for target - register utilities. 90 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 91 RegStorage TargetReg32(SpecialTargetRegister reg); 92 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 93 if (wide_kind == kWide) { 94 if (cu_->target64) { 95 return As64BitReg(TargetReg32(symbolic_reg)); 96 } else { 97 // x86: construct a pair. 98 DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || 99 (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || 100 (kRet0 == symbolic_reg)); 101 return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), 102 TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); 103 } 104 } else if (wide_kind == kRef && cu_->target64) { 105 return As64BitReg(TargetReg32(symbolic_reg)); 106 } else { 107 return TargetReg32(symbolic_reg); 108 } 109 } 110 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 111 return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); 112 } 113 RegStorage GetArgMappingToPhysicalReg(int arg_num); 114 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 115 RegLocation GetReturnAlt(); 116 RegLocation GetReturnWideAlt(); 117 RegLocation LocCReturn(); 118 RegLocation LocCReturnRef(); 119 RegLocation LocCReturnDouble(); 120 RegLocation LocCReturnFloat(); 121 RegLocation LocCReturnWide(); 122 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 123 void AdjustSpillMask(); 124 void ClobberCallerSave(); 125 void FreeCallTemps(); 126 void LockCallTemps(); 127 void CompilerInitializeRegAlloc(); 128 int VectorRegisterSize(); 129 int NumReservableVectorRegisters(bool fp_used); 130 131 // Required for target - miscellaneous. 132 void AssembleLIR(); 133 int AssignInsnOffsets(); 134 void AssignOffsets(); 135 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 136 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 137 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 138 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 139 const char* GetTargetInstFmt(int opcode); 140 const char* GetTargetInstName(int opcode); 141 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 142 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 143 uint64_t GetTargetInstFlags(int opcode); 144 size_t GetInsnSize(LIR* lir) OVERRIDE; 145 bool IsUnconditionalBranch(LIR* lir); 146 147 // Check support for volatile load/store of a given size. 148 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 149 // Get the register class for load/store of a field. 150 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 151 152 // Required for target - Dalvik-level generators. 153 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 154 RegLocation rl_src2); 155 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 156 RegLocation rl_dest, int scale); 157 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 158 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 159 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 160 RegLocation rl_src1, RegLocation rl_shift); 161 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 162 RegLocation rl_src2); 163 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 164 RegLocation rl_src2); 165 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 166 RegLocation rl_src2); 167 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 168 RegLocation rl_src2); 169 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 170 RegLocation rl_src2); 171 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 172 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 173 RegLocation rl_src2); 174 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 175 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 176 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); 177 bool GenInlinedSqrt(CallInfo* info); 178 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 179 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 180 bool GenInlinedPeek(CallInfo* info, OpSize size); 181 bool GenInlinedPoke(CallInfo* info, OpSize size); 182 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 183 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 184 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 185 RegLocation rl_src2); 186 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 187 RegLocation rl_src2); 188 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 189 RegLocation rl_src2); 190 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 191 RegLocation rl_src2, bool is_div); 192 // TODO: collapse reg_lo, reg_hi 193 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 194 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 195 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 196 void GenDivZeroCheckWide(RegStorage reg); 197 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 198 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 199 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 200 void GenExitSequence(); 201 void GenSpecialExitSequence(); 202 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 203 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 204 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 205 void GenSelect(BasicBlock* bb, MIR* mir); 206 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 207 int32_t true_val, int32_t false_val, RegStorage rs_dest, 208 int dest_reg_class) OVERRIDE; 209 // Optimized version for selection of 0 and 1. 210 void GenSelectConst01(RegStorage left_op, RegStorage right_op, ConditionCode code, bool true_val, 211 RegStorage rs_dest); 212 bool GenMemBarrier(MemBarrierKind barrier_kind); 213 void GenMoveException(RegLocation rl_dest); 214 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 215 int first_bit, int second_bit); 216 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 217 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 218 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 219 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 220 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 221 222 /* 223 * @brief Generate a two address long operation with a constant value 224 * @param rl_dest location of result 225 * @param rl_src constant source operand 226 * @param op Opcode to be generated 227 * @return success or not 228 */ 229 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 230 /* 231 * @brief Generate a three address long operation with a constant value 232 * @param rl_dest location of result 233 * @param rl_src1 source operand 234 * @param rl_src2 constant source operand 235 * @param op Opcode to be generated 236 * @return success or not 237 */ 238 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 239 Instruction::Code op); 240 241 /** 242 * @brief Generate a long arithmetic operation. 243 * @param rl_dest The destination. 244 * @param rl_src1 First operand. 245 * @param rl_src2 Second operand. 246 * @param op The DEX opcode for the operation. 247 * @param is_commutative The sources can be swapped if needed. 248 */ 249 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 250 Instruction::Code op, bool is_commutative); 251 252 /** 253 * @brief Generate a two operand long arithmetic operation. 254 * @param rl_dest The destination. 255 * @param rl_src Second operand. 256 * @param op The DEX opcode for the operation. 257 */ 258 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 259 260 /** 261 * @brief Generate a long operation. 262 * @param rl_dest The destination. Must be in a register 263 * @param rl_src The other operand. May be in a register or in memory. 264 * @param op The DEX opcode for the operation. 265 */ 266 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 267 268 /** 269 * @brief Implement instanceof a final class with x86 specific code. 270 * @param use_declaring_class 'true' if we can use the class itself. 271 * @param type_idx Type index to use if use_declaring_class is 'false'. 272 * @param rl_dest Result to be set to 0 or 1. 273 * @param rl_src Object to be tested. 274 */ 275 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 276 RegLocation rl_src); 277 /* 278 * 279 * @brief Implement Set up instanceof a class with x86 specific code. 280 * @param needs_access_check 'true' if we must check the access. 281 * @param type_known_final 'true' if the type is known to be a final class. 282 * @param type_known_abstract 'true' if the type is known to be an abstract class. 283 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 284 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 285 * @param type_idx Type index to use if use_declaring_class is 'false'. 286 * @param rl_dest Result to be set to 0 or 1. 287 * @param rl_src Object to be tested. 288 */ 289 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 290 bool type_known_abstract, bool use_declaring_class, 291 bool can_assume_type_is_in_dex_cache, 292 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 293 294 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 295 RegLocation rl_src1, RegLocation rl_shift); 296 297 // Single operation generators. 298 LIR* OpUnconditionalBranch(LIR* target); 299 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 300 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 301 LIR* OpCondBranch(ConditionCode cc, LIR* target); 302 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 303 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 304 LIR* OpIT(ConditionCode cond, const char* guide); 305 void OpEndIT(LIR* it); 306 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 307 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 308 LIR* OpReg(OpKind op, RegStorage r_dest_src); 309 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 310 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 311 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 312 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 313 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 314 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 315 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 316 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 317 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 318 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 319 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 320 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 321 LIR* OpTestSuspend(LIR* target); 322 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 323 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 324 LIR* OpVldm(RegStorage r_base, int count); 325 LIR* OpVstm(RegStorage r_base, int count); 326 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 327 void OpRegCopyWide(RegStorage dest, RegStorage src); 328 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 329 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 330 331 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 332 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 333 void SpillCoreRegs(); 334 void UnSpillCoreRegs(); 335 void UnSpillFPRegs(); 336 void SpillFPRegs(); 337 static const X86EncodingMap EncodingMap[kX86Last]; 338 bool InexpensiveConstantInt(int32_t value); 339 bool InexpensiveConstantFloat(int32_t value); 340 bool InexpensiveConstantLong(int64_t value); 341 bool InexpensiveConstantDouble(int64_t value); 342 343 /* 344 * @brief Should try to optimize for two address instructions? 345 * @return true if we try to avoid generating three operand instructions. 346 */ 347 virtual bool GenerateTwoOperandInstructions() const { return true; } 348 349 /* 350 * @brief x86 specific codegen for int operations. 351 * @param opcode Operation to perform. 352 * @param rl_dest Destination for the result. 353 * @param rl_lhs Left hand operand. 354 * @param rl_rhs Right hand operand. 355 */ 356 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 357 RegLocation rl_rhs); 358 359 /* 360 * @brief Dump a RegLocation using printf 361 * @param loc Register location to dump 362 */ 363 static void DumpRegLocation(RegLocation loc); 364 365 /* 366 * @brief Load the Method* of a dex method into the register. 367 * @param target_method The MethodReference of the method to be invoked. 368 * @param type How the method will be invoked. 369 * @param register that will contain the code address. 370 * @note register will be passed to TargetReg to get physical register. 371 */ 372 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 373 SpecialTargetRegister symbolic_reg); 374 375 /* 376 * @brief Load the Class* of a Dex Class type into the register. 377 * @param type How the method will be invoked. 378 * @param register that will contain the code address. 379 * @note register will be passed to TargetReg to get physical register. 380 */ 381 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 382 383 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 384 385 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 386 NextCallInsn next_call_insn, 387 const MethodReference& target_method, 388 uint32_t vtable_idx, 389 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 390 bool skip_this); 391 392 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 393 NextCallInsn next_call_insn, 394 const MethodReference& target_method, 395 uint32_t vtable_idx, 396 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 397 bool skip_this); 398 399 /* 400 * @brief Generate a relative call to the method that will be patched at link time. 401 * @param target_method The MethodReference of the method to be invoked. 402 * @param type How the method will be invoked. 403 * @returns Call instruction 404 */ 405 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 406 407 /* 408 * @brief Handle x86 specific literals 409 */ 410 void InstallLiteralPools(); 411 412 /* 413 * @brief Generate the debug_frame CFI information. 414 * @returns pointer to vector containing CFE information 415 */ 416 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 417 418 /* 419 * @brief Generate the debug_frame FDE information. 420 * @returns pointer to vector containing CFE information 421 */ 422 std::vector<uint8_t>* ReturnCallFrameInformation(); 423 424 protected: 425 // Casting of RegStorage 426 RegStorage As32BitReg(RegStorage reg) { 427 DCHECK(!reg.IsPair()); 428 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 429 if (kFailOnSizeError) { 430 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 431 } else { 432 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 433 return reg; 434 } 435 } 436 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 437 reg.GetRawBits() & RegStorage::kRegTypeMask); 438 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 439 ->GetReg().GetReg(), 440 ret_val.GetReg()); 441 return ret_val; 442 } 443 444 RegStorage As64BitReg(RegStorage reg) { 445 DCHECK(!reg.IsPair()); 446 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 447 if (kFailOnSizeError) { 448 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 449 } else { 450 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 451 return reg; 452 } 453 } 454 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 455 reg.GetRawBits() & RegStorage::kRegTypeMask); 456 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 457 ->GetReg().GetReg(), 458 ret_val.GetReg()); 459 return ret_val; 460 } 461 462 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 463 int32_t raw_base, int32_t displacement); 464 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 465 void EmitPrefix(const X86EncodingMap* entry, 466 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 467 void EmitOpcode(const X86EncodingMap* entry); 468 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 469 int32_t reg_r, int32_t reg_x, int32_t reg_b); 470 void EmitDisp(uint8_t base, int32_t disp); 471 void EmitModrmThread(uint8_t reg_or_opcode); 472 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 473 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 474 int32_t disp); 475 void EmitImm(const X86EncodingMap* entry, int64_t imm); 476 void EmitNullary(const X86EncodingMap* entry); 477 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 478 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 479 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 480 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 481 int32_t disp); 482 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 483 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 484 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 485 int32_t raw_index, int scale, int32_t disp); 486 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 487 int32_t disp, int32_t raw_reg); 488 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 489 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 490 int32_t raw_disp, int32_t imm); 491 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 492 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 493 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 494 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 495 int32_t imm); 496 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 497 int32_t imm); 498 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 499 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 500 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 501 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 502 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 503 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 504 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 505 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 506 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 507 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 508 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 509 int32_t cc); 510 511 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 512 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 513 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 514 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 515 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 516 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 517 int32_t raw_index, int scale, int32_t table_or_disp); 518 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 519 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 520 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 521 int64_t val, ConditionCode ccode); 522 void GenConstWide(RegLocation rl_dest, int64_t value); 523 void GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir); 524 void GenShiftByteVector(BasicBlock *bb, MIR *mir); 525 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 526 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); 527 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); 528 529 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 530 531 /* 532 * @brief Ensure that a temporary register is byte addressable. 533 * @returns a temporary guarenteed to be byte addressable. 534 */ 535 virtual RegStorage AllocateByteRegister(); 536 537 /* 538 * @brief Use a wide temporary as a 128-bit register 539 * @returns a 128-bit temporary register. 540 */ 541 virtual RegStorage Get128BitRegister(RegStorage reg); 542 543 /* 544 * @brief Check if a register is byte addressable. 545 * @returns true if a register is byte addressable. 546 */ 547 bool IsByteRegister(RegStorage reg); 548 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; 549 550 /* 551 * @brief generate inline code for fast case of Strng.indexOf. 552 * @param info Call parameters 553 * @param zero_based 'true' if the index into the string is 0. 554 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 555 * generated. 556 */ 557 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 558 559 /** 560 * @brief Reserve a fixed number of vector registers from the register pool 561 * @details The mir->dalvikInsn.vA specifies an N such that vector registers 562 * [0..N-1] are removed from the temporary pool. The caller must call 563 * ReturnVectorRegisters before calling ReserveVectorRegisters again. 564 * Also sets the num_reserved_vector_regs_ to the specified value 565 * @param mir whose vA specifies the number of registers to reserve 566 */ 567 void ReserveVectorRegisters(MIR* mir); 568 569 /** 570 * @brief Return all the reserved vector registers to the temp pool 571 * @details Returns [0..num_reserved_vector_regs_] 572 */ 573 void ReturnVectorRegisters(); 574 575 /* 576 * @brief Load 128 bit constant into vector register. 577 * @param bb The basic block in which the MIR is from. 578 * @param mir The MIR whose opcode is kMirConstVector 579 * @note vA is the TypeSize for the register. 580 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 581 */ 582 void GenConst128(BasicBlock* bb, MIR* mir); 583 584 /* 585 * @brief MIR to move a vectorized register to another. 586 * @param bb The basic block in which the MIR is from. 587 * @param mir The MIR whose opcode is kMirConstVector. 588 * @note vA: TypeSize 589 * @note vB: destination 590 * @note vC: source 591 */ 592 void GenMoveVector(BasicBlock *bb, MIR *mir); 593 594 /* 595 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 596 * @param bb The basic block in which the MIR is from. 597 * @param mir The MIR whose opcode is kMirConstVector. 598 * @note vA: TypeSize 599 * @note vB: destination and source 600 * @note vC: source 601 */ 602 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 603 604 /* 605 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 606 * @param bb The basic block in which the MIR is from. 607 * @param mir The MIR whose opcode is kMirConstVector. 608 * @note vA: TypeSize 609 * @note vB: destination and source 610 * @note vC: source 611 */ 612 void GenAddVector(BasicBlock *bb, MIR *mir); 613 614 /* 615 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 616 * @param bb The basic block in which the MIR is from. 617 * @param mir The MIR whose opcode is kMirConstVector. 618 * @note vA: TypeSize 619 * @note vB: destination and source 620 * @note vC: source 621 */ 622 void GenSubtractVector(BasicBlock *bb, MIR *mir); 623 624 /* 625 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 626 * @param bb The basic block in which the MIR is from. 627 * @param mir The MIR whose opcode is kMirConstVector. 628 * @note vA: TypeSize 629 * @note vB: destination and source 630 * @note vC: immediate 631 */ 632 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 633 634 /* 635 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 636 * @param bb The basic block in which the MIR is from. 637 * @param mir The MIR whose opcode is kMirConstVector. 638 * @note vA: TypeSize 639 * @note vB: destination and source 640 * @note vC: immediate 641 */ 642 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 643 644 /* 645 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 646 * @param bb The basic block in which the MIR is from.. 647 * @param mir The MIR whose opcode is kMirConstVector. 648 * @note vA: TypeSize 649 * @note vB: destination and source 650 * @note vC: immediate 651 */ 652 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 653 654 /* 655 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 656 * @note vA: TypeSize 657 * @note vB: destination and source 658 * @note vC: source 659 */ 660 void GenAndVector(BasicBlock *bb, MIR *mir); 661 662 /* 663 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 664 * @param bb The basic block in which the MIR is from. 665 * @param mir The MIR whose opcode is kMirConstVector. 666 * @note vA: TypeSize 667 * @note vB: destination and source 668 * @note vC: source 669 */ 670 void GenOrVector(BasicBlock *bb, MIR *mir); 671 672 /* 673 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 674 * @param bb The basic block in which the MIR is from. 675 * @param mir The MIR whose opcode is kMirConstVector. 676 * @note vA: TypeSize 677 * @note vB: destination and source 678 * @note vC: source 679 */ 680 void GenXorVector(BasicBlock *bb, MIR *mir); 681 682 /* 683 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 684 * @param bb The basic block in which the MIR is from. 685 * @param mir The MIR whose opcode is kMirConstVector. 686 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 687 * @note vA: TypeSize 688 * @note vB: destination and source VR (not vector register) 689 * @note vC: source (vector register) 690 */ 691 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 692 693 /* 694 * @brief Extract a packed element into a single VR. 695 * @param bb The basic block in which the MIR is from. 696 * @param mir The MIR whose opcode is kMirConstVector. 697 * @note vA: TypeSize 698 * @note vB: destination VR (not vector register) 699 * @note vC: source (vector register) 700 * @note arg[0]: The index to use for extraction from vector register (which packed element). 701 */ 702 void GenReduceVector(BasicBlock *bb, MIR *mir); 703 704 /* 705 * @brief Create a vector value, with all TypeSize values equal to vC 706 * @param bb The basic block in which the MIR is from. 707 * @param mir The MIR whose opcode is kMirConstVector. 708 * @note vA: TypeSize. 709 * @note vB: destination vector register. 710 * @note vC: source VR (not vector register). 711 */ 712 void GenSetVector(BasicBlock *bb, MIR *mir); 713 714 /* 715 * @brief Generate code for a vector opcode. 716 * @param bb The basic block in which the MIR is from. 717 * @param mir The MIR whose opcode is a non-standard opcode. 718 */ 719 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 720 721 /* 722 * @brief Return the correct x86 opcode for the Dex operation 723 * @param op Dex opcode for the operation 724 * @param loc Register location of the operand 725 * @param is_high_op 'true' if this is an operation on the high word 726 * @param value Immediate value for the operation. Used for byte variants 727 * @returns the correct x86 opcode to perform the operation 728 */ 729 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 730 731 /* 732 * @brief Return the correct x86 opcode for the Dex operation 733 * @param op Dex opcode for the operation 734 * @param dest location of the destination. May be register or memory. 735 * @param rhs Location for the rhs of the operation. May be in register or memory. 736 * @param is_high_op 'true' if this is an operation on the high word 737 * @returns the correct x86 opcode to perform the operation 738 * @note at most one location may refer to memory 739 */ 740 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 741 bool is_high_op); 742 743 /* 744 * @brief Is this operation a no-op for this opcode and value 745 * @param op Dex opcode for the operation 746 * @param value Immediate value for the operation. 747 * @returns 'true' if the operation will have no effect 748 */ 749 bool IsNoOp(Instruction::Code op, int32_t value); 750 751 /** 752 * @brief Calculate magic number and shift for a given divisor 753 * @param divisor divisor number for calculation 754 * @param magic hold calculated magic number 755 * @param shift hold calculated shift 756 */ 757 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 758 759 /* 760 * @brief Generate an integer div or rem operation. 761 * @param rl_dest Destination Location. 762 * @param rl_src1 Numerator Location. 763 * @param rl_src2 Divisor Location. 764 * @param is_div 'true' if this is a division, 'false' for a remainder. 765 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 766 */ 767 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 768 bool is_div, bool check_zero); 769 770 /* 771 * @brief Generate an integer div or rem operation by a literal. 772 * @param rl_dest Destination Location. 773 * @param rl_src Numerator Location. 774 * @param lit Divisor. 775 * @param is_div 'true' if this is a division, 'false' for a remainder. 776 */ 777 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 778 779 /* 780 * Generate code to implement long shift operations. 781 * @param opcode The DEX opcode to specify the shift type. 782 * @param rl_dest The destination. 783 * @param rl_src The value to be shifted. 784 * @param shift_amount How much to shift. 785 * @returns the RegLocation of the result. 786 */ 787 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 788 RegLocation rl_src, int shift_amount); 789 /* 790 * Generate an imul of a register by a constant or a better sequence. 791 * @param dest Destination Register. 792 * @param src Source Register. 793 * @param val Constant multiplier. 794 */ 795 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 796 797 /* 798 * Generate an imul of a memory location by a constant or a better sequence. 799 * @param dest Destination Register. 800 * @param sreg Symbolic register. 801 * @param displacement Displacement on stack of Symbolic Register. 802 * @param val Constant multiplier. 803 */ 804 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 805 806 /* 807 * @brief Compare memory to immediate, and branch if condition true. 808 * @param cond The condition code that when true will branch to the target. 809 * @param temp_reg A temporary register that can be used if compare memory is not 810 * supported by the architecture. 811 * @param base_reg The register holding the base address. 812 * @param offset The offset from the base. 813 * @param check_value The immediate to compare to. 814 */ 815 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 816 int offset, int check_value, LIR* target); 817 818 /* 819 * Can this operation be using core registers without temporaries? 820 * @param rl_lhs Left hand operand. 821 * @param rl_rhs Right hand operand. 822 * @returns 'true' if the operation can proceed without needing temporary regs. 823 */ 824 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 825 826 /** 827 * @brief Generates inline code for conversion of long to FP by using x87/ 828 * @param rl_dest The destination of the FP. 829 * @param rl_src The source of the long. 830 * @param is_double 'true' if dealing with double, 'false' for float. 831 */ 832 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 833 834 /* 835 * @brief Perform MIR analysis before compiling method. 836 * @note Invokes Mir2LiR::Materialize after analysis. 837 */ 838 void Materialize(); 839 840 /* 841 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 842 * without regard to data type. In practice, this can result in UpdateLoc returning a 843 * location record for a Dalvik float value in a core register, and vis-versa. For targets 844 * which can inexpensively move data between core and float registers, this can often be a win. 845 * However, for x86 this is generally not a win. These variants of UpdateLoc() 846 * take a register class argument - and will return an in-register location record only if 847 * the value is live in a temp register of the correct class. Additionally, if the value is in 848 * a temp register of the wrong register class, it will be clobbered. 849 */ 850 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 851 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 852 853 /* 854 * @brief Analyze MIR before generating code, to prepare for the code generation. 855 */ 856 void AnalyzeMIR(); 857 858 /* 859 * @brief Analyze one basic block. 860 * @param bb Basic block to analyze. 861 */ 862 void AnalyzeBB(BasicBlock * bb); 863 864 /* 865 * @brief Analyze one extended MIR instruction 866 * @param opcode MIR instruction opcode. 867 * @param bb Basic block containing instruction. 868 * @param mir Extended instruction to analyze. 869 */ 870 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 871 872 /* 873 * @brief Analyze one MIR instruction 874 * @param opcode MIR instruction opcode. 875 * @param bb Basic block containing instruction. 876 * @param mir Instruction to analyze. 877 */ 878 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 879 880 /* 881 * @brief Analyze one MIR float/double instruction 882 * @param opcode MIR instruction opcode. 883 * @param bb Basic block containing instruction. 884 * @param mir Instruction to analyze. 885 */ 886 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 887 888 /* 889 * @brief Analyze one use of a double operand. 890 * @param rl_use Double RegLocation for the operand. 891 */ 892 void AnalyzeDoubleUse(RegLocation rl_use); 893 894 /* 895 * @brief Analyze one invoke-static MIR instruction 896 * @param opcode MIR instruction opcode. 897 * @param bb Basic block containing instruction. 898 * @param mir Instruction to analyze. 899 */ 900 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 901 902 // Information derived from analysis of MIR 903 904 // The compiler temporary for the code address of the method. 905 CompilerTemp *base_of_code_; 906 907 // Have we decided to compute a ptr to code and store in temporary VR? 908 bool store_method_addr_; 909 910 // Have we used the stored method address? 911 bool store_method_addr_used_; 912 913 // Instructions to remove if we didn't use the stored method address. 914 LIR* setup_method_address_[2]; 915 916 // Instructions needing patching with Method* values. 917 GrowableArray<LIR*> method_address_insns_; 918 919 // Instructions needing patching with Class Type* values. 920 GrowableArray<LIR*> class_type_address_insns_; 921 922 // Instructions needing patching with PC relative code addresses. 923 GrowableArray<LIR*> call_method_insns_; 924 925 // Prologue decrement of stack pointer. 926 LIR* stack_decrement_; 927 928 // Epilogue increment of stack pointer. 929 LIR* stack_increment_; 930 931 // The list of const vector literals. 932 LIR *const_vectors_; 933 934 /* 935 * @brief Search for a matching vector literal 936 * @param mir A kMirOpConst128b MIR instruction to match. 937 * @returns pointer to matching LIR constant, or nullptr if not found. 938 */ 939 LIR *ScanVectorLiteral(MIR *mir); 940 941 /* 942 * @brief Add a constant vector literal 943 * @param mir A kMirOpConst128b MIR instruction to match. 944 */ 945 LIR *AddVectorLiteral(MIR *mir); 946 947 InToRegStorageMapping in_to_reg_storage_mapping_; 948 949 bool WideGPRsAreAliases() OVERRIDE { 950 return cu_->target64; // On 64b, we have 64b GPRs. 951 } 952 bool WideFPRsAreAliases() OVERRIDE { 953 return true; // xmm registers have 64b views even on x86. 954 } 955 956 private: 957 // The number of vector registers [0..N] reserved by a call to ReserveVectorRegisters 958 int num_reserved_vector_regs_; 959}; 960 961} // namespace art 962 963#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 964