codegen_x86.h revision d6ed642458c8820e1beca72f3d7b5f0be4a4b64b
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23namespace art { 24 25class X86Mir2Lir FINAL : public Mir2Lir { 26 public: 27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 33 LIR* CheckSuspendUsingLoad() OVERRIDE; 34 RegStorage LoadHelper(ThreadOffset<4> offset); 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 36 int s_reg); 37 LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg); 38 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 39 OpSize size); 40 // TODO: collapse r_dest, r_dest_hi 41 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 42 RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg); 43 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 44 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 45 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 46 LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src); 47 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 48 OpSize size); 49 // TODO: collapse r_src, r_src_hi 50 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 51 RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg); 52 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 53 54 // Required for target - register utilities. 55 bool IsFpReg(int reg); 56 bool IsFpReg(RegStorage reg); 57 bool SameRegType(int reg1, int reg2); 58 RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 59 RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 60 int S2d(int low_reg, int high_reg); 61 RegStorage TargetReg(SpecialTargetRegister reg); 62 RegStorage GetArgMappingToPhysicalReg(int arg_num); 63 RegLocation GetReturnAlt(); 64 RegLocation GetReturnWideAlt(); 65 RegLocation LocCReturn(); 66 RegLocation LocCReturnDouble(); 67 RegLocation LocCReturnFloat(); 68 RegLocation LocCReturnWide(); 69 uint32_t FpRegMask(); 70 uint64_t GetRegMaskCommon(int reg); 71 void AdjustSpillMask(); 72 void ClobberCallerSave(); 73 void FlushReg(RegStorage reg); 74 void FlushRegWide(RegStorage reg); 75 void FreeCallTemps(); 76 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 77 void LockCallTemps(); 78 void MarkPreservedSingle(int v_reg, int reg); 79 void CompilerInitializeRegAlloc(); 80 81 // Required for target - miscellaneous. 82 void AssembleLIR(); 83 int AssignInsnOffsets(); 84 void AssignOffsets(); 85 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 86 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); 87 void SetupTargetResourceMasks(LIR* lir, uint64_t flags); 88 const char* GetTargetInstFmt(int opcode); 89 const char* GetTargetInstName(int opcode); 90 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 91 uint64_t GetPCUseDefEncoding(); 92 uint64_t GetTargetInstFlags(int opcode); 93 int GetInsnSize(LIR* lir); 94 bool IsUnconditionalBranch(LIR* lir); 95 96 // Required for target - Dalvik-level generators. 97 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 98 RegLocation rl_src2); 99 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 100 RegLocation rl_dest, int scale); 101 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 102 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 103 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 104 RegLocation rl_src1, RegLocation rl_shift); 105 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 106 RegLocation rl_src2); 107 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 108 RegLocation rl_src2); 109 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 110 RegLocation rl_src2); 111 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 112 RegLocation rl_src2); 113 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 114 RegLocation rl_src2); 115 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 116 RegLocation rl_src2); 117 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 118 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 119 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 120 bool GenInlinedSqrt(CallInfo* info); 121 bool GenInlinedPeek(CallInfo* info, OpSize size); 122 bool GenInlinedPoke(CallInfo* info, OpSize size); 123 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 124 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 125 RegLocation rl_src2); 126 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 127 RegLocation rl_src2); 128 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 129 RegLocation rl_src2); 130 LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset, 131 ThrowKind kind); 132 LIR* GenMemImmedCheck(ConditionCode c_code, RegStorage base, int offset, int check_value, 133 ThrowKind kind); 134 // TODO: collapse reg_lo, reg_hi 135 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 136 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 137 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 138 void GenDivZeroCheck(RegStorage reg); 139 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 140 void GenExitSequence(); 141 void GenSpecialExitSequence(); 142 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 143 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 144 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 145 void GenSelect(BasicBlock* bb, MIR* mir); 146 void GenMemBarrier(MemBarrierKind barrier_kind); 147 void GenMoveException(RegLocation rl_dest); 148 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 149 int first_bit, int second_bit); 150 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 151 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 152 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 153 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 154 155 /* 156 * @brief Generate a two address long operation with a constant value 157 * @param rl_dest location of result 158 * @param rl_src constant source operand 159 * @param op Opcode to be generated 160 */ 161 void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 162 /* 163 * @brief Generate a three address long operation with a constant value 164 * @param rl_dest location of result 165 * @param rl_src1 source operand 166 * @param rl_src2 constant source operand 167 * @param op Opcode to be generated 168 */ 169 void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 170 Instruction::Code op); 171 172 /** 173 * @brief Generate a long arithmetic operation. 174 * @param rl_dest The destination. 175 * @param rl_src1 First operand. 176 * @param rl_src2 Second operand. 177 * @param op The DEX opcode for the operation. 178 * @param is_commutative The sources can be swapped if needed. 179 */ 180 void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 181 Instruction::Code op, bool is_commutative); 182 183 /** 184 * @brief Generate a two operand long arithmetic operation. 185 * @param rl_dest The destination. 186 * @param rl_src Second operand. 187 * @param op The DEX opcode for the operation. 188 */ 189 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 190 191 /** 192 * @brief Generate a long operation. 193 * @param rl_dest The destination. Must be in a register 194 * @param rl_src The other operand. May be in a register or in memory. 195 * @param op The DEX opcode for the operation. 196 */ 197 void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 198 199 /** 200 * @brief Implement instanceof a final class with x86 specific code. 201 * @param use_declaring_class 'true' if we can use the class itself. 202 * @param type_idx Type index to use if use_declaring_class is 'false'. 203 * @param rl_dest Result to be set to 0 or 1. 204 * @param rl_src Object to be tested. 205 */ 206 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 207 RegLocation rl_src); 208 /* 209 * 210 * @brief Implement Set up instanceof a class with x86 specific code. 211 * @param needs_access_check 'true' if we must check the access. 212 * @param type_known_final 'true' if the type is known to be a final class. 213 * @param type_known_abstract 'true' if the type is known to be an abstract class. 214 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 215 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 216 * @param type_idx Type index to use if use_declaring_class is 'false'. 217 * @param rl_dest Result to be set to 0 or 1. 218 * @param rl_src Object to be tested. 219 */ 220 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 221 bool type_known_abstract, bool use_declaring_class, 222 bool can_assume_type_is_in_dex_cache, 223 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 224 225 // Single operation generators. 226 LIR* OpUnconditionalBranch(LIR* target); 227 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 228 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 229 LIR* OpCondBranch(ConditionCode cc, LIR* target); 230 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 231 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 232 LIR* OpIT(ConditionCode cond, const char* guide); 233 void OpEndIT(LIR* it); 234 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 235 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 236 LIR* OpReg(OpKind op, RegStorage r_dest_src); 237 LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src); 238 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 239 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 240 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 241 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 242 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 243 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 244 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 245 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 246 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 247 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 248 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 249 LIR* OpTestSuspend(LIR* target); 250 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); 251 LIR* OpVldm(RegStorage r_base, int count); 252 LIR* OpVstm(RegStorage r_base, int count); 253 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 254 void OpRegCopyWide(RegStorage dest, RegStorage src); 255 void OpTlsCmp(ThreadOffset<4> offset, int val); 256 257 void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset<4> thread_offset); 258 void SpillCoreRegs(); 259 void UnSpillCoreRegs(); 260 static const X86EncodingMap EncodingMap[kX86Last]; 261 bool InexpensiveConstantInt(int32_t value); 262 bool InexpensiveConstantFloat(int32_t value); 263 bool InexpensiveConstantLong(int64_t value); 264 bool InexpensiveConstantDouble(int64_t value); 265 266 RegLocation UpdateLocWide(RegLocation loc); 267 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 268 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 269 RegStorage AllocTempDouble(); 270 void ResetDefLocWide(RegLocation rl); 271 272 /* 273 * @brief x86 specific codegen for int operations. 274 * @param opcode Operation to perform. 275 * @param rl_dest Destination for the result. 276 * @param rl_lhs Left hand operand. 277 * @param rl_rhs Right hand operand. 278 */ 279 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 280 RegLocation rl_rhs); 281 282 /* 283 * @brief Dump a RegLocation using printf 284 * @param loc Register location to dump 285 */ 286 static void DumpRegLocation(RegLocation loc); 287 288 /* 289 * @brief Load the Method* of a dex method into the register. 290 * @param target_method The MethodReference of the method to be invoked. 291 * @param type How the method will be invoked. 292 * @param register that will contain the code address. 293 * @note register will be passed to TargetReg to get physical register. 294 */ 295 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 296 SpecialTargetRegister symbolic_reg); 297 298 /* 299 * @brief Load the Class* of a Dex Class type into the register. 300 * @param type How the method will be invoked. 301 * @param register that will contain the code address. 302 * @note register will be passed to TargetReg to get physical register. 303 */ 304 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 305 306 /* 307 * @brief Generate a relative call to the method that will be patched at link time. 308 * @param target_method The MethodReference of the method to be invoked. 309 * @param type How the method will be invoked. 310 * @returns Call instruction 311 */ 312 LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 313 314 /* 315 * @brief Handle x86 specific literals 316 */ 317 void InstallLiteralPools(); 318 319 /* 320 * @brief Generate the debug_frame CFI information. 321 * @returns pointer to vector containing CFE information 322 */ 323 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 324 325 /* 326 * @brief Generate the debug_frame FDE information. 327 * @returns pointer to vector containing CFE information 328 */ 329 std::vector<uint8_t>* ReturnCallFrameInformation(); 330 331 private: 332 void EmitPrefix(const X86EncodingMap* entry); 333 void EmitOpcode(const X86EncodingMap* entry); 334 void EmitPrefixAndOpcode(const X86EncodingMap* entry); 335 void EmitDisp(uint8_t base, int disp); 336 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); 337 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); 338 void EmitImm(const X86EncodingMap* entry, int imm); 339 void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); 340 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); 341 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); 342 void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp); 343 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); 344 void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); 345 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); 346 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 347 int scale, int disp); 348 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 349 uint8_t reg); 350 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); 351 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); 352 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 353 void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 354 void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, 355 int32_t imm); 356 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 357 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); 358 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 359 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 360 void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); 361 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); 362 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); 363 364 /** 365 * @brief Used for encoding conditional register to register operation. 366 * @param entry The entry in the encoding map for the opcode. 367 * @param reg1 The first physical register. 368 * @param reg2 The second physical register. 369 * @param condition The condition code for operation. 370 */ 371 void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); 372 373 void EmitJmp(const X86EncodingMap* entry, int rel); 374 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); 375 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); 376 void EmitCallImmediate(const X86EncodingMap* entry, int disp); 377 void EmitCallThread(const X86EncodingMap* entry, int disp); 378 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, 379 int scale, int table_or_disp); 380 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); 381 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 382 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 383 int64_t val, ConditionCode ccode); 384 void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg); 385 void GenConstWide(RegLocation rl_dest, int64_t value); 386 387 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 388 389 /* 390 * @brief generate inline code for fast case of Strng.indexOf. 391 * @param info Call parameters 392 * @param zero_based 'true' if the index into the string is 0. 393 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 394 * generated. 395 */ 396 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 397 398 /* 399 * @brief Return the correct x86 opcode for the Dex operation 400 * @param op Dex opcode for the operation 401 * @param loc Register location of the operand 402 * @param is_high_op 'true' if this is an operation on the high word 403 * @param value Immediate value for the operation. Used for byte variants 404 * @returns the correct x86 opcode to perform the operation 405 */ 406 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 407 408 /* 409 * @brief Return the correct x86 opcode for the Dex operation 410 * @param op Dex opcode for the operation 411 * @param dest location of the destination. May be register or memory. 412 * @param rhs Location for the rhs of the operation. May be in register or memory. 413 * @param is_high_op 'true' if this is an operation on the high word 414 * @returns the correct x86 opcode to perform the operation 415 * @note at most one location may refer to memory 416 */ 417 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 418 bool is_high_op); 419 420 /* 421 * @brief Is this operation a no-op for this opcode and value 422 * @param op Dex opcode for the operation 423 * @param value Immediate value for the operation. 424 * @returns 'true' if the operation will have no effect 425 */ 426 bool IsNoOp(Instruction::Code op, int32_t value); 427 428 /** 429 * @brief Calculate magic number and shift for a given divisor 430 * @param divisor divisor number for calculation 431 * @param magic hold calculated magic number 432 * @param shift hold calculated shift 433 */ 434 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 435 436 /* 437 * @brief Generate an integer div or rem operation. 438 * @param rl_dest Destination Location. 439 * @param rl_src1 Numerator Location. 440 * @param rl_src2 Divisor Location. 441 * @param is_div 'true' if this is a division, 'false' for a remainder. 442 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 443 */ 444 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 445 bool is_div, bool check_zero); 446 447 /* 448 * @brief Generate an integer div or rem operation by a literal. 449 * @param rl_dest Destination Location. 450 * @param rl_src Numerator Location. 451 * @param lit Divisor. 452 * @param is_div 'true' if this is a division, 'false' for a remainder. 453 */ 454 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 455 456 /* 457 * Generate code to implement long shift operations. 458 * @param opcode The DEX opcode to specify the shift type. 459 * @param rl_dest The destination. 460 * @param rl_src The value to be shifted. 461 * @param shift_amount How much to shift. 462 * @returns the RegLocation of the result. 463 */ 464 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 465 RegLocation rl_src, int shift_amount); 466 /* 467 * Generate an imul of a register by a constant or a better sequence. 468 * @param dest Destination Register. 469 * @param src Source Register. 470 * @param val Constant multiplier. 471 */ 472 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 473 474 /* 475 * Generate an imul of a memory location by a constant or a better sequence. 476 * @param dest Destination Register. 477 * @param sreg Symbolic register. 478 * @param displacement Displacement on stack of Symbolic Register. 479 * @param val Constant multiplier. 480 */ 481 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 482 483 /* 484 * @brief Compare memory to immediate, and branch if condition true. 485 * @param cond The condition code that when true will branch to the target. 486 * @param temp_reg A temporary register that can be used if compare memory is not 487 * supported by the architecture. 488 * @param base_reg The register holding the base address. 489 * @param offset The offset from the base. 490 * @param check_value The immediate to compare to. 491 */ 492 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 493 int offset, int check_value, LIR* target); 494 495 /* 496 * Can this operation be using core registers without temporaries? 497 * @param rl_lhs Left hand operand. 498 * @param rl_rhs Right hand operand. 499 * @returns 'true' if the operation can proceed without needing temporary regs. 500 */ 501 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 502 503 /** 504 * @brief Generates inline code for conversion of long to FP by using x87/ 505 * @param rl_dest The destination of the FP. 506 * @param rl_src The source of the long. 507 * @param is_double 'true' if dealing with double, 'false' for float. 508 */ 509 void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 510 511 /* 512 * @brief Perform MIR analysis before compiling method. 513 * @note Invokes Mir2LiR::Materialize after analysis. 514 */ 515 void Materialize(); 516 517 /* 518 * @brief Analyze MIR before generating code, to prepare for the code generation. 519 */ 520 void AnalyzeMIR(); 521 522 /* 523 * @brief Analyze one basic block. 524 * @param bb Basic block to analyze. 525 */ 526 void AnalyzeBB(BasicBlock * bb); 527 528 /* 529 * @brief Analyze one extended MIR instruction 530 * @param opcode MIR instruction opcode. 531 * @param bb Basic block containing instruction. 532 * @param mir Extended instruction to analyze. 533 */ 534 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 535 536 /* 537 * @brief Analyze one MIR instruction 538 * @param opcode MIR instruction opcode. 539 * @param bb Basic block containing instruction. 540 * @param mir Instruction to analyze. 541 */ 542 void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 543 544 /* 545 * @brief Analyze one MIR float/double instruction 546 * @param opcode MIR instruction opcode. 547 * @param bb Basic block containing instruction. 548 * @param mir Instruction to analyze. 549 */ 550 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 551 552 /* 553 * @brief Analyze one use of a double operand. 554 * @param rl_use Double RegLocation for the operand. 555 */ 556 void AnalyzeDoubleUse(RegLocation rl_use); 557 558 // Information derived from analysis of MIR 559 560 // The compiler temporary for the code address of the method. 561 CompilerTemp *base_of_code_; 562 563 // Have we decided to compute a ptr to code and store in temporary VR? 564 bool store_method_addr_; 565 566 // Have we used the stored method address? 567 bool store_method_addr_used_; 568 569 // Instructions to remove if we didn't use the stored method address. 570 LIR* setup_method_address_[2]; 571 572 // Instructions needing patching with Method* values. 573 GrowableArray<LIR*> method_address_insns_; 574 575 // Instructions needing patching with Class Type* values. 576 GrowableArray<LIR*> class_type_address_insns_; 577 578 // Instructions needing patching with PC relative code addresses. 579 GrowableArray<LIR*> call_method_insns_; 580 581 // Prologue decrement of stack pointer. 582 LIR* stack_decrement_; 583 584 // Epilogue increment of stack pointer. 585 LIR* stack_increment_; 586}; 587 588} // namespace art 589 590#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 591