int_x86.cc revision 1c282e2b9a9b432e132b2c332f861cad9feb4a73
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the X86 ISA */ 18 19#include "codegen_x86.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "mirror/array.h" 22#include "x86_lir.h" 23 24namespace art { 25 26/* 27 * Perform register memory operation. 28 */ 29LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code, 30 int reg1, int base, int offset, ThrowKind kind) { 31 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, 32 current_dalvik_offset_, reg1, base, offset); 33 OpRegMem(kOpCmp, reg1, base, offset); 34 LIR* branch = OpCondBranch(c_code, tgt); 35 // Remember branch target - will process later 36 throw_launchpads_.Insert(tgt); 37 return branch; 38} 39 40/* 41 * Compare two 64-bit values 42 * x = y return 0 43 * x < y return -1 44 * x > y return 1 45 */ 46void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 47 RegLocation rl_src2) { 48 FlushAllRegs(); 49 LockCallTemps(); // Prepare for explicit register usage 50 LoadValueDirectWideFixed(rl_src1, r0, r1); 51 LoadValueDirectWideFixed(rl_src2, r2, r3); 52 // Compute (r1:r0) = (r1:r0) - (r3:r2) 53 OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2 54 OpRegReg(kOpSbc, r1, r3); // r1 = r1 - r3 - CF 55 NewLIR2(kX86Set8R, r2, kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 56 NewLIR2(kX86Movzx8RR, r2, r2); 57 OpReg(kOpNeg, r2); // r2 = -r2 58 OpRegReg(kOpOr, r0, r1); // r0 = high | low - sets ZF 59 NewLIR2(kX86Set8R, r0, kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 60 NewLIR2(kX86Movzx8RR, r0, r0); 61 OpRegReg(kOpOr, r0, r2); // r0 = r0 | r2 62 RegLocation rl_result = LocCReturn(); 63 StoreValue(rl_dest, rl_result); 64} 65 66X86ConditionCode X86ConditionEncoding(ConditionCode cond) { 67 switch (cond) { 68 case kCondEq: return kX86CondEq; 69 case kCondNe: return kX86CondNe; 70 case kCondCs: return kX86CondC; 71 case kCondCc: return kX86CondNc; 72 case kCondMi: return kX86CondS; 73 case kCondPl: return kX86CondNs; 74 case kCondVs: return kX86CondO; 75 case kCondVc: return kX86CondNo; 76 case kCondHi: return kX86CondA; 77 case kCondLs: return kX86CondBe; 78 case kCondGe: return kX86CondGe; 79 case kCondLt: return kX86CondL; 80 case kCondGt: return kX86CondG; 81 case kCondLe: return kX86CondLe; 82 case kCondAl: 83 case kCondNv: LOG(FATAL) << "Should not reach here"; 84 } 85 return kX86CondO; 86} 87 88LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2, 89 LIR* target) { 90 NewLIR2(kX86Cmp32RR, src1, src2); 91 X86ConditionCode cc = X86ConditionEncoding(cond); 92 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , 93 cc); 94 branch->target = target; 95 return branch; 96} 97 98LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg, 99 int check_value, LIR* target) { 100 if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { 101 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode 102 NewLIR2(kX86Test32RR, reg, reg); 103 } else { 104 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg, check_value); 105 } 106 X86ConditionCode cc = X86ConditionEncoding(cond); 107 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); 108 branch->target = target; 109 return branch; 110} 111 112LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) { 113 if (X86_FPREG(r_dest) || X86_FPREG(r_src)) 114 return OpFpRegCopy(r_dest, r_src); 115 LIR* res = RawLIR(current_dalvik_offset_, kX86Mov32RR, 116 r_dest, r_src); 117 if (r_dest == r_src) { 118 res->flags.is_nop = true; 119 } 120 return res; 121} 122 123LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) { 124 LIR *res = OpRegCopyNoInsert(r_dest, r_src); 125 AppendLIR(res); 126 return res; 127} 128 129void X86Mir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, 130 int src_lo, int src_hi) { 131 bool dest_fp = X86_FPREG(dest_lo) && X86_FPREG(dest_hi); 132 bool src_fp = X86_FPREG(src_lo) && X86_FPREG(src_hi); 133 assert(X86_FPREG(src_lo) == X86_FPREG(src_hi)); 134 assert(X86_FPREG(dest_lo) == X86_FPREG(dest_hi)); 135 if (dest_fp) { 136 if (src_fp) { 137 OpRegCopy(S2d(dest_lo, dest_hi), S2d(src_lo, src_hi)); 138 } else { 139 // TODO: Prevent this from happening in the code. The result is often 140 // unused or could have been loaded more easily from memory. 141 NewLIR2(kX86MovdxrRR, dest_lo, src_lo); 142 NewLIR2(kX86MovdxrRR, dest_hi, src_hi); 143 NewLIR2(kX86PsllqRI, dest_hi, 32); 144 NewLIR2(kX86OrpsRR, dest_lo, dest_hi); 145 } 146 } else { 147 if (src_fp) { 148 NewLIR2(kX86MovdrxRR, dest_lo, src_lo); 149 NewLIR2(kX86PsrlqRI, src_lo, 32); 150 NewLIR2(kX86MovdrxRR, dest_hi, src_lo); 151 } else { 152 // Handle overlap 153 if (src_hi == dest_lo) { 154 OpRegCopy(dest_hi, src_hi); 155 OpRegCopy(dest_lo, src_lo); 156 } else { 157 OpRegCopy(dest_lo, src_lo); 158 OpRegCopy(dest_hi, src_hi); 159 } 160 } 161 } 162} 163 164void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 165 UNIMPLEMENTED(FATAL) << "Need codegen for GenSelect"; 166} 167 168void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 169 LIR* taken = &block_label_list_[bb->taken]; 170 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 171 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 172 FlushAllRegs(); 173 LockCallTemps(); // Prepare for explicit register usage 174 LoadValueDirectWideFixed(rl_src1, r0, r1); 175 LoadValueDirectWideFixed(rl_src2, r2, r3); 176 ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]); 177 // Swap operands and condition code to prevent use of zero flag. 178 if (ccode == kCondLe || ccode == kCondGt) { 179 // Compute (r3:r2) = (r3:r2) - (r1:r0) 180 OpRegReg(kOpSub, r2, r0); // r2 = r2 - r0 181 OpRegReg(kOpSbc, r3, r1); // r3 = r3 - r1 - CF 182 } else { 183 // Compute (r1:r0) = (r1:r0) - (r3:r2) 184 OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2 185 OpRegReg(kOpSbc, r1, r3); // r1 = r1 - r3 - CF 186 } 187 switch (ccode) { 188 case kCondEq: 189 case kCondNe: 190 OpRegReg(kOpOr, r0, r1); // r0 = r0 | r1 191 break; 192 case kCondLe: 193 ccode = kCondGe; 194 break; 195 case kCondGt: 196 ccode = kCondLt; 197 break; 198 case kCondLt: 199 case kCondGe: 200 break; 201 default: 202 LOG(FATAL) << "Unexpected ccode: " << ccode; 203 } 204 OpCondBranch(ccode, taken); 205} 206 207RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, int reg_lo, 208 int lit, bool is_div) { 209 LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; 210 return rl_dest; 211} 212 213RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, int reg_lo, 214 int reg_hi, bool is_div) { 215 LOG(FATAL) << "Unexpected use of GenDivRem for x86"; 216 return rl_dest; 217} 218 219bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { 220 DCHECK_EQ(cu_->instruction_set, kX86); 221 RegLocation rl_src1 = info->args[0]; 222 RegLocation rl_src2 = info->args[1]; 223 rl_src1 = LoadValue(rl_src1, kCoreReg); 224 rl_src2 = LoadValue(rl_src2, kCoreReg); 225 RegLocation rl_dest = InlineTarget(info); 226 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 227 OpRegReg(kOpCmp, rl_src1.low_reg, rl_src2.low_reg); 228 DCHECK_EQ(cu_->instruction_set, kX86); 229 LIR* branch = NewLIR2(kX86Jcc8, 0, is_min ? kX86CondG : kX86CondL); 230 OpRegReg(kOpMov, rl_result.low_reg, rl_src1.low_reg); 231 LIR* branch2 = NewLIR1(kX86Jmp8, 0); 232 branch->target = NewLIR0(kPseudoTargetLabel); 233 OpRegReg(kOpMov, rl_result.low_reg, rl_src2.low_reg); 234 branch2->target = NewLIR0(kPseudoTargetLabel); 235 StoreValue(rl_dest, rl_result); 236 return true; 237} 238 239bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 240 RegLocation rl_src_address = info->args[0]; // long address 241 rl_src_address.wide = 0; // ignore high half in info->args[1] 242 RegLocation rl_dest = InlineTarget(info); 243 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 244 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 245 if (size == kLong) { 246 // Unaligned access is allowed on x86. 247 LoadBaseDispWide(rl_address.low_reg, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); 248 StoreValueWide(rl_dest, rl_result); 249 } else { 250 DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord); 251 // Unaligned access is allowed on x86. 252 LoadBaseDisp(rl_address.low_reg, 0, rl_result.low_reg, size, INVALID_SREG); 253 StoreValue(rl_dest, rl_result); 254 } 255 return true; 256} 257 258bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 259 RegLocation rl_src_address = info->args[0]; // long address 260 rl_src_address.wide = 0; // ignore high half in info->args[1] 261 RegLocation rl_src_value = info->args[2]; // [size] value 262 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 263 if (size == kLong) { 264 // Unaligned access is allowed on x86. 265 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 266 StoreBaseDispWide(rl_address.low_reg, 0, rl_value.low_reg, rl_value.high_reg); 267 } else { 268 DCHECK(size == kSignedByte || size == kSignedHalf || size == kWord); 269 // Unaligned access is allowed on x86. 270 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 271 StoreBaseDisp(rl_address.low_reg, 0, rl_value.low_reg, size); 272 } 273 return true; 274} 275 276void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { 277 NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset); 278} 279 280void X86Mir2Lir::OpTlsCmp(ThreadOffset offset, int val) { 281 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 282} 283 284bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 285 DCHECK_NE(cu_->instruction_set, kThumb2); 286 return false; 287} 288 289LIR* X86Mir2Lir::OpPcRelLoad(int reg, LIR* target) { 290 LOG(FATAL) << "Unexpected use of OpPcRelLoad for x86"; 291 return NULL; 292} 293 294LIR* X86Mir2Lir::OpVldm(int rBase, int count) { 295 LOG(FATAL) << "Unexpected use of OpVldm for x86"; 296 return NULL; 297} 298 299LIR* X86Mir2Lir::OpVstm(int rBase, int count) { 300 LOG(FATAL) << "Unexpected use of OpVstm for x86"; 301 return NULL; 302} 303 304void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 305 RegLocation rl_result, int lit, 306 int first_bit, int second_bit) { 307 int t_reg = AllocTemp(); 308 OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit); 309 OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg); 310 FreeTemp(t_reg); 311 if (first_bit != 0) { 312 OpRegRegImm(kOpLsl, rl_result.low_reg, rl_result.low_reg, first_bit); 313 } 314} 315 316void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) { 317 int t_reg = AllocTemp(); 318 OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi); 319 GenImmedCheck(kCondEq, t_reg, 0, kThrowDivZero); 320 FreeTemp(t_reg); 321} 322 323// Test suspend flag, return target of taken suspend branch 324LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { 325 OpTlsCmp(Thread::ThreadFlagsOffset(), 0); 326 return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); 327} 328 329// Decrement register and branch on condition 330LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) { 331 OpRegImm(kOpSub, reg, 1); 332 return OpCmpImmBranch(c_code, reg, 0, target); 333} 334 335bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 336 RegLocation rl_src, RegLocation rl_dest, int lit) { 337 LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; 338 return false; 339} 340 341LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { 342 LOG(FATAL) << "Unexpected use of OpIT in x86"; 343 return NULL; 344} 345 346void X86Mir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1, 347 RegLocation rl_src2) { 348 LOG(FATAL) << "Unexpected use of GenX86Long for x86"; 349} 350void X86Mir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1, 351 RegLocation rl_src2) { 352 // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart 353 // enough. 354 FlushAllRegs(); 355 LockCallTemps(); // Prepare for explicit register usage 356 LoadValueDirectWideFixed(rl_src1, r0, r1); 357 LoadValueDirectWideFixed(rl_src2, r2, r3); 358 // Compute (r1:r0) = (r1:r0) + (r2:r3) 359 OpRegReg(kOpAdd, r0, r2); // r0 = r0 + r2 360 OpRegReg(kOpAdc, r1, r3); // r1 = r1 + r3 + CF 361 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 362 INVALID_SREG, INVALID_SREG}; 363 StoreValueWide(rl_dest, rl_result); 364} 365 366void X86Mir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1, 367 RegLocation rl_src2) { 368 // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart 369 // enough. 370 FlushAllRegs(); 371 LockCallTemps(); // Prepare for explicit register usage 372 LoadValueDirectWideFixed(rl_src1, r0, r1); 373 LoadValueDirectWideFixed(rl_src2, r2, r3); 374 // Compute (r1:r0) = (r1:r0) + (r2:r3) 375 OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2 376 OpRegReg(kOpSbc, r1, r3); // r1 = r1 - r3 - CF 377 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 378 INVALID_SREG, INVALID_SREG}; 379 StoreValueWide(rl_dest, rl_result); 380} 381 382void X86Mir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1, 383 RegLocation rl_src2) { 384 // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart 385 // enough. 386 FlushAllRegs(); 387 LockCallTemps(); // Prepare for explicit register usage 388 LoadValueDirectWideFixed(rl_src1, r0, r1); 389 LoadValueDirectWideFixed(rl_src2, r2, r3); 390 // Compute (r1:r0) = (r1:r0) & (r2:r3) 391 OpRegReg(kOpAnd, r0, r2); // r0 = r0 & r2 392 OpRegReg(kOpAnd, r1, r3); // r1 = r1 & r3 393 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 394 INVALID_SREG, INVALID_SREG}; 395 StoreValueWide(rl_dest, rl_result); 396} 397 398void X86Mir2Lir::GenOrLong(RegLocation rl_dest, 399 RegLocation rl_src1, RegLocation rl_src2) { 400 // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart 401 // enough. 402 FlushAllRegs(); 403 LockCallTemps(); // Prepare for explicit register usage 404 LoadValueDirectWideFixed(rl_src1, r0, r1); 405 LoadValueDirectWideFixed(rl_src2, r2, r3); 406 // Compute (r1:r0) = (r1:r0) | (r2:r3) 407 OpRegReg(kOpOr, r0, r2); // r0 = r0 | r2 408 OpRegReg(kOpOr, r1, r3); // r1 = r1 | r3 409 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 410 INVALID_SREG, INVALID_SREG}; 411 StoreValueWide(rl_dest, rl_result); 412} 413 414void X86Mir2Lir::GenXorLong(RegLocation rl_dest, 415 RegLocation rl_src1, RegLocation rl_src2) { 416 // TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart 417 // enough. 418 FlushAllRegs(); 419 LockCallTemps(); // Prepare for explicit register usage 420 LoadValueDirectWideFixed(rl_src1, r0, r1); 421 LoadValueDirectWideFixed(rl_src2, r2, r3); 422 // Compute (r1:r0) = (r1:r0) ^ (r2:r3) 423 OpRegReg(kOpXor, r0, r2); // r0 = r0 ^ r2 424 OpRegReg(kOpXor, r1, r3); // r1 = r1 ^ r3 425 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 426 INVALID_SREG, INVALID_SREG}; 427 StoreValueWide(rl_dest, rl_result); 428} 429 430void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 431 FlushAllRegs(); 432 LockCallTemps(); // Prepare for explicit register usage 433 LoadValueDirectWideFixed(rl_src, r0, r1); 434 // Compute (r1:r0) = -(r1:r0) 435 OpRegReg(kOpNeg, r0, r0); // r0 = -r0 436 OpRegImm(kOpAdc, r1, 0); // r1 = r1 + CF 437 OpRegReg(kOpNeg, r1, r1); // r1 = -r1 438 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, 439 INVALID_SREG, INVALID_SREG}; 440 StoreValueWide(rl_dest, rl_result); 441} 442 443void X86Mir2Lir::OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset) { 444 X86OpCode opcode = kX86Bkpt; 445 switch (op) { 446 case kOpCmp: opcode = kX86Cmp32RT; break; 447 case kOpMov: opcode = kX86Mov32RT; break; 448 default: 449 LOG(FATAL) << "Bad opcode: " << op; 450 break; 451 } 452 NewLIR2(opcode, r_dest, thread_offset.Int32Value()); 453} 454 455/* 456 * Generate array load 457 */ 458void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 459 RegLocation rl_index, RegLocation rl_dest, int scale) { 460 RegisterClass reg_class = oat_reg_class_by_size(size); 461 int len_offset = mirror::Array::LengthOffset().Int32Value(); 462 int data_offset; 463 RegLocation rl_result; 464 rl_array = LoadValue(rl_array, kCoreReg); 465 rl_index = LoadValue(rl_index, kCoreReg); 466 467 if (size == kLong || size == kDouble) { 468 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 469 } else { 470 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 471 } 472 473 /* null object? */ 474 GenNullCheck(rl_array.s_reg_low, rl_array.low_reg, opt_flags); 475 476 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 477 /* if (rl_index >= [rl_array + len_offset]) goto kThrowArrayBounds */ 478 GenRegMemCheck(kCondUge, rl_index.low_reg, rl_array.low_reg, 479 len_offset, kThrowArrayBounds); 480 } 481 if ((size == kLong) || (size == kDouble)) { 482 int reg_addr = AllocTemp(); 483 OpLea(reg_addr, rl_array.low_reg, rl_index.low_reg, scale, data_offset); 484 FreeTemp(rl_array.low_reg); 485 FreeTemp(rl_index.low_reg); 486 rl_result = EvalLoc(rl_dest, reg_class, true); 487 LoadBaseIndexedDisp(reg_addr, INVALID_REG, 0, 0, rl_result.low_reg, 488 rl_result.high_reg, size, INVALID_SREG); 489 StoreValueWide(rl_dest, rl_result); 490 } else { 491 rl_result = EvalLoc(rl_dest, reg_class, true); 492 493 LoadBaseIndexedDisp(rl_array.low_reg, rl_index.low_reg, scale, 494 data_offset, rl_result.low_reg, INVALID_REG, size, 495 INVALID_SREG); 496 497 StoreValue(rl_dest, rl_result); 498 } 499} 500 501/* 502 * Generate array store 503 * 504 */ 505void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 506 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 507 RegisterClass reg_class = oat_reg_class_by_size(size); 508 int len_offset = mirror::Array::LengthOffset().Int32Value(); 509 int data_offset; 510 511 if (size == kLong || size == kDouble) { 512 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 513 } else { 514 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 515 } 516 517 rl_array = LoadValue(rl_array, kCoreReg); 518 rl_index = LoadValue(rl_index, kCoreReg); 519 520 /* null object? */ 521 GenNullCheck(rl_array.s_reg_low, rl_array.low_reg, opt_flags); 522 523 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 524 /* if (rl_index >= [rl_array + len_offset]) goto kThrowArrayBounds */ 525 GenRegMemCheck(kCondUge, rl_index.low_reg, rl_array.low_reg, len_offset, kThrowArrayBounds); 526 } 527 if ((size == kLong) || (size == kDouble)) { 528 rl_src = LoadValueWide(rl_src, reg_class); 529 } else { 530 rl_src = LoadValue(rl_src, reg_class); 531 } 532 // If the src reg can't be byte accessed, move it to a temp first. 533 if ((size == kSignedByte || size == kUnsignedByte) && rl_src.low_reg >= 4) { 534 int temp = AllocTemp(); 535 OpRegCopy(temp, rl_src.low_reg); 536 StoreBaseIndexedDisp(rl_array.low_reg, rl_index.low_reg, scale, data_offset, temp, 537 INVALID_REG, size, INVALID_SREG); 538 } else { 539 StoreBaseIndexedDisp(rl_array.low_reg, rl_index.low_reg, scale, data_offset, rl_src.low_reg, 540 rl_src.high_reg, size, INVALID_SREG); 541 } 542 if (card_mark) { 543 // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. 544 FreeTemp(rl_index.low_reg); 545 MarkGCCard(rl_src.low_reg, rl_array.low_reg); 546 } 547} 548 549void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 550 RegLocation rl_src1, RegLocation rl_shift) { 551 // Default implementation is just to ignore the constant case. 552 GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); 553} 554 555void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, 556 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 557 // Default - bail to non-const handler. 558 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 559} 560 561} // namespace art 562