int_x86.cc revision d8191d000413504b33702e0f52e1e8e522a47ec0
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the X86 ISA */ 18 19#include "codegen_x86.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "mirror/array.h" 22#include "x86_lir.h" 23 24namespace art { 25 26/* 27 * Compare two 64-bit values 28 * x = y return 0 29 * x < y return -1 30 * x > y return 1 31 */ 32void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 33 RegLocation rl_src2) { 34 if (Gen64Bit()) { 35 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 36 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 37 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 38 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); // result = 0 39 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 40 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondNe); // result = (src1 != src2) ? 1 : result 41 RegStorage temp_reg = AllocTemp(); 42 OpRegReg(kOpNeg, temp_reg, rl_result.reg); 43 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 44 // result = (src1 < src2) ? -result : result 45 OpCondRegReg(kOpCmov, kCondLt, rl_result.reg, temp_reg); 46 StoreValue(rl_dest, rl_result); 47 FreeTemp(temp_reg); 48 return; 49 } 50 51 FlushAllRegs(); 52 LockCallTemps(); // Prepare for explicit register usage 53 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 54 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 55 LoadValueDirectWideFixed(rl_src1, r_tmp1); 56 LoadValueDirectWideFixed(rl_src2, r_tmp2); 57 // Compute (r1:r0) = (r1:r0) - (r3:r2) 58 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 59 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 60 NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 61 NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); 62 OpReg(kOpNeg, rs_r2); // r2 = -r2 63 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF 64 NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 65 NewLIR2(kX86Movzx8RR, r0, r0); 66 OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 67 RegLocation rl_result = LocCReturn(); 68 StoreValue(rl_dest, rl_result); 69} 70 71X86ConditionCode X86ConditionEncoding(ConditionCode cond) { 72 switch (cond) { 73 case kCondEq: return kX86CondEq; 74 case kCondNe: return kX86CondNe; 75 case kCondCs: return kX86CondC; 76 case kCondCc: return kX86CondNc; 77 case kCondUlt: return kX86CondC; 78 case kCondUge: return kX86CondNc; 79 case kCondMi: return kX86CondS; 80 case kCondPl: return kX86CondNs; 81 case kCondVs: return kX86CondO; 82 case kCondVc: return kX86CondNo; 83 case kCondHi: return kX86CondA; 84 case kCondLs: return kX86CondBe; 85 case kCondGe: return kX86CondGe; 86 case kCondLt: return kX86CondL; 87 case kCondGt: return kX86CondG; 88 case kCondLe: return kX86CondLe; 89 case kCondAl: 90 case kCondNv: LOG(FATAL) << "Should not reach here"; 91 } 92 return kX86CondO; 93} 94 95LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { 96 NewLIR2(kX86Cmp32RR, src1.GetReg(), src2.GetReg()); 97 X86ConditionCode cc = X86ConditionEncoding(cond); 98 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , 99 cc); 100 branch->target = target; 101 return branch; 102} 103 104LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, 105 int check_value, LIR* target) { 106 if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { 107 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode 108 NewLIR2(kX86Test32RR, reg.GetReg(), reg.GetReg()); 109 } else { 110 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); 111 } 112 X86ConditionCode cc = X86ConditionEncoding(cond); 113 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); 114 branch->target = target; 115 return branch; 116} 117 118LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 119 // If src or dest is a pair, we'll be using low reg. 120 if (r_dest.IsPair()) { 121 r_dest = r_dest.GetLow(); 122 } 123 if (r_src.IsPair()) { 124 r_src = r_src.GetLow(); 125 } 126 if (r_dest.IsFloat() || r_src.IsFloat()) 127 return OpFpRegCopy(r_dest, r_src); 128 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, 129 r_dest.GetReg(), r_src.GetReg()); 130 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 131 res->flags.is_nop = true; 132 } 133 return res; 134} 135 136void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 137 if (r_dest != r_src) { 138 LIR *res = OpRegCopyNoInsert(r_dest, r_src); 139 AppendLIR(res); 140 } 141} 142 143void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { 144 if (r_dest != r_src) { 145 bool dest_fp = r_dest.IsFloat(); 146 bool src_fp = r_src.IsFloat(); 147 if (dest_fp) { 148 if (src_fp) { 149 OpRegCopy(r_dest, r_src); 150 } else { 151 // TODO: Prevent this from happening in the code. The result is often 152 // unused or could have been loaded more easily from memory. 153 if (!r_src.IsPair()) { 154 DCHECK(!r_dest.IsPair()); 155 NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); 156 } else { 157 NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); 158 RegStorage r_tmp = AllocTempDouble(); 159 NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); 160 NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); 161 FreeTemp(r_tmp); 162 } 163 } 164 } else { 165 if (src_fp) { 166 if (!r_dest.IsPair()) { 167 DCHECK(!r_src.IsPair()); 168 NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); 169 } else { 170 NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); 171 RegStorage temp_reg = AllocTempDouble(); 172 NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); 173 NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); 174 NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); 175 } 176 } else { 177 DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); 178 if (!r_src.IsPair()) { 179 // Just copy the register directly. 180 OpRegCopy(r_dest, r_src); 181 } else { 182 // Handle overlap 183 if (r_src.GetHighReg() == r_dest.GetLowReg() && 184 r_src.GetLowReg() == r_dest.GetHighReg()) { 185 // Deal with cycles. 186 RegStorage temp_reg = AllocTemp(); 187 OpRegCopy(temp_reg, r_dest.GetHigh()); 188 OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); 189 OpRegCopy(r_dest.GetLow(), temp_reg); 190 FreeTemp(temp_reg); 191 } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { 192 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 193 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 194 } else { 195 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 196 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 197 } 198 } 199 } 200 } 201 } 202} 203 204void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 205 RegLocation rl_result; 206 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 207 RegLocation rl_dest = mir_graph_->GetDest(mir); 208 // Avoid using float regs here. 209 RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; 210 RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; 211 rl_src = LoadValue(rl_src, src_reg_class); 212 ConditionCode ccode = mir->meta.ccode; 213 214 // The kMirOpSelect has two variants, one for constants and one for moves. 215 const bool is_constant_case = (mir->ssa_rep->num_uses == 1); 216 217 if (is_constant_case) { 218 int true_val = mir->dalvikInsn.vB; 219 int false_val = mir->dalvikInsn.vC; 220 rl_result = EvalLoc(rl_dest, result_reg_class, true); 221 222 /* 223 * For ccode == kCondEq: 224 * 225 * 1) When the true case is zero and result_reg is not same as src_reg: 226 * xor result_reg, result_reg 227 * cmp $0, src_reg 228 * mov t1, $false_case 229 * cmovnz result_reg, t1 230 * 2) When the false case is zero and result_reg is not same as src_reg: 231 * xor result_reg, result_reg 232 * cmp $0, src_reg 233 * mov t1, $true_case 234 * cmovz result_reg, t1 235 * 3) All other cases (we do compare first to set eflags): 236 * cmp $0, src_reg 237 * mov result_reg, $false_case 238 * mov t1, $true_case 239 * cmovz result_reg, t1 240 */ 241 // FIXME: depending on how you use registers you could get a false != mismatch when dealing 242 // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). 243 const bool result_reg_same_as_src = 244 (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg()); 245 const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); 246 const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); 247 const bool catch_all_case = !(true_zero_case || false_zero_case); 248 249 if (true_zero_case || false_zero_case) { 250 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); 251 } 252 253 if (true_zero_case || false_zero_case || catch_all_case) { 254 OpRegImm(kOpCmp, rl_src.reg, 0); 255 } 256 257 if (catch_all_case) { 258 OpRegImm(kOpMov, rl_result.reg, false_val); 259 } 260 261 if (true_zero_case || false_zero_case || catch_all_case) { 262 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; 263 int immediateForTemp = true_zero_case ? false_val : true_val; 264 RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); 265 OpRegImm(kOpMov, temp1_reg, immediateForTemp); 266 267 OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); 268 269 FreeTemp(temp1_reg); 270 } 271 } else { 272 RegLocation rl_true = mir_graph_->GetSrc(mir, 1); 273 RegLocation rl_false = mir_graph_->GetSrc(mir, 2); 274 rl_true = LoadValue(rl_true, result_reg_class); 275 rl_false = LoadValue(rl_false, result_reg_class); 276 rl_result = EvalLoc(rl_dest, result_reg_class, true); 277 278 /* 279 * For ccode == kCondEq: 280 * 281 * 1) When true case is already in place: 282 * cmp $0, src_reg 283 * cmovnz result_reg, false_reg 284 * 2) When false case is already in place: 285 * cmp $0, src_reg 286 * cmovz result_reg, true_reg 287 * 3) When neither cases are in place: 288 * cmp $0, src_reg 289 * mov result_reg, false_reg 290 * cmovz result_reg, true_reg 291 */ 292 293 // kMirOpSelect is generated just for conditional cases when comparison is done with zero. 294 OpRegImm(kOpCmp, rl_src.reg, 0); 295 296 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { 297 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); 298 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { 299 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 300 } else { 301 OpRegCopy(rl_result.reg, rl_false.reg); 302 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 303 } 304 } 305 306 StoreValue(rl_dest, rl_result); 307} 308 309void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 310 LIR* taken = &block_label_list_[bb->taken]; 311 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 312 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 313 ConditionCode ccode = mir->meta.ccode; 314 315 if (rl_src1.is_const) { 316 std::swap(rl_src1, rl_src2); 317 ccode = FlipComparisonOrder(ccode); 318 } 319 if (rl_src2.is_const) { 320 // Do special compare/branch against simple const operand 321 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 322 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); 323 return; 324 } 325 326 FlushAllRegs(); 327 LockCallTemps(); // Prepare for explicit register usage 328 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 329 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 330 LoadValueDirectWideFixed(rl_src1, r_tmp1); 331 LoadValueDirectWideFixed(rl_src2, r_tmp2); 332 // Swap operands and condition code to prevent use of zero flag. 333 if (ccode == kCondLe || ccode == kCondGt) { 334 // Compute (r3:r2) = (r3:r2) - (r1:r0) 335 OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 336 OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF 337 } else { 338 // Compute (r1:r0) = (r1:r0) - (r3:r2) 339 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 340 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 341 } 342 switch (ccode) { 343 case kCondEq: 344 case kCondNe: 345 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 346 break; 347 case kCondLe: 348 ccode = kCondGe; 349 break; 350 case kCondGt: 351 ccode = kCondLt; 352 break; 353 case kCondLt: 354 case kCondGe: 355 break; 356 default: 357 LOG(FATAL) << "Unexpected ccode: " << ccode; 358 } 359 OpCondBranch(ccode, taken); 360} 361 362void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 363 int64_t val, ConditionCode ccode) { 364 int32_t val_lo = Low32Bits(val); 365 int32_t val_hi = High32Bits(val); 366 LIR* taken = &block_label_list_[bb->taken]; 367 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 368 bool is_equality_test = ccode == kCondEq || ccode == kCondNe; 369 if (is_equality_test && val != 0) { 370 rl_src1 = ForceTempWide(rl_src1); 371 } 372 RegStorage low_reg = rl_src1.reg.GetLow(); 373 RegStorage high_reg = rl_src1.reg.GetHigh(); 374 375 if (is_equality_test) { 376 // We can simpolify of comparing for ==, != to 0. 377 if (val == 0) { 378 if (IsTemp(low_reg)) { 379 OpRegReg(kOpOr, low_reg, high_reg); 380 // We have now changed it; ignore the old values. 381 Clobber(rl_src1.reg); 382 } else { 383 RegStorage t_reg = AllocTemp(); 384 OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); 385 FreeTemp(t_reg); 386 } 387 OpCondBranch(ccode, taken); 388 return; 389 } 390 391 // Need to compute the actual value for ==, !=. 392 OpRegImm(kOpSub, low_reg, val_lo); 393 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 394 OpRegReg(kOpOr, high_reg, low_reg); 395 Clobber(rl_src1.reg); 396 } else if (ccode == kCondLe || ccode == kCondGt) { 397 // Swap operands and condition code to prevent use of zero flag. 398 RegStorage tmp = AllocTypedTempWide(false, kCoreReg); 399 LoadConstantWide(tmp, val); 400 OpRegReg(kOpSub, tmp.GetLow(), low_reg); 401 OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); 402 ccode = (ccode == kCondLe) ? kCondGe : kCondLt; 403 FreeTemp(tmp); 404 } else { 405 // We can use a compare for the low word to set CF. 406 OpRegImm(kOpCmp, low_reg, val_lo); 407 if (IsTemp(high_reg)) { 408 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 409 // We have now changed it; ignore the old values. 410 Clobber(rl_src1.reg); 411 } else { 412 // mov temp_reg, high_reg; sbb temp_reg, high_constant 413 RegStorage t_reg = AllocTemp(); 414 OpRegCopy(t_reg, high_reg); 415 NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); 416 FreeTemp(t_reg); 417 } 418 } 419 420 OpCondBranch(ccode, taken); 421} 422 423void X86Mir2Lir::CalculateMagicAndShift(int divisor, int& magic, int& shift) { 424 // It does not make sense to calculate magic and shift for zero divisor. 425 DCHECK_NE(divisor, 0); 426 427 /* According to H.S.Warren's Hacker's Delight Chapter 10 and 428 * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 429 * The magic number M and shift S can be calculated in the following way: 430 * Let nc be the most positive value of numerator(n) such that nc = kd - 1, 431 * where divisor(d) >=2. 432 * Let nc be the most negative value of numerator(n) such that nc = kd + 1, 433 * where divisor(d) <= -2. 434 * Thus nc can be calculated like: 435 * nc = 2^31 + 2^31 % d - 1, where d >= 2 436 * nc = -2^31 + (2^31 + 1) % d, where d >= 2. 437 * 438 * So the shift p is the smallest p satisfying 439 * 2^p > nc * (d - 2^p % d), where d >= 2 440 * 2^p > nc * (d + 2^p % d), where d <= -2. 441 * 442 * the magic number M is calcuated by 443 * M = (2^p + d - 2^p % d) / d, where d >= 2 444 * M = (2^p - d - 2^p % d) / d, where d <= -2. 445 * 446 * Notice that p is always bigger than or equal to 32, so we just return 32-p as 447 * the shift number S. 448 */ 449 450 int32_t p = 31; 451 const uint32_t two31 = 0x80000000U; 452 453 // Initialize the computations. 454 uint32_t abs_d = (divisor >= 0) ? divisor : -divisor; 455 uint32_t tmp = two31 + (static_cast<uint32_t>(divisor) >> 31); 456 uint32_t abs_nc = tmp - 1 - tmp % abs_d; 457 uint32_t quotient1 = two31 / abs_nc; 458 uint32_t remainder1 = two31 % abs_nc; 459 uint32_t quotient2 = two31 / abs_d; 460 uint32_t remainder2 = two31 % abs_d; 461 462 /* 463 * To avoid handling both positive and negative divisor, Hacker's Delight 464 * introduces a method to handle these 2 cases together to avoid duplication. 465 */ 466 uint32_t delta; 467 do { 468 p++; 469 quotient1 = 2 * quotient1; 470 remainder1 = 2 * remainder1; 471 if (remainder1 >= abs_nc) { 472 quotient1++; 473 remainder1 = remainder1 - abs_nc; 474 } 475 quotient2 = 2 * quotient2; 476 remainder2 = 2 * remainder2; 477 if (remainder2 >= abs_d) { 478 quotient2++; 479 remainder2 = remainder2 - abs_d; 480 } 481 delta = abs_d - remainder2; 482 } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); 483 484 magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); 485 shift = p - 32; 486} 487 488RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { 489 LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; 490 return rl_dest; 491} 492 493RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, 494 int imm, bool is_div) { 495 // Use a multiply (and fixup) to perform an int div/rem by a constant. 496 497 // We have to use fixed registers, so flush all the temps. 498 FlushAllRegs(); 499 LockCallTemps(); // Prepare for explicit register usage. 500 501 // Assume that the result will be in EDX. 502 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; 503 504 // handle div/rem by 1 special case. 505 if (imm == 1) { 506 if (is_div) { 507 // x / 1 == x. 508 StoreValue(rl_result, rl_src); 509 } else { 510 // x % 1 == 0. 511 LoadConstantNoClobber(rs_r0, 0); 512 // For this case, return the result in EAX. 513 rl_result.reg.SetReg(r0); 514 } 515 } else if (imm == -1) { // handle 0x80000000 / -1 special case. 516 if (is_div) { 517 LIR *minint_branch = 0; 518 LoadValueDirectFixed(rl_src, rs_r0); 519 OpRegImm(kOpCmp, rs_r0, 0x80000000); 520 minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); 521 522 // for x != MIN_INT, x / -1 == -x. 523 NewLIR1(kX86Neg32R, r0); 524 525 LIR* branch_around = NewLIR1(kX86Jmp8, 0); 526 // The target for cmp/jmp above. 527 minint_branch->target = NewLIR0(kPseudoTargetLabel); 528 // EAX already contains the right value (0x80000000), 529 branch_around->target = NewLIR0(kPseudoTargetLabel); 530 } else { 531 // x % -1 == 0. 532 LoadConstantNoClobber(rs_r0, 0); 533 } 534 // For this case, return the result in EAX. 535 rl_result.reg.SetReg(r0); 536 } else { 537 CHECK(imm <= -2 || imm >= 2); 538 // Use H.S.Warren's Hacker's Delight Chapter 10 and 539 // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 540 int magic, shift; 541 CalculateMagicAndShift(imm, magic, shift); 542 543 /* 544 * For imm >= 2, 545 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 546 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. 547 * For imm <= -2, 548 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 549 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. 550 * We implement this algorithm in the following way: 551 * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX 552 * 2. if imm > 0 and magic < 0, add numerator to EDX 553 * if imm < 0 and magic > 0, sub numerator from EDX 554 * 3. if S !=0, SAR S bits for EDX 555 * 4. add 1 to EDX if EDX < 0 556 * 5. Thus, EDX is the quotient 557 */ 558 559 // Numerator into EAX. 560 RegStorage numerator_reg; 561 if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { 562 // We will need the value later. 563 if (rl_src.location == kLocPhysReg) { 564 // We can use it directly. 565 DCHECK(rl_src.reg.GetReg() != rs_r0.GetReg() && rl_src.reg.GetReg() != rs_r2.GetReg()); 566 numerator_reg = rl_src.reg; 567 } else { 568 numerator_reg = rs_r1; 569 LoadValueDirectFixed(rl_src, numerator_reg); 570 } 571 OpRegCopy(rs_r0, numerator_reg); 572 } else { 573 // Only need this once. Just put it into EAX. 574 LoadValueDirectFixed(rl_src, rs_r0); 575 } 576 577 // EDX = magic. 578 LoadConstantNoClobber(rs_r2, magic); 579 580 // EDX:EAX = magic & dividend. 581 NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); 582 583 if (imm > 0 && magic < 0) { 584 // Add numerator to EDX. 585 DCHECK(numerator_reg.Valid()); 586 NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 587 } else if (imm < 0 && magic > 0) { 588 DCHECK(numerator_reg.Valid()); 589 NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 590 } 591 592 // Do we need the shift? 593 if (shift != 0) { 594 // Shift EDX by 'shift' bits. 595 NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); 596 } 597 598 // Add 1 to EDX if EDX < 0. 599 600 // Move EDX to EAX. 601 OpRegCopy(rs_r0, rs_r2); 602 603 // Move sign bit to bit 0, zeroing the rest. 604 NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); 605 606 // EDX = EDX + EAX. 607 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); 608 609 // Quotient is in EDX. 610 if (!is_div) { 611 // We need to compute the remainder. 612 // Remainder is divisor - (quotient * imm). 613 DCHECK(numerator_reg.Valid()); 614 OpRegCopy(rs_r0, numerator_reg); 615 616 // EAX = numerator * imm. 617 OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); 618 619 // EDX -= EAX. 620 NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); 621 622 // For this case, return the result in EAX. 623 rl_result.reg.SetReg(r0); 624 } 625 } 626 627 return rl_result; 628} 629 630RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 631 bool is_div) { 632 LOG(FATAL) << "Unexpected use of GenDivRem for x86"; 633 return rl_dest; 634} 635 636RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 637 RegLocation rl_src2, bool is_div, bool check_zero) { 638 // We have to use fixed registers, so flush all the temps. 639 FlushAllRegs(); 640 LockCallTemps(); // Prepare for explicit register usage. 641 642 // Load LHS into EAX. 643 LoadValueDirectFixed(rl_src1, rs_r0); 644 645 // Load RHS into EBX. 646 LoadValueDirectFixed(rl_src2, rs_r1); 647 648 // Copy LHS sign bit into EDX. 649 NewLIR0(kx86Cdq32Da); 650 651 if (check_zero) { 652 // Handle division by zero case. 653 GenDivZeroCheck(rs_r1); 654 } 655 656 // Have to catch 0x80000000/-1 case, or we will get an exception! 657 OpRegImm(kOpCmp, rs_r1, -1); 658 LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 659 660 // RHS is -1. 661 OpRegImm(kOpCmp, rs_r0, 0x80000000); 662 LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 663 664 // In 0x80000000/-1 case. 665 if (!is_div) { 666 // For DIV, EAX is already right. For REM, we need EDX 0. 667 LoadConstantNoClobber(rs_r2, 0); 668 } 669 LIR* done = NewLIR1(kX86Jmp8, 0); 670 671 // Expected case. 672 minus_one_branch->target = NewLIR0(kPseudoTargetLabel); 673 minint_branch->target = minus_one_branch->target; 674 NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); 675 done->target = NewLIR0(kPseudoTargetLabel); 676 677 // Result is in EAX for div and EDX for rem. 678 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; 679 if (!is_div) { 680 rl_result.reg.SetReg(r2); 681 } 682 return rl_result; 683} 684 685bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { 686 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 687 688 // Get the two arguments to the invoke and place them in GP registers. 689 RegLocation rl_src1 = info->args[0]; 690 RegLocation rl_src2 = info->args[1]; 691 rl_src1 = LoadValue(rl_src1, kCoreReg); 692 rl_src2 = LoadValue(rl_src2, kCoreReg); 693 694 RegLocation rl_dest = InlineTarget(info); 695 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 696 697 /* 698 * If the result register is the same as the second element, then we need to be careful. 699 * The reason is that the first copy will inadvertently clobber the second element with 700 * the first one thus yielding the wrong result. Thus we do a swap in that case. 701 */ 702 if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 703 std::swap(rl_src1, rl_src2); 704 } 705 706 // Pick the first integer as min/max. 707 OpRegCopy(rl_result.reg, rl_src1.reg); 708 709 // If the integers are both in the same register, then there is nothing else to do 710 // because they are equal and we have already moved one into the result. 711 if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { 712 // It is possible we didn't pick correctly so do the actual comparison now. 713 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 714 715 // Conditionally move the other integer into the destination register. 716 ConditionCode condition_code = is_min ? kCondGt : kCondLt; 717 OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); 718 } 719 720 StoreValue(rl_dest, rl_result); 721 return true; 722} 723 724bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 725 RegLocation rl_src_address = info->args[0]; // long address 726 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 727 RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); 728 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 729 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 730 // Unaligned access is allowed on x86. 731 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size); 732 if (size == k64) { 733 StoreValueWide(rl_dest, rl_result); 734 } else { 735 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 736 StoreValue(rl_dest, rl_result); 737 } 738 return true; 739} 740 741bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 742 RegLocation rl_src_address = info->args[0]; // long address 743 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 744 RegLocation rl_src_value = info->args[2]; // [size] value 745 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 746 if (size == k64) { 747 // Unaligned access is allowed on x86. 748 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 749 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 750 } else { 751 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 752 // Unaligned access is allowed on x86. 753 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 754 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 755 } 756 return true; 757} 758 759void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { 760 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); 761} 762 763void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { 764 DCHECK_EQ(kX86, cu_->instruction_set); 765 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 766} 767 768void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { 769 DCHECK_EQ(kX86_64, cu_->instruction_set); 770 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 771} 772 773static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { 774 return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); 775} 776 777bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 778 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 779 // Unused - RegLocation rl_src_unsafe = info->args[0]; 780 RegLocation rl_src_obj = info->args[1]; // Object - known non-null 781 RegLocation rl_src_offset = info->args[2]; // long low 782 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 783 RegLocation rl_src_expected = info->args[4]; // int, long or Object 784 // If is_long, high half is in info->args[5] 785 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object 786 // If is_long, high half is in info->args[7] 787 788 if (is_long) { 789 // TODO: avoid unnecessary loads of SI and DI when the values are in registers. 790 // TODO: CFI support. 791 FlushAllRegs(); 792 LockCallTemps(); 793 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); 794 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); 795 LoadValueDirectWideFixed(rl_src_expected, r_tmp1); 796 LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); 797 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 798 MarkTemp(rs_rDI); 799 LockTemp(rs_rDI); 800 NewLIR1(kX86Push32R, rs_rSI.GetReg()); 801 MarkTemp(rs_rSI); 802 LockTemp(rs_rSI); 803 const int push_offset = 4 /* push edi */ + 4 /* push esi */; 804 int srcObjSp = IsInReg(this, rl_src_obj, rs_rSI) ? 0 805 : (IsInReg(this, rl_src_obj, rs_rDI) ? 4 806 : (SRegOffset(rl_src_obj.s_reg_low) + push_offset)); 807 // FIXME: needs 64-bit update. 808 LoadWordDisp(TargetReg(kSp), srcObjSp, rs_rDI); 809 int srcOffsetSp = IsInReg(this, rl_src_offset, rs_rSI) ? 0 810 : (IsInReg(this, rl_src_offset, rs_rDI) ? 4 811 : (SRegOffset(rl_src_offset.s_reg_low) + push_offset)); 812 LoadWordDisp(TargetReg(kSp), srcOffsetSp, rs_rSI); 813 NewLIR4(kX86LockCmpxchg64A, rs_rDI.GetReg(), rs_rSI.GetReg(), 0, 0); 814 815 // After a store we need to insert barrier in case of potential load. Since the 816 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 817 GenMemBarrier(kStoreLoad); 818 819 FreeTemp(rs_rSI); 820 UnmarkTemp(rs_rSI); 821 NewLIR1(kX86Pop32R, rs_rSI.GetReg()); 822 FreeTemp(rs_rDI); 823 UnmarkTemp(rs_rDI); 824 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 825 FreeCallTemps(); 826 } else { 827 // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. 828 FlushReg(rs_r0); 829 Clobber(rs_r0); 830 LockTemp(rs_r0); 831 832 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 833 RegLocation rl_new_value = LoadValue(rl_src_new_value); 834 835 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { 836 // Mark card for object assuming new value is stored. 837 FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). 838 MarkGCCard(rl_new_value.reg, rl_object.reg); 839 LockTemp(rs_r0); 840 } 841 842 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 843 LoadValueDirect(rl_src_expected, rs_r0); 844 NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, rl_new_value.reg.GetReg()); 845 846 // After a store we need to insert barrier in case of potential load. Since the 847 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 848 GenMemBarrier(kStoreLoad); 849 850 FreeTemp(rs_r0); 851 } 852 853 // Convert ZF to boolean 854 RegLocation rl_dest = InlineTarget(info); // boolean place for result 855 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 856 RegStorage result_reg = rl_result.reg; 857 858 // SETcc only works with EAX..EDX. 859 if (result_reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 860 result_reg = AllocateByteRegister(); 861 DCHECK_LT(result_reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 862 } 863 NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); 864 NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); 865 if (IsTemp(result_reg)) { 866 FreeTemp(result_reg); 867 } 868 StoreValue(rl_dest, rl_result); 869 return true; 870} 871 872LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { 873 CHECK(base_of_code_ != nullptr); 874 875 // Address the start of the method 876 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 877 if (rl_method.wide) { 878 LoadValueDirectWideFixed(rl_method, reg); 879 } else { 880 LoadValueDirectFixed(rl_method, reg); 881 } 882 store_method_addr_used_ = true; 883 884 // Load the proper value from the literal area. 885 // We don't know the proper offset for the value, so pick one that will force 886 // 4 byte offset. We will fix this up in the assembler later to have the right 887 // value. 888 LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, 889 0, 0, target); 890 res->target = target; 891 res->flags.fixup = kFixupLoad; 892 SetMemRefType(res, true, kLiteral); 893 store_method_addr_used_ = true; 894 return res; 895} 896 897LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { 898 LOG(FATAL) << "Unexpected use of OpVldm for x86"; 899 return NULL; 900} 901 902LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { 903 LOG(FATAL) << "Unexpected use of OpVstm for x86"; 904 return NULL; 905} 906 907void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 908 RegLocation rl_result, int lit, 909 int first_bit, int second_bit) { 910 RegStorage t_reg = AllocTemp(); 911 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); 912 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); 913 FreeTemp(t_reg); 914 if (first_bit != 0) { 915 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); 916 } 917} 918 919void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { 920 if (Gen64Bit()) { 921 DCHECK(reg.Is64Bit()); 922 923 NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); 924 } else { 925 DCHECK(reg.IsPair()); 926 927 // We are not supposed to clobber the incoming storage, so allocate a temporary. 928 RegStorage t_reg = AllocTemp(); 929 // Doing an OR is a quick way to check if both registers are zero. This will set the flags. 930 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); 931 // The temp is no longer needed so free it at this time. 932 FreeTemp(t_reg); 933 } 934 935 // In case of zero, throw ArithmeticException. 936 GenDivZeroCheck(kCondEq); 937} 938 939void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, 940 RegStorage array_base, 941 int len_offset) { 942 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 943 public: 944 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 945 RegStorage index, RegStorage array_base, int32_t len_offset) 946 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 947 index_(index), array_base_(array_base), len_offset_(len_offset) { 948 } 949 950 void Compile() OVERRIDE { 951 m2l_->ResetRegPool(); 952 m2l_->ResetDefTracking(); 953 GenerateTargetLabel(kPseudoThrowTarget); 954 955 RegStorage new_index = index_; 956 // Move index out of kArg1, either directly to kArg0, or to kArg2. 957 if (index_.GetReg() == m2l_->TargetReg(kArg1).GetReg()) { 958 if (array_base_.GetReg() == m2l_->TargetReg(kArg0).GetReg()) { 959 m2l_->OpRegCopy(m2l_->TargetReg(kArg2), index_); 960 new_index = m2l_->TargetReg(kArg2); 961 } else { 962 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), index_); 963 new_index = m2l_->TargetReg(kArg0); 964 } 965 } 966 // Load array length to kArg1. 967 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 968 if (Is64BitInstructionSet(cu_->instruction_set)) { 969 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 970 new_index, m2l_->TargetReg(kArg1), true); 971 } else { 972 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 973 new_index, m2l_->TargetReg(kArg1), true); 974 } 975 } 976 977 private: 978 const RegStorage index_; 979 const RegStorage array_base_; 980 const int32_t len_offset_; 981 }; 982 983 OpRegMem(kOpCmp, index, array_base, len_offset); 984 LIR* branch = OpCondBranch(kCondUge, nullptr); 985 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 986 index, array_base, len_offset)); 987} 988 989void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, 990 RegStorage array_base, 991 int32_t len_offset) { 992 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 993 public: 994 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 995 int32_t index, RegStorage array_base, int32_t len_offset) 996 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 997 index_(index), array_base_(array_base), len_offset_(len_offset) { 998 } 999 1000 void Compile() OVERRIDE { 1001 m2l_->ResetRegPool(); 1002 m2l_->ResetDefTracking(); 1003 GenerateTargetLabel(kPseudoThrowTarget); 1004 1005 // Load array length to kArg1. 1006 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 1007 m2l_->LoadConstant(m2l_->TargetReg(kArg0), index_); 1008 if (Is64BitInstructionSet(cu_->instruction_set)) { 1009 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 1010 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 1011 } else { 1012 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 1013 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 1014 } 1015 } 1016 1017 private: 1018 const int32_t index_; 1019 const RegStorage array_base_; 1020 const int32_t len_offset_; 1021 }; 1022 1023 NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); 1024 LIR* branch = OpCondBranch(kCondLs, nullptr); 1025 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 1026 index, array_base, len_offset)); 1027} 1028 1029// Test suspend flag, return target of taken suspend branch 1030LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { 1031 if (Is64BitInstructionSet(cu_->instruction_set)) { 1032 OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); 1033 } else { 1034 OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); 1035 } 1036 return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); 1037} 1038 1039// Decrement register and branch on condition 1040LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { 1041 OpRegImm(kOpSub, reg, 1); 1042 return OpCondBranch(c_code, target); 1043} 1044 1045bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1046 RegLocation rl_src, RegLocation rl_dest, int lit) { 1047 LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; 1048 return false; 1049} 1050 1051bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1052 LOG(FATAL) << "Unexpected use of easyMultiply in x86"; 1053 return false; 1054} 1055 1056LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { 1057 LOG(FATAL) << "Unexpected use of OpIT in x86"; 1058 return NULL; 1059} 1060 1061void X86Mir2Lir::OpEndIT(LIR* it) { 1062 LOG(FATAL) << "Unexpected use of OpEndIT in x86"; 1063} 1064 1065void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { 1066 switch (val) { 1067 case 0: 1068 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1069 break; 1070 case 1: 1071 OpRegCopy(dest, src); 1072 break; 1073 default: 1074 OpRegRegImm(kOpMul, dest, src, val); 1075 break; 1076 } 1077} 1078 1079void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { 1080 LIR *m; 1081 switch (val) { 1082 case 0: 1083 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1084 break; 1085 case 1: 1086 LoadBaseDisp(rs_rX86_SP, displacement, dest, k32); 1087 break; 1088 default: 1089 m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), 1090 rs_rX86_SP.GetReg(), displacement, val); 1091 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); 1092 break; 1093 } 1094} 1095 1096void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1097 RegLocation rl_src2) { 1098 if (Gen64Bit()) { 1099 if (rl_src1.is_const) { 1100 std::swap(rl_src1, rl_src2); 1101 } 1102 // Are we multiplying by a constant? 1103 if (rl_src2.is_const) { 1104 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1105 if (val == 0) { 1106 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1107 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); 1108 StoreValueWide(rl_dest, rl_result); 1109 return; 1110 } else if (val == 1) { 1111 StoreValueWide(rl_dest, rl_src1); 1112 return; 1113 } else if (val == 2) { 1114 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); 1115 return; 1116 } else if (IsPowerOfTwo(val)) { 1117 int shift_amount = LowestSetBit(val); 1118 if (!BadOverlap(rl_src1, rl_dest)) { 1119 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1120 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, 1121 rl_src1, shift_amount); 1122 StoreValueWide(rl_dest, rl_result); 1123 return; 1124 } 1125 } 1126 // Falltrhough to handle. 1127 } 1128 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1129 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1130 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1131 if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && 1132 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 1133 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); 1134 } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && 1135 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 1136 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); 1137 } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && 1138 rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { 1139 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1140 } else { 1141 OpRegCopy(rl_result.reg, rl_src1.reg); 1142 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1143 } 1144 StoreValueWide(rl_dest, rl_result); 1145 return; 1146 } 1147 1148 if (rl_src1.is_const) { 1149 std::swap(rl_src1, rl_src2); 1150 } 1151 // Are we multiplying by a constant? 1152 if (rl_src2.is_const) { 1153 // Do special compare/branch against simple const operand 1154 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1155 if (val == 0) { 1156 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1157 OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); 1158 OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); 1159 StoreValueWide(rl_dest, rl_result); 1160 return; 1161 } else if (val == 1) { 1162 StoreValueWide(rl_dest, rl_src1); 1163 return; 1164 } else if (val == 2) { 1165 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); 1166 return; 1167 } else if (IsPowerOfTwo(val)) { 1168 int shift_amount = LowestSetBit(val); 1169 if (!BadOverlap(rl_src1, rl_dest)) { 1170 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1171 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, 1172 rl_src1, shift_amount); 1173 StoreValueWide(rl_dest, rl_result); 1174 return; 1175 } 1176 } 1177 1178 // Okay, just bite the bullet and do it. 1179 int32_t val_lo = Low32Bits(val); 1180 int32_t val_hi = High32Bits(val); 1181 FlushAllRegs(); 1182 LockCallTemps(); // Prepare for explicit register usage. 1183 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1184 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1185 int displacement = SRegOffset(rl_src1.s_reg_low); 1186 1187 // ECX <- 1H * 2L 1188 // EAX <- 1L * 2H 1189 if (src1_in_reg) { 1190 GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); 1191 GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); 1192 } else { 1193 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); 1194 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); 1195 } 1196 1197 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1198 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1199 1200 // EAX <- 2L 1201 LoadConstantNoClobber(rs_r0, val_lo); 1202 1203 // EDX:EAX <- 2L * 1L (double precision) 1204 if (src1_in_reg) { 1205 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1206 } else { 1207 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1208 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1209 true /* is_load */, true /* is_64bit */); 1210 } 1211 1212 // EDX <- EDX + ECX (add high words) 1213 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1214 1215 // Result is EDX:EAX 1216 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1217 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1218 StoreValueWide(rl_dest, rl_result); 1219 return; 1220 } 1221 1222 // Nope. Do it the hard way 1223 // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. 1224 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == 1225 mir_graph_->SRegToVReg(rl_src2.s_reg_low); 1226 1227 FlushAllRegs(); 1228 LockCallTemps(); // Prepare for explicit register usage. 1229 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1230 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1231 1232 // At this point, the VRs are in their home locations. 1233 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1234 bool src2_in_reg = rl_src2.location == kLocPhysReg; 1235 1236 // ECX <- 1H 1237 if (src1_in_reg) { 1238 NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); 1239 } else { 1240 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32); 1241 } 1242 1243 if (is_square) { 1244 // Take advantage of the fact that the values are the same. 1245 // ECX <- ECX * 2L (1H * 2L) 1246 if (src2_in_reg) { 1247 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1248 } else { 1249 int displacement = SRegOffset(rl_src2.s_reg_low); 1250 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1251 displacement + LOWORD_OFFSET); 1252 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1253 true /* is_load */, true /* is_64bit */); 1254 } 1255 1256 // ECX <- 2*ECX (2H * 1L) + (1H * 2L) 1257 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); 1258 } else { 1259 // EAX <- 2H 1260 if (src2_in_reg) { 1261 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); 1262 } else { 1263 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32); 1264 } 1265 1266 // EAX <- EAX * 1L (2H * 1L) 1267 if (src1_in_reg) { 1268 NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); 1269 } else { 1270 int displacement = SRegOffset(rl_src1.s_reg_low); 1271 LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), 1272 displacement + LOWORD_OFFSET); 1273 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1274 true /* is_load */, true /* is_64bit */); 1275 } 1276 1277 // ECX <- ECX * 2L (1H * 2L) 1278 if (src2_in_reg) { 1279 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1280 } else { 1281 int displacement = SRegOffset(rl_src2.s_reg_low); 1282 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1283 displacement + LOWORD_OFFSET); 1284 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1285 true /* is_load */, true /* is_64bit */); 1286 } 1287 1288 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1289 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1290 } 1291 1292 // EAX <- 2L 1293 if (src2_in_reg) { 1294 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); 1295 } else { 1296 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32); 1297 } 1298 1299 // EDX:EAX <- 2L * 1L (double precision) 1300 if (src1_in_reg) { 1301 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1302 } else { 1303 int displacement = SRegOffset(rl_src1.s_reg_low); 1304 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1305 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1306 true /* is_load */, true /* is_64bit */); 1307 } 1308 1309 // EDX <- EDX + ECX (add high words) 1310 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1311 1312 // Result is EDX:EAX 1313 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1314 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1315 StoreValueWide(rl_dest, rl_result); 1316} 1317 1318void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, 1319 Instruction::Code op) { 1320 DCHECK_EQ(rl_dest.location, kLocPhysReg); 1321 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1322 if (rl_src.location == kLocPhysReg) { 1323 // Both operands are in registers. 1324 // But we must ensure that rl_src is in pair 1325 if (Gen64Bit()) { 1326 NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); 1327 } else { 1328 rl_src = LoadValueWide(rl_src, kCoreReg); 1329 if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1330 // The registers are the same, so we would clobber it before the use. 1331 RegStorage temp_reg = AllocTemp(); 1332 OpRegCopy(temp_reg, rl_dest.reg); 1333 rl_src.reg.SetHighReg(temp_reg.GetReg()); 1334 } 1335 NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); 1336 1337 x86op = GetOpcode(op, rl_dest, rl_src, true); 1338 NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); 1339 FreeTemp(rl_src.reg); // ??? 1340 } 1341 return; 1342 } 1343 1344 // RHS is in memory. 1345 DCHECK((rl_src.location == kLocDalvikFrame) || 1346 (rl_src.location == kLocCompilerTemp)); 1347 int r_base = TargetReg(kSp).GetReg(); 1348 int displacement = SRegOffset(rl_src.s_reg_low); 1349 1350 LIR *lir = NewLIR3(x86op, Gen64Bit() ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), r_base, displacement + LOWORD_OFFSET); 1351 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1352 true /* is_load */, true /* is64bit */); 1353 if (!Gen64Bit()) { 1354 x86op = GetOpcode(op, rl_dest, rl_src, true); 1355 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); 1356 } 1357 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1358 true /* is_load */, true /* is64bit */); 1359} 1360 1361void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 1362 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 1363 if (rl_dest.location == kLocPhysReg) { 1364 // Ensure we are in a register pair 1365 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1366 1367 rl_src = UpdateLocWideTyped(rl_src, kCoreReg); 1368 GenLongRegOrMemOp(rl_result, rl_src, op); 1369 StoreFinalValueWide(rl_dest, rl_result); 1370 return; 1371 } 1372 1373 // It wasn't in registers, so it better be in memory. 1374 DCHECK((rl_dest.location == kLocDalvikFrame) || 1375 (rl_dest.location == kLocCompilerTemp)); 1376 rl_src = LoadValueWide(rl_src, kCoreReg); 1377 1378 // Operate directly into memory. 1379 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1380 int r_base = TargetReg(kSp).GetReg(); 1381 int displacement = SRegOffset(rl_dest.s_reg_low); 1382 1383 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, 1384 Gen64Bit() ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); 1385 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1386 true /* is_load */, true /* is64bit */); 1387 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1388 false /* is_load */, true /* is64bit */); 1389 if (!Gen64Bit()) { 1390 x86op = GetOpcode(op, rl_dest, rl_src, true); 1391 lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); 1392 } 1393 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1394 true /* is_load */, true /* is64bit */); 1395 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1396 false /* is_load */, true /* is64bit */); 1397 FreeTemp(rl_src.reg); 1398} 1399 1400void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, 1401 RegLocation rl_src2, Instruction::Code op, 1402 bool is_commutative) { 1403 // Is this really a 2 operand operation? 1404 switch (op) { 1405 case Instruction::ADD_LONG_2ADDR: 1406 case Instruction::SUB_LONG_2ADDR: 1407 case Instruction::AND_LONG_2ADDR: 1408 case Instruction::OR_LONG_2ADDR: 1409 case Instruction::XOR_LONG_2ADDR: 1410 if (GenerateTwoOperandInstructions()) { 1411 GenLongArith(rl_dest, rl_src2, op); 1412 return; 1413 } 1414 break; 1415 1416 default: 1417 break; 1418 } 1419 1420 if (rl_dest.location == kLocPhysReg) { 1421 RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); 1422 1423 // We are about to clobber the LHS, so it needs to be a temp. 1424 rl_result = ForceTempWide(rl_result); 1425 1426 // Perform the operation using the RHS. 1427 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1428 GenLongRegOrMemOp(rl_result, rl_src2, op); 1429 1430 // And now record that the result is in the temp. 1431 StoreFinalValueWide(rl_dest, rl_result); 1432 return; 1433 } 1434 1435 // It wasn't in registers, so it better be in memory. 1436 DCHECK((rl_dest.location == kLocDalvikFrame) || 1437 (rl_dest.location == kLocCompilerTemp)); 1438 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1439 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1440 1441 // Get one of the source operands into temporary register. 1442 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1443 if (Gen64Bit()) { 1444 if (IsTemp(rl_src1.reg)) { 1445 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1446 } else if (is_commutative) { 1447 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1448 // We need at least one of them to be a temporary. 1449 if (!IsTemp(rl_src2.reg)) { 1450 rl_src1 = ForceTempWide(rl_src1); 1451 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1452 } else { 1453 GenLongRegOrMemOp(rl_src2, rl_src1, op); 1454 StoreFinalValueWide(rl_dest, rl_src2); 1455 return; 1456 } 1457 } else { 1458 // Need LHS to be the temp. 1459 rl_src1 = ForceTempWide(rl_src1); 1460 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1461 } 1462 } else { 1463 if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { 1464 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1465 } else if (is_commutative) { 1466 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1467 // We need at least one of them to be a temporary. 1468 if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { 1469 rl_src1 = ForceTempWide(rl_src1); 1470 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1471 } else { 1472 GenLongRegOrMemOp(rl_src2, rl_src1, op); 1473 StoreFinalValueWide(rl_dest, rl_src2); 1474 return; 1475 } 1476 } else { 1477 // Need LHS to be the temp. 1478 rl_src1 = ForceTempWide(rl_src1); 1479 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1480 } 1481 } 1482 1483 StoreFinalValueWide(rl_dest, rl_src1); 1484} 1485 1486void X86Mir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, 1487 RegLocation rl_src1, RegLocation rl_src2) { 1488 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1489} 1490 1491void X86Mir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, 1492 RegLocation rl_src1, RegLocation rl_src2) { 1493 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); 1494} 1495 1496void X86Mir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, 1497 RegLocation rl_src1, RegLocation rl_src2) { 1498 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1499} 1500 1501void X86Mir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, 1502 RegLocation rl_src1, RegLocation rl_src2) { 1503 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1504} 1505 1506void X86Mir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, 1507 RegLocation rl_src1, RegLocation rl_src2) { 1508 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1509} 1510 1511void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { 1512 if (Gen64Bit()) { 1513 rl_src = LoadValueWide(rl_src, kCoreReg); 1514 RegLocation rl_result; 1515 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1516 OpRegCopy(rl_result.reg, rl_src.reg); 1517 OpReg(kOpNot, rl_result.reg); 1518 StoreValueWide(rl_dest, rl_result); 1519 } else { 1520 LOG(FATAL) << "Unexpected use GenNotLong()"; 1521 } 1522} 1523 1524void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1525 RegLocation rl_src2, bool is_div) { 1526 if (!Gen64Bit()) { 1527 LOG(FATAL) << "Unexpected use GenDivRemLong()"; 1528 return; 1529 } 1530 1531 // We have to use fixed registers, so flush all the temps. 1532 FlushAllRegs(); 1533 LockCallTemps(); // Prepare for explicit register usage. 1534 1535 // Load LHS into RAX. 1536 LoadValueDirectWideFixed(rl_src1, rs_r0q); 1537 1538 // Load RHS into RCX. 1539 LoadValueDirectWideFixed(rl_src2, rs_r1q); 1540 1541 // Copy LHS sign bit into RDX. 1542 NewLIR0(kx86Cqo64Da); 1543 1544 // Handle division by zero case. 1545 GenDivZeroCheckWide(rs_r1q); 1546 1547 // Have to catch 0x8000000000000000/-1 case, or we will get an exception! 1548 NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); 1549 LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 1550 1551 // RHS is -1. 1552 LoadConstantWide(rs_r3q, 0x8000000000000000); 1553 NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r3q.GetReg()); 1554 LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 1555 1556 // In 0x8000000000000000/-1 case. 1557 if (!is_div) { 1558 // For DIV, RAX is already right. For REM, we need RDX 0. 1559 NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); 1560 } 1561 LIR* done = NewLIR1(kX86Jmp8, 0); 1562 1563 // Expected case. 1564 minus_one_branch->target = NewLIR0(kPseudoTargetLabel); 1565 minint_branch->target = minus_one_branch->target; 1566 NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); 1567 done->target = NewLIR0(kPseudoTargetLabel); 1568 1569 // Result is in RAX for div and RDX for rem. 1570 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; 1571 if (!is_div) { 1572 rl_result.reg.SetReg(r2q); 1573 } 1574 1575 StoreValueWide(rl_dest, rl_result); 1576} 1577 1578void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 1579 rl_src = LoadValueWide(rl_src, kCoreReg); 1580 RegLocation rl_result; 1581 if (Gen64Bit()) { 1582 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1583 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1584 } else { 1585 rl_result = ForceTempWide(rl_src); 1586 if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && 1587 ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { 1588 // The registers are the same, so we would clobber it before the use. 1589 RegStorage temp_reg = AllocTemp(); 1590 OpRegCopy(temp_reg, rl_result.reg); 1591 rl_result.reg.SetHighReg(temp_reg.GetReg()); 1592 } 1593 OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow 1594 OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF 1595 OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh 1596 } 1597 StoreValueWide(rl_dest, rl_result); 1598} 1599 1600void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { 1601 DCHECK_EQ(kX86, cu_->instruction_set); 1602 X86OpCode opcode = kX86Bkpt; 1603 switch (op) { 1604 case kOpCmp: opcode = kX86Cmp32RT; break; 1605 case kOpMov: opcode = kX86Mov32RT; break; 1606 default: 1607 LOG(FATAL) << "Bad opcode: " << op; 1608 break; 1609 } 1610 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1611} 1612 1613void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { 1614 DCHECK_EQ(kX86_64, cu_->instruction_set); 1615 X86OpCode opcode = kX86Bkpt; 1616 if (Gen64Bit() && r_dest.Is64BitSolo()) { 1617 switch (op) { 1618 case kOpCmp: opcode = kX86Cmp64RT; break; 1619 case kOpMov: opcode = kX86Mov64RT; break; 1620 default: 1621 LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; 1622 break; 1623 } 1624 } else { 1625 switch (op) { 1626 case kOpCmp: opcode = kX86Cmp32RT; break; 1627 case kOpMov: opcode = kX86Mov32RT; break; 1628 default: 1629 LOG(FATAL) << "Bad opcode: " << op; 1630 break; 1631 } 1632 } 1633 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1634} 1635 1636/* 1637 * Generate array load 1638 */ 1639void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1640 RegLocation rl_index, RegLocation rl_dest, int scale) { 1641 RegisterClass reg_class = RegClassBySize(size); 1642 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1643 RegLocation rl_result; 1644 rl_array = LoadValue(rl_array, kRefReg); 1645 1646 int data_offset; 1647 if (size == k64 || size == kDouble) { 1648 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1649 } else { 1650 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1651 } 1652 1653 bool constant_index = rl_index.is_const; 1654 int32_t constant_index_value = 0; 1655 if (!constant_index) { 1656 rl_index = LoadValue(rl_index, kCoreReg); 1657 } else { 1658 constant_index_value = mir_graph_->ConstantValue(rl_index); 1659 // If index is constant, just fold it into the data offset 1660 data_offset += constant_index_value << scale; 1661 // treat as non array below 1662 rl_index.reg = RegStorage::InvalidReg(); 1663 } 1664 1665 /* null object? */ 1666 GenNullCheck(rl_array.reg, opt_flags); 1667 1668 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1669 if (constant_index) { 1670 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1671 } else { 1672 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1673 } 1674 } 1675 rl_result = EvalLoc(rl_dest, reg_class, true); 1676 LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); 1677 if ((size == k64) || (size == kDouble)) { 1678 StoreValueWide(rl_dest, rl_result); 1679 } else { 1680 StoreValue(rl_dest, rl_result); 1681 } 1682} 1683 1684/* 1685 * Generate array store 1686 * 1687 */ 1688void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1689 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1690 RegisterClass reg_class = RegClassBySize(size); 1691 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1692 int data_offset; 1693 1694 if (size == k64 || size == kDouble) { 1695 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1696 } else { 1697 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1698 } 1699 1700 rl_array = LoadValue(rl_array, kRefReg); 1701 bool constant_index = rl_index.is_const; 1702 int32_t constant_index_value = 0; 1703 if (!constant_index) { 1704 rl_index = LoadValue(rl_index, kCoreReg); 1705 } else { 1706 // If index is constant, just fold it into the data offset 1707 constant_index_value = mir_graph_->ConstantValue(rl_index); 1708 data_offset += constant_index_value << scale; 1709 // treat as non array below 1710 rl_index.reg = RegStorage::InvalidReg(); 1711 } 1712 1713 /* null object? */ 1714 GenNullCheck(rl_array.reg, opt_flags); 1715 1716 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1717 if (constant_index) { 1718 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1719 } else { 1720 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1721 } 1722 } 1723 if ((size == k64) || (size == kDouble)) { 1724 rl_src = LoadValueWide(rl_src, reg_class); 1725 } else { 1726 rl_src = LoadValue(rl_src, reg_class); 1727 } 1728 // If the src reg can't be byte accessed, move it to a temp first. 1729 if ((size == kSignedByte || size == kUnsignedByte) && 1730 rl_src.reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 1731 RegStorage temp = AllocTemp(); 1732 OpRegCopy(temp, rl_src.reg); 1733 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); 1734 } else { 1735 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); 1736 } 1737 if (card_mark) { 1738 // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. 1739 if (!constant_index) { 1740 FreeTemp(rl_index.reg); 1741 } 1742 MarkGCCard(rl_src.reg, rl_array.reg); 1743 } 1744} 1745 1746RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1747 RegLocation rl_src, int shift_amount) { 1748 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1749 if (Gen64Bit()) { 1750 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1751 switch (opcode) { 1752 case Instruction::SHL_LONG: 1753 case Instruction::SHL_LONG_2ADDR: 1754 op = kOpLsl; 1755 break; 1756 case Instruction::SHR_LONG: 1757 case Instruction::SHR_LONG_2ADDR: 1758 op = kOpAsr; 1759 break; 1760 case Instruction::USHR_LONG: 1761 case Instruction::USHR_LONG_2ADDR: 1762 op = kOpLsr; 1763 break; 1764 default: 1765 LOG(FATAL) << "Unexpected case"; 1766 } 1767 OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); 1768 } else { 1769 switch (opcode) { 1770 case Instruction::SHL_LONG: 1771 case Instruction::SHL_LONG_2ADDR: 1772 DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. 1773 if (shift_amount == 32) { 1774 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1775 LoadConstant(rl_result.reg.GetLow(), 0); 1776 } else if (shift_amount > 31) { 1777 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1778 NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); 1779 LoadConstant(rl_result.reg.GetLow(), 0); 1780 } else { 1781 OpRegCopy(rl_result.reg, rl_src.reg); 1782 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1783 NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), 1784 shift_amount); 1785 NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); 1786 } 1787 break; 1788 case Instruction::SHR_LONG: 1789 case Instruction::SHR_LONG_2ADDR: 1790 if (shift_amount == 32) { 1791 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1792 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1793 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1794 } else if (shift_amount > 31) { 1795 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1796 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1797 NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1798 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1799 } else { 1800 OpRegCopy(rl_result.reg, rl_src.reg); 1801 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1802 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), 1803 shift_amount); 1804 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); 1805 } 1806 break; 1807 case Instruction::USHR_LONG: 1808 case Instruction::USHR_LONG_2ADDR: 1809 if (shift_amount == 32) { 1810 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1811 LoadConstant(rl_result.reg.GetHigh(), 0); 1812 } else if (shift_amount > 31) { 1813 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1814 NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1815 LoadConstant(rl_result.reg.GetHigh(), 0); 1816 } else { 1817 OpRegCopy(rl_result.reg, rl_src.reg); 1818 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1819 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), 1820 shift_amount); 1821 NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); 1822 } 1823 break; 1824 default: 1825 LOG(FATAL) << "Unexpected case"; 1826 } 1827 } 1828 return rl_result; 1829} 1830 1831void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1832 RegLocation rl_src, RegLocation rl_shift) { 1833 // Per spec, we only care about low 6 bits of shift amount. 1834 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; 1835 if (shift_amount == 0) { 1836 rl_src = LoadValueWide(rl_src, kCoreReg); 1837 StoreValueWide(rl_dest, rl_src); 1838 return; 1839 } else if (shift_amount == 1 && 1840 (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { 1841 // Need to handle this here to avoid calling StoreValueWide twice. 1842 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); 1843 return; 1844 } 1845 if (BadOverlap(rl_src, rl_dest)) { 1846 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); 1847 return; 1848 } 1849 rl_src = LoadValueWide(rl_src, kCoreReg); 1850 RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); 1851 StoreValueWide(rl_dest, rl_result); 1852} 1853 1854void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, 1855 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1856 bool isConstSuccess = false; 1857 switch (opcode) { 1858 case Instruction::ADD_LONG: 1859 case Instruction::AND_LONG: 1860 case Instruction::OR_LONG: 1861 case Instruction::XOR_LONG: 1862 if (rl_src2.is_const) { 1863 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1864 } else { 1865 DCHECK(rl_src1.is_const); 1866 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1867 } 1868 break; 1869 case Instruction::SUB_LONG: 1870 case Instruction::SUB_LONG_2ADDR: 1871 if (rl_src2.is_const) { 1872 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1873 } else { 1874 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1875 isConstSuccess = true; 1876 } 1877 break; 1878 case Instruction::ADD_LONG_2ADDR: 1879 case Instruction::OR_LONG_2ADDR: 1880 case Instruction::XOR_LONG_2ADDR: 1881 case Instruction::AND_LONG_2ADDR: 1882 if (rl_src2.is_const) { 1883 if (GenerateTwoOperandInstructions()) { 1884 isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); 1885 } else { 1886 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1887 } 1888 } else { 1889 DCHECK(rl_src1.is_const); 1890 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1891 } 1892 break; 1893 default: 1894 isConstSuccess = false; 1895 break; 1896 } 1897 1898 if (!isConstSuccess) { 1899 // Default - bail to non-const handler. 1900 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1901 } 1902} 1903 1904bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { 1905 switch (op) { 1906 case Instruction::AND_LONG_2ADDR: 1907 case Instruction::AND_LONG: 1908 return value == -1; 1909 case Instruction::OR_LONG: 1910 case Instruction::OR_LONG_2ADDR: 1911 case Instruction::XOR_LONG: 1912 case Instruction::XOR_LONG_2ADDR: 1913 return value == 0; 1914 default: 1915 return false; 1916 } 1917} 1918 1919X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 1920 bool is_high_op) { 1921 bool rhs_in_mem = rhs.location != kLocPhysReg; 1922 bool dest_in_mem = dest.location != kLocPhysReg; 1923 bool is64Bit = Gen64Bit(); 1924 DCHECK(!rhs_in_mem || !dest_in_mem); 1925 switch (op) { 1926 case Instruction::ADD_LONG: 1927 case Instruction::ADD_LONG_2ADDR: 1928 if (dest_in_mem) { 1929 return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; 1930 } else if (rhs_in_mem) { 1931 return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; 1932 } 1933 return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; 1934 case Instruction::SUB_LONG: 1935 case Instruction::SUB_LONG_2ADDR: 1936 if (dest_in_mem) { 1937 return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; 1938 } else if (rhs_in_mem) { 1939 return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; 1940 } 1941 return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; 1942 case Instruction::AND_LONG_2ADDR: 1943 case Instruction::AND_LONG: 1944 if (dest_in_mem) { 1945 return is64Bit ? kX86And64MR : kX86And32MR; 1946 } 1947 if (is64Bit) { 1948 return rhs_in_mem ? kX86And64RM : kX86And64RR; 1949 } 1950 return rhs_in_mem ? kX86And32RM : kX86And32RR; 1951 case Instruction::OR_LONG: 1952 case Instruction::OR_LONG_2ADDR: 1953 if (dest_in_mem) { 1954 return is64Bit ? kX86Or64MR : kX86Or32MR; 1955 } 1956 if (is64Bit) { 1957 return rhs_in_mem ? kX86Or64RM : kX86Or64RR; 1958 } 1959 return rhs_in_mem ? kX86Or32RM : kX86Or32RR; 1960 case Instruction::XOR_LONG: 1961 case Instruction::XOR_LONG_2ADDR: 1962 if (dest_in_mem) { 1963 return is64Bit ? kX86Xor64MR : kX86Xor32MR; 1964 } 1965 if (is64Bit) { 1966 return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; 1967 } 1968 return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; 1969 default: 1970 LOG(FATAL) << "Unexpected opcode: " << op; 1971 return kX86Add32RR; 1972 } 1973} 1974 1975X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, 1976 int32_t value) { 1977 bool in_mem = loc.location != kLocPhysReg; 1978 bool is64Bit = Gen64Bit(); 1979 bool byte_imm = IS_SIMM8(value); 1980 DCHECK(in_mem || !loc.reg.IsFloat()); 1981 switch (op) { 1982 case Instruction::ADD_LONG: 1983 case Instruction::ADD_LONG_2ADDR: 1984 if (byte_imm) { 1985 if (in_mem) { 1986 return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; 1987 } 1988 return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; 1989 } 1990 if (in_mem) { 1991 return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; 1992 } 1993 return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; 1994 case Instruction::SUB_LONG: 1995 case Instruction::SUB_LONG_2ADDR: 1996 if (byte_imm) { 1997 if (in_mem) { 1998 return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; 1999 } 2000 return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; 2001 } 2002 if (in_mem) { 2003 return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; 2004 } 2005 return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; 2006 case Instruction::AND_LONG_2ADDR: 2007 case Instruction::AND_LONG: 2008 if (byte_imm) { 2009 if (is64Bit) { 2010 return in_mem ? kX86And64MI8 : kX86And64RI8; 2011 } 2012 return in_mem ? kX86And32MI8 : kX86And32RI8; 2013 } 2014 if (is64Bit) { 2015 return in_mem ? kX86And64MI : kX86And64RI; 2016 } 2017 return in_mem ? kX86And32MI : kX86And32RI; 2018 case Instruction::OR_LONG: 2019 case Instruction::OR_LONG_2ADDR: 2020 if (byte_imm) { 2021 if (is64Bit) { 2022 return in_mem ? kX86Or64MI8 : kX86Or64RI8; 2023 } 2024 return in_mem ? kX86Or32MI8 : kX86Or32RI8; 2025 } 2026 if (is64Bit) { 2027 return in_mem ? kX86Or64MI : kX86Or64RI; 2028 } 2029 return in_mem ? kX86Or32MI : kX86Or32RI; 2030 case Instruction::XOR_LONG: 2031 case Instruction::XOR_LONG_2ADDR: 2032 if (byte_imm) { 2033 if (is64Bit) { 2034 return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; 2035 } 2036 return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; 2037 } 2038 if (is64Bit) { 2039 return in_mem ? kX86Xor64MI : kX86Xor64RI; 2040 } 2041 return in_mem ? kX86Xor32MI : kX86Xor32RI; 2042 default: 2043 LOG(FATAL) << "Unexpected opcode: " << op; 2044 return kX86Add32MI; 2045 } 2046} 2047 2048bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 2049 DCHECK(rl_src.is_const); 2050 int64_t val = mir_graph_->ConstantValueWide(rl_src); 2051 2052 if (Gen64Bit()) { 2053 // We can do with imm only if it fits 32 bit 2054 if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { 2055 return false; 2056 } 2057 2058 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2059 2060 if ((rl_dest.location == kLocDalvikFrame) || 2061 (rl_dest.location == kLocCompilerTemp)) { 2062 int r_base = TargetReg(kSp).GetReg(); 2063 int displacement = SRegOffset(rl_dest.s_reg_low); 2064 2065 X86OpCode x86op = GetOpcode(op, rl_dest, false, val); 2066 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); 2067 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2068 true /* is_load */, true /* is64bit */); 2069 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2070 false /* is_load */, true /* is64bit */); 2071 return true; 2072 } 2073 2074 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2075 DCHECK_EQ(rl_result.location, kLocPhysReg); 2076 DCHECK(!rl_result.reg.IsFloat()); 2077 2078 X86OpCode x86op = GetOpcode(op, rl_result, false, val); 2079 NewLIR2(x86op, rl_result.reg.GetReg(), val); 2080 2081 StoreValueWide(rl_dest, rl_result); 2082 return true; 2083 } 2084 2085 int32_t val_lo = Low32Bits(val); 2086 int32_t val_hi = High32Bits(val); 2087 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2088 2089 // Can we just do this into memory? 2090 if ((rl_dest.location == kLocDalvikFrame) || 2091 (rl_dest.location == kLocCompilerTemp)) { 2092 int r_base = TargetReg(kSp).GetReg(); 2093 int displacement = SRegOffset(rl_dest.s_reg_low); 2094 2095 if (!IsNoOp(op, val_lo)) { 2096 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 2097 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); 2098 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2099 true /* is_load */, true /* is64bit */); 2100 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2101 false /* is_load */, true /* is64bit */); 2102 } 2103 if (!IsNoOp(op, val_hi)) { 2104 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 2105 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); 2106 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 2107 true /* is_load */, true /* is64bit */); 2108 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 2109 false /* is_load */, true /* is64bit */); 2110 } 2111 return true; 2112 } 2113 2114 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2115 DCHECK_EQ(rl_result.location, kLocPhysReg); 2116 DCHECK(!rl_result.reg.IsFloat()); 2117 2118 if (!IsNoOp(op, val_lo)) { 2119 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 2120 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 2121 } 2122 if (!IsNoOp(op, val_hi)) { 2123 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 2124 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 2125 } 2126 StoreValueWide(rl_dest, rl_result); 2127 return true; 2128} 2129 2130bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, 2131 RegLocation rl_src2, Instruction::Code op) { 2132 DCHECK(rl_src2.is_const); 2133 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 2134 2135 if (Gen64Bit()) { 2136 // We can do with imm only if it fits 32 bit 2137 if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { 2138 return false; 2139 } 2140 if (rl_dest.location == kLocPhysReg && 2141 rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { 2142 X86OpCode x86op = GetOpcode(op, rl_dest, false, val); 2143 NewLIR2(x86op, rl_dest.reg.GetReg(), val); 2144 StoreFinalValueWide(rl_dest, rl_dest); 2145 return true; 2146 } 2147 2148 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2149 // We need the values to be in a temporary 2150 RegLocation rl_result = ForceTempWide(rl_src1); 2151 2152 X86OpCode x86op = GetOpcode(op, rl_result, false, val); 2153 NewLIR2(x86op, rl_result.reg.GetReg(), val); 2154 2155 StoreFinalValueWide(rl_dest, rl_result); 2156 return true; 2157 } 2158 2159 int32_t val_lo = Low32Bits(val); 2160 int32_t val_hi = High32Bits(val); 2161 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2162 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 2163 2164 // Can we do this directly into the destination registers? 2165 if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && 2166 rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && 2167 rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { 2168 if (!IsNoOp(op, val_lo)) { 2169 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 2170 NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); 2171 } 2172 if (!IsNoOp(op, val_hi)) { 2173 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 2174 NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); 2175 } 2176 2177 StoreFinalValueWide(rl_dest, rl_dest); 2178 return true; 2179 } 2180 2181 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2182 DCHECK_EQ(rl_src1.location, kLocPhysReg); 2183 2184 // We need the values to be in a temporary 2185 RegLocation rl_result = ForceTempWide(rl_src1); 2186 if (!IsNoOp(op, val_lo)) { 2187 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 2188 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 2189 } 2190 if (!IsNoOp(op, val_hi)) { 2191 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 2192 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 2193 } 2194 2195 StoreFinalValueWide(rl_dest, rl_result); 2196 return true; 2197} 2198 2199// For final classes there are no sub-classes to check and so we can answer the instance-of 2200// question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. 2201void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 2202 RegLocation rl_dest, RegLocation rl_src) { 2203 RegLocation object = LoadValue(rl_src, kRefReg); 2204 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 2205 RegStorage result_reg = rl_result.reg; 2206 2207 // SETcc only works with EAX..EDX. 2208 if (result_reg == object.reg || result_reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 2209 result_reg = AllocateByteRegister(); 2210 DCHECK_LT(result_reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 2211 } 2212 2213 // Assume that there is no match. 2214 LoadConstant(result_reg, 0); 2215 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 2216 2217 // We will use this register to compare to memory below. 2218 // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). 2219 // For this reason, force allocation of a 32 bit register to use, so that the 2220 // compare to memory will be done using a 32 bit comparision. 2221 // The LoadRefDisp(s) below will work normally, even in 64 bit mode. 2222 RegStorage check_class = AllocTemp(); 2223 2224 // If Method* is already in a register, we can save a copy. 2225 RegLocation rl_method = mir_graph_->GetMethodLoc(); 2226 int32_t offset_of_type = mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 2227 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 2228 2229 if (rl_method.location == kLocPhysReg) { 2230 if (use_declaring_class) { 2231 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2232 check_class); 2233 } else { 2234 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2235 check_class); 2236 LoadRefDisp(check_class, offset_of_type, check_class); 2237 } 2238 } else { 2239 LoadCurrMethodDirect(check_class); 2240 if (use_declaring_class) { 2241 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2242 check_class); 2243 } else { 2244 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2245 check_class); 2246 LoadRefDisp(check_class, offset_of_type, check_class); 2247 } 2248 } 2249 2250 // Compare the computed class to the class in the object. 2251 DCHECK_EQ(object.location, kLocPhysReg); 2252 OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); 2253 2254 // Set the low byte of the result to 0 or 1 from the compare condition code. 2255 NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); 2256 2257 LIR* target = NewLIR0(kPseudoTargetLabel); 2258 null_branchover->target = target; 2259 FreeTemp(check_class); 2260 if (IsTemp(result_reg)) { 2261 OpRegCopy(rl_result.reg, result_reg); 2262 FreeTemp(result_reg); 2263 } 2264 StoreValue(rl_dest, rl_result); 2265} 2266 2267void X86Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 2268 bool type_known_abstract, bool use_declaring_class, 2269 bool can_assume_type_is_in_dex_cache, 2270 uint32_t type_idx, RegLocation rl_dest, 2271 RegLocation rl_src) { 2272 FlushAllRegs(); 2273 // May generate a call - use explicit registers. 2274 LockCallTemps(); 2275 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 gets current Method*. 2276 RegStorage class_reg = TargetReg(kArg2); // kArg2 will hold the Class*. 2277 // Reference must end up in kArg0. 2278 if (needs_access_check) { 2279 // Check we have access to type_idx and if not throw IllegalAccessError, 2280 // Caller function returns Class* in kArg0. 2281 if (Is64BitInstructionSet(cu_->instruction_set)) { 2282 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 2283 type_idx, true); 2284 } else { 2285 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 2286 type_idx, true); 2287 } 2288 OpRegCopy(class_reg, TargetReg(kRet0)); 2289 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2290 } else if (use_declaring_class) { 2291 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2292 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2293 class_reg); 2294 } else { 2295 // Load dex cache entry into class_reg (kArg2). 2296 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2297 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2298 class_reg); 2299 int32_t offset_of_type = 2300 mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 2301 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 2302 LoadRefDisp(class_reg, offset_of_type, class_reg); 2303 if (!can_assume_type_is_in_dex_cache) { 2304 // Need to test presence of type in dex cache at runtime. 2305 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 2306 // Type is not resolved. Call out to helper, which will return resolved type in kRet0/kArg0. 2307 if (Is64BitInstructionSet(cu_->instruction_set)) { 2308 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx, true); 2309 } else { 2310 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); 2311 } 2312 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path. 2313 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* Reload Ref. */ 2314 // Rejoin code paths 2315 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 2316 hop_branch->target = hop_target; 2317 } 2318 } 2319 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result. */ 2320 RegLocation rl_result = GetReturn(kRefReg); 2321 2322 // SETcc only works with EAX..EDX. 2323 DCHECK_LT(rl_result.reg.GetRegNum(), 4); 2324 2325 // Is the class NULL? 2326 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 2327 2328 /* Load object->klass_. */ 2329 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 2330 LoadRefDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 2331 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class. */ 2332 LIR* branchover = nullptr; 2333 if (type_known_final) { 2334 // Ensure top 3 bytes of result are 0. 2335 LoadConstant(rl_result.reg, 0); 2336 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); 2337 // Set the low byte of the result to 0 or 1 from the compare condition code. 2338 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondEq); 2339 } else { 2340 if (!type_known_abstract) { 2341 LoadConstant(rl_result.reg, 1); // Assume result succeeds. 2342 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 2343 } 2344 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 2345 if (Is64BitInstructionSet(cu_->instruction_set)) { 2346 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)); 2347 } else { 2348 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 2349 } 2350 } 2351 // TODO: only clobber when type isn't final? 2352 ClobberCallerSave(); 2353 /* Branch targets here. */ 2354 LIR* target = NewLIR0(kPseudoTargetLabel); 2355 StoreValue(rl_dest, rl_result); 2356 branch1->target = target; 2357 if (branchover != nullptr) { 2358 branchover->target = target; 2359 } 2360} 2361 2362void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 2363 RegLocation rl_lhs, RegLocation rl_rhs) { 2364 OpKind op = kOpBkpt; 2365 bool is_div_rem = false; 2366 bool unary = false; 2367 bool shift_op = false; 2368 bool is_two_addr = false; 2369 RegLocation rl_result; 2370 switch (opcode) { 2371 case Instruction::NEG_INT: 2372 op = kOpNeg; 2373 unary = true; 2374 break; 2375 case Instruction::NOT_INT: 2376 op = kOpMvn; 2377 unary = true; 2378 break; 2379 case Instruction::ADD_INT_2ADDR: 2380 is_two_addr = true; 2381 // Fallthrough 2382 case Instruction::ADD_INT: 2383 op = kOpAdd; 2384 break; 2385 case Instruction::SUB_INT_2ADDR: 2386 is_two_addr = true; 2387 // Fallthrough 2388 case Instruction::SUB_INT: 2389 op = kOpSub; 2390 break; 2391 case Instruction::MUL_INT_2ADDR: 2392 is_two_addr = true; 2393 // Fallthrough 2394 case Instruction::MUL_INT: 2395 op = kOpMul; 2396 break; 2397 case Instruction::DIV_INT_2ADDR: 2398 is_two_addr = true; 2399 // Fallthrough 2400 case Instruction::DIV_INT: 2401 op = kOpDiv; 2402 is_div_rem = true; 2403 break; 2404 /* NOTE: returns in kArg1 */ 2405 case Instruction::REM_INT_2ADDR: 2406 is_two_addr = true; 2407 // Fallthrough 2408 case Instruction::REM_INT: 2409 op = kOpRem; 2410 is_div_rem = true; 2411 break; 2412 case Instruction::AND_INT_2ADDR: 2413 is_two_addr = true; 2414 // Fallthrough 2415 case Instruction::AND_INT: 2416 op = kOpAnd; 2417 break; 2418 case Instruction::OR_INT_2ADDR: 2419 is_two_addr = true; 2420 // Fallthrough 2421 case Instruction::OR_INT: 2422 op = kOpOr; 2423 break; 2424 case Instruction::XOR_INT_2ADDR: 2425 is_two_addr = true; 2426 // Fallthrough 2427 case Instruction::XOR_INT: 2428 op = kOpXor; 2429 break; 2430 case Instruction::SHL_INT_2ADDR: 2431 is_two_addr = true; 2432 // Fallthrough 2433 case Instruction::SHL_INT: 2434 shift_op = true; 2435 op = kOpLsl; 2436 break; 2437 case Instruction::SHR_INT_2ADDR: 2438 is_two_addr = true; 2439 // Fallthrough 2440 case Instruction::SHR_INT: 2441 shift_op = true; 2442 op = kOpAsr; 2443 break; 2444 case Instruction::USHR_INT_2ADDR: 2445 is_two_addr = true; 2446 // Fallthrough 2447 case Instruction::USHR_INT: 2448 shift_op = true; 2449 op = kOpLsr; 2450 break; 2451 default: 2452 LOG(FATAL) << "Invalid word arith op: " << opcode; 2453 } 2454 2455 // Can we convert to a two address instruction? 2456 if (!is_two_addr && 2457 (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == 2458 mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { 2459 is_two_addr = true; 2460 } 2461 2462 if (!GenerateTwoOperandInstructions()) { 2463 is_two_addr = false; 2464 } 2465 2466 // Get the div/rem stuff out of the way. 2467 if (is_div_rem) { 2468 rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); 2469 StoreValue(rl_dest, rl_result); 2470 return; 2471 } 2472 2473 if (unary) { 2474 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2475 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2476 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2477 OpRegReg(op, rl_result.reg, rl_lhs.reg); 2478 } else { 2479 if (shift_op) { 2480 // X86 doesn't require masking and must use ECX. 2481 RegStorage t_reg = TargetReg(kCount); // rCX 2482 LoadValueDirectFixed(rl_rhs, t_reg); 2483 if (is_two_addr) { 2484 // Can we do this directly into memory? 2485 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2486 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2487 if (rl_result.location != kLocPhysReg) { 2488 // Okay, we can do this into memory 2489 OpMemReg(op, rl_result, t_reg.GetReg()); 2490 FreeTemp(t_reg); 2491 return; 2492 } else if (!rl_result.reg.IsFloat()) { 2493 // Can do this directly into the result register 2494 OpRegReg(op, rl_result.reg, t_reg); 2495 FreeTemp(t_reg); 2496 StoreFinalValue(rl_dest, rl_result); 2497 return; 2498 } 2499 } 2500 // Three address form, or we can't do directly. 2501 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2502 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2503 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); 2504 FreeTemp(t_reg); 2505 } else { 2506 // Multiply is 3 operand only (sort of). 2507 if (is_two_addr && op != kOpMul) { 2508 // Can we do this directly into memory? 2509 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2510 if (rl_result.location == kLocPhysReg) { 2511 // Ensure res is in a core reg 2512 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2513 // Can we do this from memory directly? 2514 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2515 if (rl_rhs.location != kLocPhysReg) { 2516 OpRegMem(op, rl_result.reg, rl_rhs); 2517 StoreFinalValue(rl_dest, rl_result); 2518 return; 2519 } else if (!rl_rhs.reg.IsFloat()) { 2520 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2521 StoreFinalValue(rl_dest, rl_result); 2522 return; 2523 } 2524 } 2525 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2526 // It might happen rl_rhs and rl_dest are the same VR 2527 // in this case rl_dest is in reg after LoadValue while 2528 // rl_result is not updated yet, so do this 2529 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2530 if (rl_result.location != kLocPhysReg) { 2531 // Okay, we can do this into memory. 2532 OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); 2533 return; 2534 } else if (!rl_result.reg.IsFloat()) { 2535 // Can do this directly into the result register. 2536 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2537 StoreFinalValue(rl_dest, rl_result); 2538 return; 2539 } else { 2540 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2541 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2542 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2543 } 2544 } else { 2545 // Try to use reg/memory instructions. 2546 rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); 2547 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2548 // We can't optimize with FP registers. 2549 if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { 2550 // Something is difficult, so fall back to the standard case. 2551 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2552 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2553 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2554 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2555 } else { 2556 // We can optimize by moving to result and using memory operands. 2557 if (rl_rhs.location != kLocPhysReg) { 2558 // Force LHS into result. 2559 // We should be careful with order here 2560 // If rl_dest and rl_lhs points to the same VR we should load first 2561 // If the are different we should find a register first for dest 2562 if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == 2563 mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { 2564 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2565 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2566 // No-op if these are the same. 2567 OpRegCopy(rl_result.reg, rl_lhs.reg); 2568 } else { 2569 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2570 LoadValueDirect(rl_lhs, rl_result.reg); 2571 } 2572 OpRegMem(op, rl_result.reg, rl_rhs); 2573 } else if (rl_lhs.location != kLocPhysReg) { 2574 // RHS is in a register; LHS is in memory. 2575 if (op != kOpSub) { 2576 // Force RHS into result and operate on memory. 2577 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2578 OpRegCopy(rl_result.reg, rl_rhs.reg); 2579 OpRegMem(op, rl_result.reg, rl_lhs); 2580 } else { 2581 // Subtraction isn't commutative. 2582 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2583 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2584 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2585 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2586 } 2587 } else { 2588 // Both are in registers. 2589 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2590 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2591 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2592 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2593 } 2594 } 2595 } 2596 } 2597 } 2598 StoreValue(rl_dest, rl_result); 2599} 2600 2601bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { 2602 // If we have non-core registers, then we can't do good things. 2603 if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { 2604 return false; 2605 } 2606 if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { 2607 return false; 2608 } 2609 2610 // Everything will be fine :-). 2611 return true; 2612} 2613 2614void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 2615 if (!Gen64Bit()) { 2616 Mir2Lir::GenIntToLong(rl_dest, rl_src); 2617 return; 2618 } 2619 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 2620 if (rl_src.location == kLocPhysReg) { 2621 NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 2622 } else { 2623 int displacement = SRegOffset(rl_src.s_reg_low); 2624 LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(), 2625 displacement + LOWORD_OFFSET); 2626 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 2627 true /* is_load */, true /* is_64bit */); 2628 } 2629 StoreValueWide(rl_dest, rl_result); 2630} 2631 2632void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 2633 RegLocation rl_src1, RegLocation rl_shift) { 2634 if (!Gen64Bit()) { 2635 Mir2Lir::GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); 2636 return; 2637 } 2638 2639 bool is_two_addr = false; 2640 OpKind op = kOpBkpt; 2641 RegLocation rl_result; 2642 2643 switch (opcode) { 2644 case Instruction::SHL_LONG_2ADDR: 2645 is_two_addr = true; 2646 // Fallthrough 2647 case Instruction::SHL_LONG: 2648 op = kOpLsl; 2649 break; 2650 case Instruction::SHR_LONG_2ADDR: 2651 is_two_addr = true; 2652 // Fallthrough 2653 case Instruction::SHR_LONG: 2654 op = kOpAsr; 2655 break; 2656 case Instruction::USHR_LONG_2ADDR: 2657 is_two_addr = true; 2658 // Fallthrough 2659 case Instruction::USHR_LONG: 2660 op = kOpLsr; 2661 break; 2662 default: 2663 op = kOpBkpt; 2664 } 2665 2666 // X86 doesn't require masking and must use ECX. 2667 RegStorage t_reg = TargetReg(kCount); // rCX 2668 LoadValueDirectFixed(rl_shift, t_reg); 2669 if (is_two_addr) { 2670 // Can we do this directly into memory? 2671 rl_result = UpdateLocWideTyped(rl_dest, kCoreReg); 2672 if (rl_result.location != kLocPhysReg) { 2673 // Okay, we can do this into memory 2674 OpMemReg(op, rl_result, t_reg.GetReg()); 2675 } else if (!rl_result.reg.IsFloat()) { 2676 // Can do this directly into the result register 2677 OpRegReg(op, rl_result.reg, t_reg); 2678 StoreFinalValueWide(rl_dest, rl_result); 2679 } 2680 } else { 2681 // Three address form, or we can't do directly. 2682 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2683 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2684 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 2685 StoreFinalValueWide(rl_dest, rl_result); 2686 } 2687 2688 FreeTemp(t_reg); 2689} 2690 2691} // namespace art 2692