int_x86.cc revision de68676b24f61a55adc0b22fe828f036a5925c41
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the X86 ISA */ 18 19#include "codegen_x86.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "mirror/array.h" 22#include "x86_lir.h" 23 24namespace art { 25 26/* 27 * Compare two 64-bit values 28 * x = y return 0 29 * x < y return -1 30 * x > y return 1 31 */ 32void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 33 RegLocation rl_src2) { 34 if (Gen64Bit()) { 35 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 36 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 37 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 38 RegStorage temp_reg = AllocTemp(); 39 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 40 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 41 NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 42 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); 43 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); 44 45 StoreValue(rl_dest, rl_result); 46 FreeTemp(temp_reg); 47 return; 48 } 49 50 FlushAllRegs(); 51 LockCallTemps(); // Prepare for explicit register usage 52 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 53 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 54 LoadValueDirectWideFixed(rl_src1, r_tmp1); 55 LoadValueDirectWideFixed(rl_src2, r_tmp2); 56 // Compute (r1:r0) = (r1:r0) - (r3:r2) 57 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 58 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 59 NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 60 NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); 61 OpReg(kOpNeg, rs_r2); // r2 = -r2 62 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF 63 NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 64 NewLIR2(kX86Movzx8RR, r0, r0); 65 OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 66 RegLocation rl_result = LocCReturn(); 67 StoreValue(rl_dest, rl_result); 68} 69 70X86ConditionCode X86ConditionEncoding(ConditionCode cond) { 71 switch (cond) { 72 case kCondEq: return kX86CondEq; 73 case kCondNe: return kX86CondNe; 74 case kCondCs: return kX86CondC; 75 case kCondCc: return kX86CondNc; 76 case kCondUlt: return kX86CondC; 77 case kCondUge: return kX86CondNc; 78 case kCondMi: return kX86CondS; 79 case kCondPl: return kX86CondNs; 80 case kCondVs: return kX86CondO; 81 case kCondVc: return kX86CondNo; 82 case kCondHi: return kX86CondA; 83 case kCondLs: return kX86CondBe; 84 case kCondGe: return kX86CondGe; 85 case kCondLt: return kX86CondL; 86 case kCondGt: return kX86CondG; 87 case kCondLe: return kX86CondLe; 88 case kCondAl: 89 case kCondNv: LOG(FATAL) << "Should not reach here"; 90 } 91 return kX86CondO; 92} 93 94LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { 95 NewLIR2(kX86Cmp32RR, src1.GetReg(), src2.GetReg()); 96 X86ConditionCode cc = X86ConditionEncoding(cond); 97 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , 98 cc); 99 branch->target = target; 100 return branch; 101} 102 103LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, 104 int check_value, LIR* target) { 105 if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { 106 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode 107 NewLIR2(kX86Test32RR, reg.GetReg(), reg.GetReg()); 108 } else { 109 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); 110 } 111 X86ConditionCode cc = X86ConditionEncoding(cond); 112 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); 113 branch->target = target; 114 return branch; 115} 116 117LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 118 // If src or dest is a pair, we'll be using low reg. 119 if (r_dest.IsPair()) { 120 r_dest = r_dest.GetLow(); 121 } 122 if (r_src.IsPair()) { 123 r_src = r_src.GetLow(); 124 } 125 if (r_dest.IsFloat() || r_src.IsFloat()) 126 return OpFpRegCopy(r_dest, r_src); 127 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, 128 r_dest.GetReg(), r_src.GetReg()); 129 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 130 res->flags.is_nop = true; 131 } 132 return res; 133} 134 135void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 136 if (r_dest != r_src) { 137 LIR *res = OpRegCopyNoInsert(r_dest, r_src); 138 AppendLIR(res); 139 } 140} 141 142void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { 143 if (r_dest != r_src) { 144 bool dest_fp = r_dest.IsFloat(); 145 bool src_fp = r_src.IsFloat(); 146 if (dest_fp) { 147 if (src_fp) { 148 OpRegCopy(r_dest, r_src); 149 } else { 150 // TODO: Prevent this from happening in the code. The result is often 151 // unused or could have been loaded more easily from memory. 152 if (!r_src.IsPair()) { 153 DCHECK(!r_dest.IsPair()); 154 NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); 155 } else { 156 NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); 157 RegStorage r_tmp = AllocTempDouble(); 158 NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); 159 NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); 160 FreeTemp(r_tmp); 161 } 162 } 163 } else { 164 if (src_fp) { 165 if (!r_dest.IsPair()) { 166 DCHECK(!r_src.IsPair()); 167 NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); 168 } else { 169 NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); 170 RegStorage temp_reg = AllocTempDouble(); 171 NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); 172 NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); 173 NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); 174 } 175 } else { 176 DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); 177 if (!r_src.IsPair()) { 178 // Just copy the register directly. 179 OpRegCopy(r_dest, r_src); 180 } else { 181 // Handle overlap 182 if (r_src.GetHighReg() == r_dest.GetLowReg() && 183 r_src.GetLowReg() == r_dest.GetHighReg()) { 184 // Deal with cycles. 185 RegStorage temp_reg = AllocTemp(); 186 OpRegCopy(temp_reg, r_dest.GetHigh()); 187 OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); 188 OpRegCopy(r_dest.GetLow(), temp_reg); 189 FreeTemp(temp_reg); 190 } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { 191 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 192 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 193 } else { 194 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 195 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 196 } 197 } 198 } 199 } 200 } 201} 202 203void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 204 RegLocation rl_result; 205 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 206 RegLocation rl_dest = mir_graph_->GetDest(mir); 207 // Avoid using float regs here. 208 RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; 209 RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; 210 rl_src = LoadValue(rl_src, src_reg_class); 211 ConditionCode ccode = mir->meta.ccode; 212 213 // The kMirOpSelect has two variants, one for constants and one for moves. 214 const bool is_constant_case = (mir->ssa_rep->num_uses == 1); 215 216 if (is_constant_case) { 217 int true_val = mir->dalvikInsn.vB; 218 int false_val = mir->dalvikInsn.vC; 219 rl_result = EvalLoc(rl_dest, result_reg_class, true); 220 221 /* 222 * For ccode == kCondEq: 223 * 224 * 1) When the true case is zero and result_reg is not same as src_reg: 225 * xor result_reg, result_reg 226 * cmp $0, src_reg 227 * mov t1, $false_case 228 * cmovnz result_reg, t1 229 * 2) When the false case is zero and result_reg is not same as src_reg: 230 * xor result_reg, result_reg 231 * cmp $0, src_reg 232 * mov t1, $true_case 233 * cmovz result_reg, t1 234 * 3) All other cases (we do compare first to set eflags): 235 * cmp $0, src_reg 236 * mov result_reg, $false_case 237 * mov t1, $true_case 238 * cmovz result_reg, t1 239 */ 240 // FIXME: depending on how you use registers you could get a false != mismatch when dealing 241 // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). 242 const bool result_reg_same_as_src = 243 (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg()); 244 const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); 245 const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); 246 const bool catch_all_case = !(true_zero_case || false_zero_case); 247 248 if (true_zero_case || false_zero_case) { 249 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); 250 } 251 252 if (true_zero_case || false_zero_case || catch_all_case) { 253 OpRegImm(kOpCmp, rl_src.reg, 0); 254 } 255 256 if (catch_all_case) { 257 OpRegImm(kOpMov, rl_result.reg, false_val); 258 } 259 260 if (true_zero_case || false_zero_case || catch_all_case) { 261 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; 262 int immediateForTemp = true_zero_case ? false_val : true_val; 263 RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); 264 OpRegImm(kOpMov, temp1_reg, immediateForTemp); 265 266 OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); 267 268 FreeTemp(temp1_reg); 269 } 270 } else { 271 RegLocation rl_true = mir_graph_->GetSrc(mir, 1); 272 RegLocation rl_false = mir_graph_->GetSrc(mir, 2); 273 rl_true = LoadValue(rl_true, result_reg_class); 274 rl_false = LoadValue(rl_false, result_reg_class); 275 rl_result = EvalLoc(rl_dest, result_reg_class, true); 276 277 /* 278 * For ccode == kCondEq: 279 * 280 * 1) When true case is already in place: 281 * cmp $0, src_reg 282 * cmovnz result_reg, false_reg 283 * 2) When false case is already in place: 284 * cmp $0, src_reg 285 * cmovz result_reg, true_reg 286 * 3) When neither cases are in place: 287 * cmp $0, src_reg 288 * mov result_reg, false_reg 289 * cmovz result_reg, true_reg 290 */ 291 292 // kMirOpSelect is generated just for conditional cases when comparison is done with zero. 293 OpRegImm(kOpCmp, rl_src.reg, 0); 294 295 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { 296 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); 297 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { 298 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 299 } else { 300 OpRegCopy(rl_result.reg, rl_false.reg); 301 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 302 } 303 } 304 305 StoreValue(rl_dest, rl_result); 306} 307 308void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 309 LIR* taken = &block_label_list_[bb->taken]; 310 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 311 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 312 ConditionCode ccode = mir->meta.ccode; 313 314 if (rl_src1.is_const) { 315 std::swap(rl_src1, rl_src2); 316 ccode = FlipComparisonOrder(ccode); 317 } 318 if (rl_src2.is_const) { 319 // Do special compare/branch against simple const operand 320 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 321 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); 322 return; 323 } 324 325 if (Gen64Bit()) { 326 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 327 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 328 329 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 330 OpCondBranch(ccode, taken); 331 return; 332 } 333 334 FlushAllRegs(); 335 LockCallTemps(); // Prepare for explicit register usage 336 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 337 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 338 LoadValueDirectWideFixed(rl_src1, r_tmp1); 339 LoadValueDirectWideFixed(rl_src2, r_tmp2); 340 341 // Swap operands and condition code to prevent use of zero flag. 342 if (ccode == kCondLe || ccode == kCondGt) { 343 // Compute (r3:r2) = (r3:r2) - (r1:r0) 344 OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 345 OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF 346 } else { 347 // Compute (r1:r0) = (r1:r0) - (r3:r2) 348 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 349 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 350 } 351 switch (ccode) { 352 case kCondEq: 353 case kCondNe: 354 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 355 break; 356 case kCondLe: 357 ccode = kCondGe; 358 break; 359 case kCondGt: 360 ccode = kCondLt; 361 break; 362 case kCondLt: 363 case kCondGe: 364 break; 365 default: 366 LOG(FATAL) << "Unexpected ccode: " << ccode; 367 } 368 OpCondBranch(ccode, taken); 369} 370 371void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 372 int64_t val, ConditionCode ccode) { 373 int32_t val_lo = Low32Bits(val); 374 int32_t val_hi = High32Bits(val); 375 LIR* taken = &block_label_list_[bb->taken]; 376 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 377 bool is_equality_test = ccode == kCondEq || ccode == kCondNe; 378 379 if (Gen64Bit()) { 380 if (is_equality_test && val == 0) { 381 // We can simplify of comparing for ==, != to 0. 382 NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg()); 383 } else if (is_equality_test && val_hi == 0 && val_lo > 0) { 384 OpRegImm(kOpCmp, rl_src1.reg, val_lo); 385 } else { 386 RegStorage tmp = AllocTypedTempWide(false, kCoreReg); 387 LoadConstantWide(tmp, val); 388 OpRegReg(kOpCmp, rl_src1.reg, tmp); 389 FreeTemp(tmp); 390 } 391 OpCondBranch(ccode, taken); 392 return; 393 } 394 395 if (is_equality_test && val != 0) { 396 rl_src1 = ForceTempWide(rl_src1); 397 } 398 RegStorage low_reg = rl_src1.reg.GetLow(); 399 RegStorage high_reg = rl_src1.reg.GetHigh(); 400 401 if (is_equality_test) { 402 // We can simplify of comparing for ==, != to 0. 403 if (val == 0) { 404 if (IsTemp(low_reg)) { 405 OpRegReg(kOpOr, low_reg, high_reg); 406 // We have now changed it; ignore the old values. 407 Clobber(rl_src1.reg); 408 } else { 409 RegStorage t_reg = AllocTemp(); 410 OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); 411 FreeTemp(t_reg); 412 } 413 OpCondBranch(ccode, taken); 414 return; 415 } 416 417 // Need to compute the actual value for ==, !=. 418 OpRegImm(kOpSub, low_reg, val_lo); 419 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 420 OpRegReg(kOpOr, high_reg, low_reg); 421 Clobber(rl_src1.reg); 422 } else if (ccode == kCondLe || ccode == kCondGt) { 423 // Swap operands and condition code to prevent use of zero flag. 424 RegStorage tmp = AllocTypedTempWide(false, kCoreReg); 425 LoadConstantWide(tmp, val); 426 OpRegReg(kOpSub, tmp.GetLow(), low_reg); 427 OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); 428 ccode = (ccode == kCondLe) ? kCondGe : kCondLt; 429 FreeTemp(tmp); 430 } else { 431 // We can use a compare for the low word to set CF. 432 OpRegImm(kOpCmp, low_reg, val_lo); 433 if (IsTemp(high_reg)) { 434 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 435 // We have now changed it; ignore the old values. 436 Clobber(rl_src1.reg); 437 } else { 438 // mov temp_reg, high_reg; sbb temp_reg, high_constant 439 RegStorage t_reg = AllocTemp(); 440 OpRegCopy(t_reg, high_reg); 441 NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); 442 FreeTemp(t_reg); 443 } 444 } 445 446 OpCondBranch(ccode, taken); 447} 448 449void X86Mir2Lir::CalculateMagicAndShift(int divisor, int& magic, int& shift) { 450 // It does not make sense to calculate magic and shift for zero divisor. 451 DCHECK_NE(divisor, 0); 452 453 /* According to H.S.Warren's Hacker's Delight Chapter 10 and 454 * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 455 * The magic number M and shift S can be calculated in the following way: 456 * Let nc be the most positive value of numerator(n) such that nc = kd - 1, 457 * where divisor(d) >=2. 458 * Let nc be the most negative value of numerator(n) such that nc = kd + 1, 459 * where divisor(d) <= -2. 460 * Thus nc can be calculated like: 461 * nc = 2^31 + 2^31 % d - 1, where d >= 2 462 * nc = -2^31 + (2^31 + 1) % d, where d >= 2. 463 * 464 * So the shift p is the smallest p satisfying 465 * 2^p > nc * (d - 2^p % d), where d >= 2 466 * 2^p > nc * (d + 2^p % d), where d <= -2. 467 * 468 * the magic number M is calcuated by 469 * M = (2^p + d - 2^p % d) / d, where d >= 2 470 * M = (2^p - d - 2^p % d) / d, where d <= -2. 471 * 472 * Notice that p is always bigger than or equal to 32, so we just return 32-p as 473 * the shift number S. 474 */ 475 476 int32_t p = 31; 477 const uint32_t two31 = 0x80000000U; 478 479 // Initialize the computations. 480 uint32_t abs_d = (divisor >= 0) ? divisor : -divisor; 481 uint32_t tmp = two31 + (static_cast<uint32_t>(divisor) >> 31); 482 uint32_t abs_nc = tmp - 1 - tmp % abs_d; 483 uint32_t quotient1 = two31 / abs_nc; 484 uint32_t remainder1 = two31 % abs_nc; 485 uint32_t quotient2 = two31 / abs_d; 486 uint32_t remainder2 = two31 % abs_d; 487 488 /* 489 * To avoid handling both positive and negative divisor, Hacker's Delight 490 * introduces a method to handle these 2 cases together to avoid duplication. 491 */ 492 uint32_t delta; 493 do { 494 p++; 495 quotient1 = 2 * quotient1; 496 remainder1 = 2 * remainder1; 497 if (remainder1 >= abs_nc) { 498 quotient1++; 499 remainder1 = remainder1 - abs_nc; 500 } 501 quotient2 = 2 * quotient2; 502 remainder2 = 2 * remainder2; 503 if (remainder2 >= abs_d) { 504 quotient2++; 505 remainder2 = remainder2 - abs_d; 506 } 507 delta = abs_d - remainder2; 508 } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); 509 510 magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); 511 shift = p - 32; 512} 513 514RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { 515 LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; 516 return rl_dest; 517} 518 519RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, 520 int imm, bool is_div) { 521 // Use a multiply (and fixup) to perform an int div/rem by a constant. 522 523 // We have to use fixed registers, so flush all the temps. 524 FlushAllRegs(); 525 LockCallTemps(); // Prepare for explicit register usage. 526 527 // Assume that the result will be in EDX. 528 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; 529 530 // handle div/rem by 1 special case. 531 if (imm == 1) { 532 if (is_div) { 533 // x / 1 == x. 534 StoreValue(rl_result, rl_src); 535 } else { 536 // x % 1 == 0. 537 LoadConstantNoClobber(rs_r0, 0); 538 // For this case, return the result in EAX. 539 rl_result.reg.SetReg(r0); 540 } 541 } else if (imm == -1) { // handle 0x80000000 / -1 special case. 542 if (is_div) { 543 LIR *minint_branch = 0; 544 LoadValueDirectFixed(rl_src, rs_r0); 545 OpRegImm(kOpCmp, rs_r0, 0x80000000); 546 minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); 547 548 // for x != MIN_INT, x / -1 == -x. 549 NewLIR1(kX86Neg32R, r0); 550 551 LIR* branch_around = NewLIR1(kX86Jmp8, 0); 552 // The target for cmp/jmp above. 553 minint_branch->target = NewLIR0(kPseudoTargetLabel); 554 // EAX already contains the right value (0x80000000), 555 branch_around->target = NewLIR0(kPseudoTargetLabel); 556 } else { 557 // x % -1 == 0. 558 LoadConstantNoClobber(rs_r0, 0); 559 } 560 // For this case, return the result in EAX. 561 rl_result.reg.SetReg(r0); 562 } else { 563 CHECK(imm <= -2 || imm >= 2); 564 // Use H.S.Warren's Hacker's Delight Chapter 10 and 565 // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 566 int magic, shift; 567 CalculateMagicAndShift(imm, magic, shift); 568 569 /* 570 * For imm >= 2, 571 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 572 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. 573 * For imm <= -2, 574 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 575 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. 576 * We implement this algorithm in the following way: 577 * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX 578 * 2. if imm > 0 and magic < 0, add numerator to EDX 579 * if imm < 0 and magic > 0, sub numerator from EDX 580 * 3. if S !=0, SAR S bits for EDX 581 * 4. add 1 to EDX if EDX < 0 582 * 5. Thus, EDX is the quotient 583 */ 584 585 // Numerator into EAX. 586 RegStorage numerator_reg; 587 if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { 588 // We will need the value later. 589 if (rl_src.location == kLocPhysReg) { 590 // We can use it directly. 591 DCHECK(rl_src.reg.GetReg() != rs_r0.GetReg() && rl_src.reg.GetReg() != rs_r2.GetReg()); 592 numerator_reg = rl_src.reg; 593 } else { 594 numerator_reg = rs_r1; 595 LoadValueDirectFixed(rl_src, numerator_reg); 596 } 597 OpRegCopy(rs_r0, numerator_reg); 598 } else { 599 // Only need this once. Just put it into EAX. 600 LoadValueDirectFixed(rl_src, rs_r0); 601 } 602 603 // EDX = magic. 604 LoadConstantNoClobber(rs_r2, magic); 605 606 // EDX:EAX = magic & dividend. 607 NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); 608 609 if (imm > 0 && magic < 0) { 610 // Add numerator to EDX. 611 DCHECK(numerator_reg.Valid()); 612 NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 613 } else if (imm < 0 && magic > 0) { 614 DCHECK(numerator_reg.Valid()); 615 NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 616 } 617 618 // Do we need the shift? 619 if (shift != 0) { 620 // Shift EDX by 'shift' bits. 621 NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); 622 } 623 624 // Add 1 to EDX if EDX < 0. 625 626 // Move EDX to EAX. 627 OpRegCopy(rs_r0, rs_r2); 628 629 // Move sign bit to bit 0, zeroing the rest. 630 NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); 631 632 // EDX = EDX + EAX. 633 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); 634 635 // Quotient is in EDX. 636 if (!is_div) { 637 // We need to compute the remainder. 638 // Remainder is divisor - (quotient * imm). 639 DCHECK(numerator_reg.Valid()); 640 OpRegCopy(rs_r0, numerator_reg); 641 642 // EAX = numerator * imm. 643 OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); 644 645 // EDX -= EAX. 646 NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); 647 648 // For this case, return the result in EAX. 649 rl_result.reg.SetReg(r0); 650 } 651 } 652 653 return rl_result; 654} 655 656RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 657 bool is_div) { 658 LOG(FATAL) << "Unexpected use of GenDivRem for x86"; 659 return rl_dest; 660} 661 662RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 663 RegLocation rl_src2, bool is_div, bool check_zero) { 664 // We have to use fixed registers, so flush all the temps. 665 FlushAllRegs(); 666 LockCallTemps(); // Prepare for explicit register usage. 667 668 // Load LHS into EAX. 669 LoadValueDirectFixed(rl_src1, rs_r0); 670 671 // Load RHS into EBX. 672 LoadValueDirectFixed(rl_src2, rs_r1); 673 674 // Copy LHS sign bit into EDX. 675 NewLIR0(kx86Cdq32Da); 676 677 if (check_zero) { 678 // Handle division by zero case. 679 GenDivZeroCheck(rs_r1); 680 } 681 682 // Have to catch 0x80000000/-1 case, or we will get an exception! 683 OpRegImm(kOpCmp, rs_r1, -1); 684 LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 685 686 // RHS is -1. 687 OpRegImm(kOpCmp, rs_r0, 0x80000000); 688 LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 689 690 // In 0x80000000/-1 case. 691 if (!is_div) { 692 // For DIV, EAX is already right. For REM, we need EDX 0. 693 LoadConstantNoClobber(rs_r2, 0); 694 } 695 LIR* done = NewLIR1(kX86Jmp8, 0); 696 697 // Expected case. 698 minus_one_branch->target = NewLIR0(kPseudoTargetLabel); 699 minint_branch->target = minus_one_branch->target; 700 NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); 701 done->target = NewLIR0(kPseudoTargetLabel); 702 703 // Result is in EAX for div and EDX for rem. 704 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; 705 if (!is_div) { 706 rl_result.reg.SetReg(r2); 707 } 708 return rl_result; 709} 710 711bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { 712 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 713 714 // Get the two arguments to the invoke and place them in GP registers. 715 RegLocation rl_src1 = info->args[0]; 716 RegLocation rl_src2 = info->args[1]; 717 rl_src1 = LoadValue(rl_src1, kCoreReg); 718 rl_src2 = LoadValue(rl_src2, kCoreReg); 719 720 RegLocation rl_dest = InlineTarget(info); 721 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 722 723 /* 724 * If the result register is the same as the second element, then we need to be careful. 725 * The reason is that the first copy will inadvertently clobber the second element with 726 * the first one thus yielding the wrong result. Thus we do a swap in that case. 727 */ 728 if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 729 std::swap(rl_src1, rl_src2); 730 } 731 732 // Pick the first integer as min/max. 733 OpRegCopy(rl_result.reg, rl_src1.reg); 734 735 // If the integers are both in the same register, then there is nothing else to do 736 // because they are equal and we have already moved one into the result. 737 if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { 738 // It is possible we didn't pick correctly so do the actual comparison now. 739 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 740 741 // Conditionally move the other integer into the destination register. 742 ConditionCode condition_code = is_min ? kCondGt : kCondLt; 743 OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); 744 } 745 746 StoreValue(rl_dest, rl_result); 747 return true; 748} 749 750bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 751 RegLocation rl_src_address = info->args[0]; // long address 752 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 753 RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); 754 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 755 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 756 // Unaligned access is allowed on x86. 757 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size); 758 if (size == k64) { 759 StoreValueWide(rl_dest, rl_result); 760 } else { 761 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 762 StoreValue(rl_dest, rl_result); 763 } 764 return true; 765} 766 767bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 768 RegLocation rl_src_address = info->args[0]; // long address 769 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 770 RegLocation rl_src_value = info->args[2]; // [size] value 771 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 772 if (size == k64) { 773 // Unaligned access is allowed on x86. 774 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 775 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 776 } else { 777 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 778 // Unaligned access is allowed on x86. 779 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 780 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 781 } 782 return true; 783} 784 785void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { 786 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); 787} 788 789void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { 790 DCHECK_EQ(kX86, cu_->instruction_set); 791 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 792} 793 794void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { 795 DCHECK_EQ(kX86_64, cu_->instruction_set); 796 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 797} 798 799static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { 800 return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); 801} 802 803bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 804 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 805 // Unused - RegLocation rl_src_unsafe = info->args[0]; 806 RegLocation rl_src_obj = info->args[1]; // Object - known non-null 807 RegLocation rl_src_offset = info->args[2]; // long low 808 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 809 RegLocation rl_src_expected = info->args[4]; // int, long or Object 810 // If is_long, high half is in info->args[5] 811 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object 812 // If is_long, high half is in info->args[7] 813 814 if (is_long) { 815 // TODO: avoid unnecessary loads of SI and DI when the values are in registers. 816 // TODO: CFI support. 817 FlushAllRegs(); 818 LockCallTemps(); 819 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); 820 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); 821 LoadValueDirectWideFixed(rl_src_expected, r_tmp1); 822 LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); 823 // FIXME: needs 64-bit update. 824 const bool obj_in_di = IsInReg(this, rl_src_obj, rs_rDI); 825 const bool obj_in_si = IsInReg(this, rl_src_obj, rs_rSI); 826 DCHECK(!obj_in_si || !obj_in_di); 827 const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); 828 const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); 829 DCHECK(!off_in_si || !off_in_di); 830 // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg. 831 RegStorage rs_obj = obj_in_di ? rs_rDI : obj_in_si ? rs_rSI : !off_in_di ? rs_rDI : rs_rSI; 832 RegStorage rs_off = off_in_si ? rs_rSI : off_in_di ? rs_rDI : !obj_in_si ? rs_rSI : rs_rDI; 833 bool push_di = (!obj_in_di && !off_in_di) && (rs_obj == rs_rDI || rs_off == rs_rDI); 834 bool push_si = (!obj_in_si && !off_in_si) && (rs_obj == rs_rSI || rs_off == rs_rSI); 835 if (push_di) { 836 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 837 MarkTemp(rs_rDI); 838 LockTemp(rs_rDI); 839 } 840 if (push_si) { 841 NewLIR1(kX86Push32R, rs_rSI.GetReg()); 842 MarkTemp(rs_rSI); 843 LockTemp(rs_rSI); 844 } 845 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 846 const size_t push_offset = (push_si ? 4u : 0u) + (push_di ? 4u : 0u); 847 if (!obj_in_si && !obj_in_di) { 848 LoadWordDisp(TargetReg(kSp), SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); 849 // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. 850 DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); 851 int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; 852 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); 853 } 854 if (!off_in_si && !off_in_di) { 855 LoadWordDisp(TargetReg(kSp), SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); 856 // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. 857 DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); 858 int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; 859 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); 860 } 861 NewLIR4(kX86LockCmpxchg64A, rs_obj.GetReg(), rs_off.GetReg(), 0, 0); 862 863 // After a store we need to insert barrier in case of potential load. Since the 864 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 865 GenMemBarrier(kStoreLoad); 866 867 868 if (push_si) { 869 FreeTemp(rs_rSI); 870 UnmarkTemp(rs_rSI); 871 NewLIR1(kX86Pop32R, rs_rSI.GetReg()); 872 } 873 if (push_di) { 874 FreeTemp(rs_rDI); 875 UnmarkTemp(rs_rDI); 876 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 877 } 878 FreeCallTemps(); 879 } else { 880 // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. 881 FlushReg(rs_r0); 882 Clobber(rs_r0); 883 LockTemp(rs_r0); 884 885 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 886 RegLocation rl_new_value = LoadValue(rl_src_new_value); 887 888 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { 889 // Mark card for object assuming new value is stored. 890 FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). 891 MarkGCCard(rl_new_value.reg, rl_object.reg); 892 LockTemp(rs_r0); 893 } 894 895 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 896 LoadValueDirect(rl_src_expected, rs_r0); 897 NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, rl_new_value.reg.GetReg()); 898 899 // After a store we need to insert barrier in case of potential load. Since the 900 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 901 GenMemBarrier(kStoreLoad); 902 903 FreeTemp(rs_r0); 904 } 905 906 // Convert ZF to boolean 907 RegLocation rl_dest = InlineTarget(info); // boolean place for result 908 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 909 RegStorage result_reg = rl_result.reg; 910 911 // For 32-bit, SETcc only works with EAX..EDX. 912 if (!IsByteRegister(result_reg)) { 913 result_reg = AllocateByteRegister(); 914 } 915 NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); 916 NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); 917 if (IsTemp(result_reg)) { 918 FreeTemp(result_reg); 919 } 920 StoreValue(rl_dest, rl_result); 921 return true; 922} 923 924LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { 925 CHECK(base_of_code_ != nullptr); 926 927 // Address the start of the method 928 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 929 if (rl_method.wide) { 930 LoadValueDirectWideFixed(rl_method, reg); 931 } else { 932 LoadValueDirectFixed(rl_method, reg); 933 } 934 store_method_addr_used_ = true; 935 936 // Load the proper value from the literal area. 937 // We don't know the proper offset for the value, so pick one that will force 938 // 4 byte offset. We will fix this up in the assembler later to have the right 939 // value. 940 ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); 941 LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, 942 0, 0, target); 943 res->target = target; 944 res->flags.fixup = kFixupLoad; 945 store_method_addr_used_ = true; 946 return res; 947} 948 949LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { 950 LOG(FATAL) << "Unexpected use of OpVldm for x86"; 951 return NULL; 952} 953 954LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { 955 LOG(FATAL) << "Unexpected use of OpVstm for x86"; 956 return NULL; 957} 958 959void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 960 RegLocation rl_result, int lit, 961 int first_bit, int second_bit) { 962 RegStorage t_reg = AllocTemp(); 963 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); 964 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); 965 FreeTemp(t_reg); 966 if (first_bit != 0) { 967 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); 968 } 969} 970 971void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { 972 if (Gen64Bit()) { 973 DCHECK(reg.Is64Bit()); 974 975 NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); 976 } else { 977 DCHECK(reg.IsPair()); 978 979 // We are not supposed to clobber the incoming storage, so allocate a temporary. 980 RegStorage t_reg = AllocTemp(); 981 // Doing an OR is a quick way to check if both registers are zero. This will set the flags. 982 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); 983 // The temp is no longer needed so free it at this time. 984 FreeTemp(t_reg); 985 } 986 987 // In case of zero, throw ArithmeticException. 988 GenDivZeroCheck(kCondEq); 989} 990 991void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, 992 RegStorage array_base, 993 int len_offset) { 994 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 995 public: 996 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 997 RegStorage index, RegStorage array_base, int32_t len_offset) 998 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 999 index_(index), array_base_(array_base), len_offset_(len_offset) { 1000 } 1001 1002 void Compile() OVERRIDE { 1003 m2l_->ResetRegPool(); 1004 m2l_->ResetDefTracking(); 1005 GenerateTargetLabel(kPseudoThrowTarget); 1006 1007 RegStorage new_index = index_; 1008 // Move index out of kArg1, either directly to kArg0, or to kArg2. 1009 if (index_.GetReg() == m2l_->TargetReg(kArg1).GetReg()) { 1010 if (array_base_.GetReg() == m2l_->TargetReg(kArg0).GetReg()) { 1011 m2l_->OpRegCopy(m2l_->TargetReg(kArg2), index_); 1012 new_index = m2l_->TargetReg(kArg2); 1013 } else { 1014 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), index_); 1015 new_index = m2l_->TargetReg(kArg0); 1016 } 1017 } 1018 // Load array length to kArg1. 1019 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 1020 if (cu_->target64) { 1021 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 1022 new_index, m2l_->TargetReg(kArg1), true); 1023 } else { 1024 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 1025 new_index, m2l_->TargetReg(kArg1), true); 1026 } 1027 } 1028 1029 private: 1030 const RegStorage index_; 1031 const RegStorage array_base_; 1032 const int32_t len_offset_; 1033 }; 1034 1035 OpRegMem(kOpCmp, index, array_base, len_offset); 1036 LIR* branch = OpCondBranch(kCondUge, nullptr); 1037 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 1038 index, array_base, len_offset)); 1039} 1040 1041void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, 1042 RegStorage array_base, 1043 int32_t len_offset) { 1044 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 1045 public: 1046 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 1047 int32_t index, RegStorage array_base, int32_t len_offset) 1048 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 1049 index_(index), array_base_(array_base), len_offset_(len_offset) { 1050 } 1051 1052 void Compile() OVERRIDE { 1053 m2l_->ResetRegPool(); 1054 m2l_->ResetDefTracking(); 1055 GenerateTargetLabel(kPseudoThrowTarget); 1056 1057 // Load array length to kArg1. 1058 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 1059 m2l_->LoadConstant(m2l_->TargetReg(kArg0), index_); 1060 if (cu_->target64) { 1061 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 1062 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 1063 } else { 1064 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 1065 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 1066 } 1067 } 1068 1069 private: 1070 const int32_t index_; 1071 const RegStorage array_base_; 1072 const int32_t len_offset_; 1073 }; 1074 1075 NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); 1076 LIR* branch = OpCondBranch(kCondLs, nullptr); 1077 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 1078 index, array_base, len_offset)); 1079} 1080 1081// Test suspend flag, return target of taken suspend branch 1082LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { 1083 if (cu_->target64) { 1084 OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); 1085 } else { 1086 OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); 1087 } 1088 return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); 1089} 1090 1091// Decrement register and branch on condition 1092LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { 1093 OpRegImm(kOpSub, reg, 1); 1094 return OpCondBranch(c_code, target); 1095} 1096 1097bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1098 RegLocation rl_src, RegLocation rl_dest, int lit) { 1099 LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; 1100 return false; 1101} 1102 1103bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1104 LOG(FATAL) << "Unexpected use of easyMultiply in x86"; 1105 return false; 1106} 1107 1108LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { 1109 LOG(FATAL) << "Unexpected use of OpIT in x86"; 1110 return NULL; 1111} 1112 1113void X86Mir2Lir::OpEndIT(LIR* it) { 1114 LOG(FATAL) << "Unexpected use of OpEndIT in x86"; 1115} 1116 1117void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { 1118 switch (val) { 1119 case 0: 1120 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1121 break; 1122 case 1: 1123 OpRegCopy(dest, src); 1124 break; 1125 default: 1126 OpRegRegImm(kOpMul, dest, src, val); 1127 break; 1128 } 1129} 1130 1131void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { 1132 // All memory accesses below reference dalvik regs. 1133 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1134 1135 LIR *m; 1136 switch (val) { 1137 case 0: 1138 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1139 break; 1140 case 1: 1141 LoadBaseDisp(rs_rX86_SP, displacement, dest, k32); 1142 break; 1143 default: 1144 m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), 1145 rs_rX86_SP.GetReg(), displacement, val); 1146 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); 1147 break; 1148 } 1149} 1150 1151void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1152 RegLocation rl_src2) { 1153 // All memory accesses below reference dalvik regs. 1154 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1155 1156 if (Gen64Bit()) { 1157 if (rl_src1.is_const) { 1158 std::swap(rl_src1, rl_src2); 1159 } 1160 // Are we multiplying by a constant? 1161 if (rl_src2.is_const) { 1162 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1163 if (val == 0) { 1164 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1165 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); 1166 StoreValueWide(rl_dest, rl_result); 1167 return; 1168 } else if (val == 1) { 1169 StoreValueWide(rl_dest, rl_src1); 1170 return; 1171 } else if (val == 2) { 1172 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); 1173 return; 1174 } else if (IsPowerOfTwo(val)) { 1175 int shift_amount = LowestSetBit(val); 1176 if (!BadOverlap(rl_src1, rl_dest)) { 1177 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1178 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, 1179 rl_src1, shift_amount); 1180 StoreValueWide(rl_dest, rl_result); 1181 return; 1182 } 1183 } 1184 } 1185 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1186 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1187 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1188 if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && 1189 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 1190 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); 1191 } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && 1192 rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 1193 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); 1194 } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && 1195 rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { 1196 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1197 } else { 1198 OpRegCopy(rl_result.reg, rl_src1.reg); 1199 NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1200 } 1201 StoreValueWide(rl_dest, rl_result); 1202 return; 1203 } 1204 1205 if (rl_src1.is_const) { 1206 std::swap(rl_src1, rl_src2); 1207 } 1208 // Are we multiplying by a constant? 1209 if (rl_src2.is_const) { 1210 // Do special compare/branch against simple const operand 1211 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1212 if (val == 0) { 1213 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1214 OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); 1215 OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); 1216 StoreValueWide(rl_dest, rl_result); 1217 return; 1218 } else if (val == 1) { 1219 StoreValueWide(rl_dest, rl_src1); 1220 return; 1221 } else if (val == 2) { 1222 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); 1223 return; 1224 } else if (IsPowerOfTwo(val)) { 1225 int shift_amount = LowestSetBit(val); 1226 if (!BadOverlap(rl_src1, rl_dest)) { 1227 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1228 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, 1229 rl_src1, shift_amount); 1230 StoreValueWide(rl_dest, rl_result); 1231 return; 1232 } 1233 } 1234 1235 // Okay, just bite the bullet and do it. 1236 int32_t val_lo = Low32Bits(val); 1237 int32_t val_hi = High32Bits(val); 1238 FlushAllRegs(); 1239 LockCallTemps(); // Prepare for explicit register usage. 1240 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1241 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1242 int displacement = SRegOffset(rl_src1.s_reg_low); 1243 1244 // ECX <- 1H * 2L 1245 // EAX <- 1L * 2H 1246 if (src1_in_reg) { 1247 GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); 1248 GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); 1249 } else { 1250 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); 1251 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); 1252 } 1253 1254 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1255 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1256 1257 // EAX <- 2L 1258 LoadConstantNoClobber(rs_r0, val_lo); 1259 1260 // EDX:EAX <- 2L * 1L (double precision) 1261 if (src1_in_reg) { 1262 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1263 } else { 1264 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1265 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1266 true /* is_load */, true /* is_64bit */); 1267 } 1268 1269 // EDX <- EDX + ECX (add high words) 1270 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1271 1272 // Result is EDX:EAX 1273 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1274 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1275 StoreValueWide(rl_dest, rl_result); 1276 return; 1277 } 1278 1279 // Nope. Do it the hard way 1280 // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. 1281 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == 1282 mir_graph_->SRegToVReg(rl_src2.s_reg_low); 1283 1284 FlushAllRegs(); 1285 LockCallTemps(); // Prepare for explicit register usage. 1286 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1287 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1288 1289 // At this point, the VRs are in their home locations. 1290 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1291 bool src2_in_reg = rl_src2.location == kLocPhysReg; 1292 1293 // ECX <- 1H 1294 if (src1_in_reg) { 1295 NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); 1296 } else { 1297 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32); 1298 } 1299 1300 if (is_square) { 1301 // Take advantage of the fact that the values are the same. 1302 // ECX <- ECX * 2L (1H * 2L) 1303 if (src2_in_reg) { 1304 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1305 } else { 1306 int displacement = SRegOffset(rl_src2.s_reg_low); 1307 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1308 displacement + LOWORD_OFFSET); 1309 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1310 true /* is_load */, true /* is_64bit */); 1311 } 1312 1313 // ECX <- 2*ECX (2H * 1L) + (1H * 2L) 1314 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); 1315 } else { 1316 // EAX <- 2H 1317 if (src2_in_reg) { 1318 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); 1319 } else { 1320 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32); 1321 } 1322 1323 // EAX <- EAX * 1L (2H * 1L) 1324 if (src1_in_reg) { 1325 NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); 1326 } else { 1327 int displacement = SRegOffset(rl_src1.s_reg_low); 1328 LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), 1329 displacement + LOWORD_OFFSET); 1330 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1331 true /* is_load */, true /* is_64bit */); 1332 } 1333 1334 // ECX <- ECX * 2L (1H * 2L) 1335 if (src2_in_reg) { 1336 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1337 } else { 1338 int displacement = SRegOffset(rl_src2.s_reg_low); 1339 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1340 displacement + LOWORD_OFFSET); 1341 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1342 true /* is_load */, true /* is_64bit */); 1343 } 1344 1345 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1346 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1347 } 1348 1349 // EAX <- 2L 1350 if (src2_in_reg) { 1351 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); 1352 } else { 1353 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32); 1354 } 1355 1356 // EDX:EAX <- 2L * 1L (double precision) 1357 if (src1_in_reg) { 1358 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1359 } else { 1360 int displacement = SRegOffset(rl_src1.s_reg_low); 1361 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1362 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1363 true /* is_load */, true /* is_64bit */); 1364 } 1365 1366 // EDX <- EDX + ECX (add high words) 1367 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1368 1369 // Result is EDX:EAX 1370 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1371 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1372 StoreValueWide(rl_dest, rl_result); 1373} 1374 1375void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, 1376 Instruction::Code op) { 1377 DCHECK_EQ(rl_dest.location, kLocPhysReg); 1378 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1379 if (rl_src.location == kLocPhysReg) { 1380 // Both operands are in registers. 1381 // But we must ensure that rl_src is in pair 1382 if (Gen64Bit()) { 1383 NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); 1384 } else { 1385 rl_src = LoadValueWide(rl_src, kCoreReg); 1386 if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1387 // The registers are the same, so we would clobber it before the use. 1388 RegStorage temp_reg = AllocTemp(); 1389 OpRegCopy(temp_reg, rl_dest.reg); 1390 rl_src.reg.SetHighReg(temp_reg.GetReg()); 1391 } 1392 NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); 1393 1394 x86op = GetOpcode(op, rl_dest, rl_src, true); 1395 NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); 1396 FreeTemp(rl_src.reg); // ??? 1397 } 1398 return; 1399 } 1400 1401 // RHS is in memory. 1402 DCHECK((rl_src.location == kLocDalvikFrame) || 1403 (rl_src.location == kLocCompilerTemp)); 1404 int r_base = TargetReg(kSp).GetReg(); 1405 int displacement = SRegOffset(rl_src.s_reg_low); 1406 1407 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1408 LIR *lir = NewLIR3(x86op, Gen64Bit() ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), r_base, displacement + LOWORD_OFFSET); 1409 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1410 true /* is_load */, true /* is64bit */); 1411 if (!Gen64Bit()) { 1412 x86op = GetOpcode(op, rl_dest, rl_src, true); 1413 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); 1414 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1415 true /* is_load */, true /* is64bit */); 1416 } 1417} 1418 1419void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 1420 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 1421 if (rl_dest.location == kLocPhysReg) { 1422 // Ensure we are in a register pair 1423 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1424 1425 rl_src = UpdateLocWideTyped(rl_src, kCoreReg); 1426 GenLongRegOrMemOp(rl_result, rl_src, op); 1427 StoreFinalValueWide(rl_dest, rl_result); 1428 return; 1429 } 1430 1431 // It wasn't in registers, so it better be in memory. 1432 DCHECK((rl_dest.location == kLocDalvikFrame) || 1433 (rl_dest.location == kLocCompilerTemp)); 1434 rl_src = LoadValueWide(rl_src, kCoreReg); 1435 1436 // Operate directly into memory. 1437 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1438 int r_base = TargetReg(kSp).GetReg(); 1439 int displacement = SRegOffset(rl_dest.s_reg_low); 1440 1441 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 1442 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, 1443 Gen64Bit() ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); 1444 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1445 true /* is_load */, true /* is64bit */); 1446 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1447 false /* is_load */, true /* is64bit */); 1448 if (!Gen64Bit()) { 1449 x86op = GetOpcode(op, rl_dest, rl_src, true); 1450 lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); 1451 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1452 true /* is_load */, true /* is64bit */); 1453 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1454 false /* is_load */, true /* is64bit */); 1455 } 1456 FreeTemp(rl_src.reg); 1457} 1458 1459void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, 1460 RegLocation rl_src2, Instruction::Code op, 1461 bool is_commutative) { 1462 // Is this really a 2 operand operation? 1463 switch (op) { 1464 case Instruction::ADD_LONG_2ADDR: 1465 case Instruction::SUB_LONG_2ADDR: 1466 case Instruction::AND_LONG_2ADDR: 1467 case Instruction::OR_LONG_2ADDR: 1468 case Instruction::XOR_LONG_2ADDR: 1469 if (GenerateTwoOperandInstructions()) { 1470 GenLongArith(rl_dest, rl_src2, op); 1471 return; 1472 } 1473 break; 1474 1475 default: 1476 break; 1477 } 1478 1479 if (rl_dest.location == kLocPhysReg) { 1480 RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); 1481 1482 // We are about to clobber the LHS, so it needs to be a temp. 1483 rl_result = ForceTempWide(rl_result); 1484 1485 // Perform the operation using the RHS. 1486 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1487 GenLongRegOrMemOp(rl_result, rl_src2, op); 1488 1489 // And now record that the result is in the temp. 1490 StoreFinalValueWide(rl_dest, rl_result); 1491 return; 1492 } 1493 1494 // It wasn't in registers, so it better be in memory. 1495 DCHECK((rl_dest.location == kLocDalvikFrame) || 1496 (rl_dest.location == kLocCompilerTemp)); 1497 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1498 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1499 1500 // Get one of the source operands into temporary register. 1501 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1502 if (Gen64Bit()) { 1503 if (IsTemp(rl_src1.reg)) { 1504 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1505 } else if (is_commutative) { 1506 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1507 // We need at least one of them to be a temporary. 1508 if (!IsTemp(rl_src2.reg)) { 1509 rl_src1 = ForceTempWide(rl_src1); 1510 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1511 } else { 1512 GenLongRegOrMemOp(rl_src2, rl_src1, op); 1513 StoreFinalValueWide(rl_dest, rl_src2); 1514 return; 1515 } 1516 } else { 1517 // Need LHS to be the temp. 1518 rl_src1 = ForceTempWide(rl_src1); 1519 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1520 } 1521 } else { 1522 if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { 1523 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1524 } else if (is_commutative) { 1525 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1526 // We need at least one of them to be a temporary. 1527 if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { 1528 rl_src1 = ForceTempWide(rl_src1); 1529 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1530 } else { 1531 GenLongRegOrMemOp(rl_src2, rl_src1, op); 1532 StoreFinalValueWide(rl_dest, rl_src2); 1533 return; 1534 } 1535 } else { 1536 // Need LHS to be the temp. 1537 rl_src1 = ForceTempWide(rl_src1); 1538 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1539 } 1540 } 1541 1542 StoreFinalValueWide(rl_dest, rl_src1); 1543} 1544 1545void X86Mir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, 1546 RegLocation rl_src1, RegLocation rl_src2) { 1547 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1548} 1549 1550void X86Mir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, 1551 RegLocation rl_src1, RegLocation rl_src2) { 1552 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); 1553} 1554 1555void X86Mir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, 1556 RegLocation rl_src1, RegLocation rl_src2) { 1557 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1558} 1559 1560void X86Mir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, 1561 RegLocation rl_src1, RegLocation rl_src2) { 1562 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1563} 1564 1565void X86Mir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, 1566 RegLocation rl_src1, RegLocation rl_src2) { 1567 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1568} 1569 1570void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { 1571 if (Gen64Bit()) { 1572 rl_src = LoadValueWide(rl_src, kCoreReg); 1573 RegLocation rl_result; 1574 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1575 OpRegCopy(rl_result.reg, rl_src.reg); 1576 OpReg(kOpNot, rl_result.reg); 1577 StoreValueWide(rl_dest, rl_result); 1578 } else { 1579 LOG(FATAL) << "Unexpected use GenNotLong()"; 1580 } 1581} 1582 1583void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1584 RegLocation rl_src2, bool is_div) { 1585 if (!Gen64Bit()) { 1586 LOG(FATAL) << "Unexpected use GenDivRemLong()"; 1587 return; 1588 } 1589 1590 // We have to use fixed registers, so flush all the temps. 1591 FlushAllRegs(); 1592 LockCallTemps(); // Prepare for explicit register usage. 1593 1594 // Load LHS into RAX. 1595 LoadValueDirectWideFixed(rl_src1, rs_r0q); 1596 1597 // Load RHS into RCX. 1598 LoadValueDirectWideFixed(rl_src2, rs_r1q); 1599 1600 // Copy LHS sign bit into RDX. 1601 NewLIR0(kx86Cqo64Da); 1602 1603 // Handle division by zero case. 1604 GenDivZeroCheckWide(rs_r1q); 1605 1606 // Have to catch 0x8000000000000000/-1 case, or we will get an exception! 1607 NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); 1608 LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 1609 1610 // RHS is -1. 1611 LoadConstantWide(rs_r6q, 0x8000000000000000); 1612 NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r6q.GetReg()); 1613 LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 1614 1615 // In 0x8000000000000000/-1 case. 1616 if (!is_div) { 1617 // For DIV, RAX is already right. For REM, we need RDX 0. 1618 NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); 1619 } 1620 LIR* done = NewLIR1(kX86Jmp8, 0); 1621 1622 // Expected case. 1623 minus_one_branch->target = NewLIR0(kPseudoTargetLabel); 1624 minint_branch->target = minus_one_branch->target; 1625 NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); 1626 done->target = NewLIR0(kPseudoTargetLabel); 1627 1628 // Result is in RAX for div and RDX for rem. 1629 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; 1630 if (!is_div) { 1631 rl_result.reg.SetReg(r2q); 1632 } 1633 1634 StoreValueWide(rl_dest, rl_result); 1635} 1636 1637void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 1638 rl_src = LoadValueWide(rl_src, kCoreReg); 1639 RegLocation rl_result; 1640 if (Gen64Bit()) { 1641 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1642 OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); 1643 } else { 1644 rl_result = ForceTempWide(rl_src); 1645 if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && 1646 ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { 1647 // The registers are the same, so we would clobber it before the use. 1648 RegStorage temp_reg = AllocTemp(); 1649 OpRegCopy(temp_reg, rl_result.reg); 1650 rl_result.reg.SetHighReg(temp_reg.GetReg()); 1651 } 1652 OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow 1653 OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF 1654 OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh 1655 } 1656 StoreValueWide(rl_dest, rl_result); 1657} 1658 1659void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { 1660 DCHECK_EQ(kX86, cu_->instruction_set); 1661 X86OpCode opcode = kX86Bkpt; 1662 switch (op) { 1663 case kOpCmp: opcode = kX86Cmp32RT; break; 1664 case kOpMov: opcode = kX86Mov32RT; break; 1665 default: 1666 LOG(FATAL) << "Bad opcode: " << op; 1667 break; 1668 } 1669 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1670} 1671 1672void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { 1673 DCHECK_EQ(kX86_64, cu_->instruction_set); 1674 X86OpCode opcode = kX86Bkpt; 1675 if (Gen64Bit() && r_dest.Is64BitSolo()) { 1676 switch (op) { 1677 case kOpCmp: opcode = kX86Cmp64RT; break; 1678 case kOpMov: opcode = kX86Mov64RT; break; 1679 default: 1680 LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; 1681 break; 1682 } 1683 } else { 1684 switch (op) { 1685 case kOpCmp: opcode = kX86Cmp32RT; break; 1686 case kOpMov: opcode = kX86Mov32RT; break; 1687 default: 1688 LOG(FATAL) << "Bad opcode: " << op; 1689 break; 1690 } 1691 } 1692 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1693} 1694 1695/* 1696 * Generate array load 1697 */ 1698void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1699 RegLocation rl_index, RegLocation rl_dest, int scale) { 1700 RegisterClass reg_class = RegClassBySize(size); 1701 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1702 RegLocation rl_result; 1703 rl_array = LoadValue(rl_array, kRefReg); 1704 1705 int data_offset; 1706 if (size == k64 || size == kDouble) { 1707 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1708 } else { 1709 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1710 } 1711 1712 bool constant_index = rl_index.is_const; 1713 int32_t constant_index_value = 0; 1714 if (!constant_index) { 1715 rl_index = LoadValue(rl_index, kCoreReg); 1716 } else { 1717 constant_index_value = mir_graph_->ConstantValue(rl_index); 1718 // If index is constant, just fold it into the data offset 1719 data_offset += constant_index_value << scale; 1720 // treat as non array below 1721 rl_index.reg = RegStorage::InvalidReg(); 1722 } 1723 1724 /* null object? */ 1725 GenNullCheck(rl_array.reg, opt_flags); 1726 1727 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1728 if (constant_index) { 1729 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1730 } else { 1731 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1732 } 1733 } 1734 rl_result = EvalLoc(rl_dest, reg_class, true); 1735 LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); 1736 if ((size == k64) || (size == kDouble)) { 1737 StoreValueWide(rl_dest, rl_result); 1738 } else { 1739 StoreValue(rl_dest, rl_result); 1740 } 1741} 1742 1743/* 1744 * Generate array store 1745 * 1746 */ 1747void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1748 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1749 RegisterClass reg_class = RegClassBySize(size); 1750 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1751 int data_offset; 1752 1753 if (size == k64 || size == kDouble) { 1754 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1755 } else { 1756 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1757 } 1758 1759 rl_array = LoadValue(rl_array, kRefReg); 1760 bool constant_index = rl_index.is_const; 1761 int32_t constant_index_value = 0; 1762 if (!constant_index) { 1763 rl_index = LoadValue(rl_index, kCoreReg); 1764 } else { 1765 // If index is constant, just fold it into the data offset 1766 constant_index_value = mir_graph_->ConstantValue(rl_index); 1767 data_offset += constant_index_value << scale; 1768 // treat as non array below 1769 rl_index.reg = RegStorage::InvalidReg(); 1770 } 1771 1772 /* null object? */ 1773 GenNullCheck(rl_array.reg, opt_flags); 1774 1775 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1776 if (constant_index) { 1777 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1778 } else { 1779 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1780 } 1781 } 1782 if ((size == k64) || (size == kDouble)) { 1783 rl_src = LoadValueWide(rl_src, reg_class); 1784 } else { 1785 rl_src = LoadValue(rl_src, reg_class); 1786 } 1787 // If the src reg can't be byte accessed, move it to a temp first. 1788 if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) { 1789 RegStorage temp = AllocTemp(); 1790 OpRegCopy(temp, rl_src.reg); 1791 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); 1792 } else { 1793 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); 1794 } 1795 if (card_mark) { 1796 // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. 1797 if (!constant_index) { 1798 FreeTemp(rl_index.reg); 1799 } 1800 MarkGCCard(rl_src.reg, rl_array.reg); 1801 } 1802} 1803 1804RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1805 RegLocation rl_src, int shift_amount) { 1806 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1807 if (Gen64Bit()) { 1808 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1809 switch (opcode) { 1810 case Instruction::SHL_LONG: 1811 case Instruction::SHL_LONG_2ADDR: 1812 op = kOpLsl; 1813 break; 1814 case Instruction::SHR_LONG: 1815 case Instruction::SHR_LONG_2ADDR: 1816 op = kOpAsr; 1817 break; 1818 case Instruction::USHR_LONG: 1819 case Instruction::USHR_LONG_2ADDR: 1820 op = kOpLsr; 1821 break; 1822 default: 1823 LOG(FATAL) << "Unexpected case"; 1824 } 1825 OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); 1826 } else { 1827 switch (opcode) { 1828 case Instruction::SHL_LONG: 1829 case Instruction::SHL_LONG_2ADDR: 1830 DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. 1831 if (shift_amount == 32) { 1832 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1833 LoadConstant(rl_result.reg.GetLow(), 0); 1834 } else if (shift_amount > 31) { 1835 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1836 NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); 1837 LoadConstant(rl_result.reg.GetLow(), 0); 1838 } else { 1839 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); 1840 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1841 NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), 1842 shift_amount); 1843 NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); 1844 } 1845 break; 1846 case Instruction::SHR_LONG: 1847 case Instruction::SHR_LONG_2ADDR: 1848 if (shift_amount == 32) { 1849 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1850 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1851 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1852 } else if (shift_amount > 31) { 1853 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1854 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1855 NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1856 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1857 } else { 1858 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); 1859 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1860 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), 1861 shift_amount); 1862 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); 1863 } 1864 break; 1865 case Instruction::USHR_LONG: 1866 case Instruction::USHR_LONG_2ADDR: 1867 if (shift_amount == 32) { 1868 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1869 LoadConstant(rl_result.reg.GetHigh(), 0); 1870 } else if (shift_amount > 31) { 1871 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1872 NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1873 LoadConstant(rl_result.reg.GetHigh(), 0); 1874 } else { 1875 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); 1876 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1877 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), 1878 shift_amount); 1879 NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); 1880 } 1881 break; 1882 default: 1883 LOG(FATAL) << "Unexpected case"; 1884 } 1885 } 1886 return rl_result; 1887} 1888 1889void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1890 RegLocation rl_src, RegLocation rl_shift) { 1891 // Per spec, we only care about low 6 bits of shift amount. 1892 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; 1893 if (shift_amount == 0) { 1894 rl_src = LoadValueWide(rl_src, kCoreReg); 1895 StoreValueWide(rl_dest, rl_src); 1896 return; 1897 } else if (shift_amount == 1 && 1898 (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { 1899 // Need to handle this here to avoid calling StoreValueWide twice. 1900 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); 1901 return; 1902 } 1903 if (BadOverlap(rl_src, rl_dest)) { 1904 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); 1905 return; 1906 } 1907 rl_src = LoadValueWide(rl_src, kCoreReg); 1908 RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); 1909 StoreValueWide(rl_dest, rl_result); 1910} 1911 1912void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, 1913 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1914 bool isConstSuccess = false; 1915 switch (opcode) { 1916 case Instruction::ADD_LONG: 1917 case Instruction::AND_LONG: 1918 case Instruction::OR_LONG: 1919 case Instruction::XOR_LONG: 1920 if (rl_src2.is_const) { 1921 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1922 } else { 1923 DCHECK(rl_src1.is_const); 1924 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1925 } 1926 break; 1927 case Instruction::SUB_LONG: 1928 case Instruction::SUB_LONG_2ADDR: 1929 if (rl_src2.is_const) { 1930 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1931 } else { 1932 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1933 isConstSuccess = true; 1934 } 1935 break; 1936 case Instruction::ADD_LONG_2ADDR: 1937 case Instruction::OR_LONG_2ADDR: 1938 case Instruction::XOR_LONG_2ADDR: 1939 case Instruction::AND_LONG_2ADDR: 1940 if (rl_src2.is_const) { 1941 if (GenerateTwoOperandInstructions()) { 1942 isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); 1943 } else { 1944 isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1945 } 1946 } else { 1947 DCHECK(rl_src1.is_const); 1948 isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1949 } 1950 break; 1951 default: 1952 isConstSuccess = false; 1953 break; 1954 } 1955 1956 if (!isConstSuccess) { 1957 // Default - bail to non-const handler. 1958 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1959 } 1960} 1961 1962bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { 1963 switch (op) { 1964 case Instruction::AND_LONG_2ADDR: 1965 case Instruction::AND_LONG: 1966 return value == -1; 1967 case Instruction::OR_LONG: 1968 case Instruction::OR_LONG_2ADDR: 1969 case Instruction::XOR_LONG: 1970 case Instruction::XOR_LONG_2ADDR: 1971 return value == 0; 1972 default: 1973 return false; 1974 } 1975} 1976 1977X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 1978 bool is_high_op) { 1979 bool rhs_in_mem = rhs.location != kLocPhysReg; 1980 bool dest_in_mem = dest.location != kLocPhysReg; 1981 bool is64Bit = Gen64Bit(); 1982 DCHECK(!rhs_in_mem || !dest_in_mem); 1983 switch (op) { 1984 case Instruction::ADD_LONG: 1985 case Instruction::ADD_LONG_2ADDR: 1986 if (dest_in_mem) { 1987 return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; 1988 } else if (rhs_in_mem) { 1989 return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; 1990 } 1991 return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; 1992 case Instruction::SUB_LONG: 1993 case Instruction::SUB_LONG_2ADDR: 1994 if (dest_in_mem) { 1995 return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; 1996 } else if (rhs_in_mem) { 1997 return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; 1998 } 1999 return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; 2000 case Instruction::AND_LONG_2ADDR: 2001 case Instruction::AND_LONG: 2002 if (dest_in_mem) { 2003 return is64Bit ? kX86And64MR : kX86And32MR; 2004 } 2005 if (is64Bit) { 2006 return rhs_in_mem ? kX86And64RM : kX86And64RR; 2007 } 2008 return rhs_in_mem ? kX86And32RM : kX86And32RR; 2009 case Instruction::OR_LONG: 2010 case Instruction::OR_LONG_2ADDR: 2011 if (dest_in_mem) { 2012 return is64Bit ? kX86Or64MR : kX86Or32MR; 2013 } 2014 if (is64Bit) { 2015 return rhs_in_mem ? kX86Or64RM : kX86Or64RR; 2016 } 2017 return rhs_in_mem ? kX86Or32RM : kX86Or32RR; 2018 case Instruction::XOR_LONG: 2019 case Instruction::XOR_LONG_2ADDR: 2020 if (dest_in_mem) { 2021 return is64Bit ? kX86Xor64MR : kX86Xor32MR; 2022 } 2023 if (is64Bit) { 2024 return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; 2025 } 2026 return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; 2027 default: 2028 LOG(FATAL) << "Unexpected opcode: " << op; 2029 return kX86Add32RR; 2030 } 2031} 2032 2033X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, 2034 int32_t value) { 2035 bool in_mem = loc.location != kLocPhysReg; 2036 bool is64Bit = Gen64Bit(); 2037 bool byte_imm = IS_SIMM8(value); 2038 DCHECK(in_mem || !loc.reg.IsFloat()); 2039 switch (op) { 2040 case Instruction::ADD_LONG: 2041 case Instruction::ADD_LONG_2ADDR: 2042 if (byte_imm) { 2043 if (in_mem) { 2044 return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; 2045 } 2046 return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; 2047 } 2048 if (in_mem) { 2049 return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; 2050 } 2051 return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; 2052 case Instruction::SUB_LONG: 2053 case Instruction::SUB_LONG_2ADDR: 2054 if (byte_imm) { 2055 if (in_mem) { 2056 return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; 2057 } 2058 return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; 2059 } 2060 if (in_mem) { 2061 return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; 2062 } 2063 return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; 2064 case Instruction::AND_LONG_2ADDR: 2065 case Instruction::AND_LONG: 2066 if (byte_imm) { 2067 if (is64Bit) { 2068 return in_mem ? kX86And64MI8 : kX86And64RI8; 2069 } 2070 return in_mem ? kX86And32MI8 : kX86And32RI8; 2071 } 2072 if (is64Bit) { 2073 return in_mem ? kX86And64MI : kX86And64RI; 2074 } 2075 return in_mem ? kX86And32MI : kX86And32RI; 2076 case Instruction::OR_LONG: 2077 case Instruction::OR_LONG_2ADDR: 2078 if (byte_imm) { 2079 if (is64Bit) { 2080 return in_mem ? kX86Or64MI8 : kX86Or64RI8; 2081 } 2082 return in_mem ? kX86Or32MI8 : kX86Or32RI8; 2083 } 2084 if (is64Bit) { 2085 return in_mem ? kX86Or64MI : kX86Or64RI; 2086 } 2087 return in_mem ? kX86Or32MI : kX86Or32RI; 2088 case Instruction::XOR_LONG: 2089 case Instruction::XOR_LONG_2ADDR: 2090 if (byte_imm) { 2091 if (is64Bit) { 2092 return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; 2093 } 2094 return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; 2095 } 2096 if (is64Bit) { 2097 return in_mem ? kX86Xor64MI : kX86Xor64RI; 2098 } 2099 return in_mem ? kX86Xor32MI : kX86Xor32RI; 2100 default: 2101 LOG(FATAL) << "Unexpected opcode: " << op; 2102 return kX86Add32MI; 2103 } 2104} 2105 2106bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 2107 DCHECK(rl_src.is_const); 2108 int64_t val = mir_graph_->ConstantValueWide(rl_src); 2109 2110 if (Gen64Bit()) { 2111 // We can do with imm only if it fits 32 bit 2112 if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { 2113 return false; 2114 } 2115 2116 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2117 2118 if ((rl_dest.location == kLocDalvikFrame) || 2119 (rl_dest.location == kLocCompilerTemp)) { 2120 int r_base = TargetReg(kSp).GetReg(); 2121 int displacement = SRegOffset(rl_dest.s_reg_low); 2122 2123 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2124 X86OpCode x86op = GetOpcode(op, rl_dest, false, val); 2125 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); 2126 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2127 true /* is_load */, true /* is64bit */); 2128 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2129 false /* is_load */, true /* is64bit */); 2130 return true; 2131 } 2132 2133 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2134 DCHECK_EQ(rl_result.location, kLocPhysReg); 2135 DCHECK(!rl_result.reg.IsFloat()); 2136 2137 X86OpCode x86op = GetOpcode(op, rl_result, false, val); 2138 NewLIR2(x86op, rl_result.reg.GetReg(), val); 2139 2140 StoreValueWide(rl_dest, rl_result); 2141 return true; 2142 } 2143 2144 int32_t val_lo = Low32Bits(val); 2145 int32_t val_hi = High32Bits(val); 2146 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2147 2148 // Can we just do this into memory? 2149 if ((rl_dest.location == kLocDalvikFrame) || 2150 (rl_dest.location == kLocCompilerTemp)) { 2151 int r_base = TargetReg(kSp).GetReg(); 2152 int displacement = SRegOffset(rl_dest.s_reg_low); 2153 2154 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2155 if (!IsNoOp(op, val_lo)) { 2156 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 2157 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); 2158 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2159 true /* is_load */, true /* is64bit */); 2160 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 2161 false /* is_load */, true /* is64bit */); 2162 } 2163 if (!IsNoOp(op, val_hi)) { 2164 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 2165 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); 2166 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 2167 true /* is_load */, true /* is64bit */); 2168 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 2169 false /* is_load */, true /* is64bit */); 2170 } 2171 return true; 2172 } 2173 2174 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2175 DCHECK_EQ(rl_result.location, kLocPhysReg); 2176 DCHECK(!rl_result.reg.IsFloat()); 2177 2178 if (!IsNoOp(op, val_lo)) { 2179 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 2180 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 2181 } 2182 if (!IsNoOp(op, val_hi)) { 2183 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 2184 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 2185 } 2186 StoreValueWide(rl_dest, rl_result); 2187 return true; 2188} 2189 2190bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, 2191 RegLocation rl_src2, Instruction::Code op) { 2192 DCHECK(rl_src2.is_const); 2193 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 2194 2195 if (Gen64Bit()) { 2196 // We can do with imm only if it fits 32 bit 2197 if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { 2198 return false; 2199 } 2200 if (rl_dest.location == kLocPhysReg && 2201 rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { 2202 X86OpCode x86op = GetOpcode(op, rl_dest, false, val); 2203 OpRegCopy(rl_dest.reg, rl_src1.reg); 2204 NewLIR2(x86op, rl_dest.reg.GetReg(), val); 2205 StoreFinalValueWide(rl_dest, rl_dest); 2206 return true; 2207 } 2208 2209 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2210 // We need the values to be in a temporary 2211 RegLocation rl_result = ForceTempWide(rl_src1); 2212 2213 X86OpCode x86op = GetOpcode(op, rl_result, false, val); 2214 NewLIR2(x86op, rl_result.reg.GetReg(), val); 2215 2216 StoreFinalValueWide(rl_dest, rl_result); 2217 return true; 2218 } 2219 2220 int32_t val_lo = Low32Bits(val); 2221 int32_t val_hi = High32Bits(val); 2222 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 2223 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 2224 2225 // Can we do this directly into the destination registers? 2226 if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && 2227 rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && 2228 rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { 2229 if (!IsNoOp(op, val_lo)) { 2230 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 2231 NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); 2232 } 2233 if (!IsNoOp(op, val_hi)) { 2234 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 2235 NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); 2236 } 2237 2238 StoreFinalValueWide(rl_dest, rl_dest); 2239 return true; 2240 } 2241 2242 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2243 DCHECK_EQ(rl_src1.location, kLocPhysReg); 2244 2245 // We need the values to be in a temporary 2246 RegLocation rl_result = ForceTempWide(rl_src1); 2247 if (!IsNoOp(op, val_lo)) { 2248 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 2249 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 2250 } 2251 if (!IsNoOp(op, val_hi)) { 2252 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 2253 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 2254 } 2255 2256 StoreFinalValueWide(rl_dest, rl_result); 2257 return true; 2258} 2259 2260// For final classes there are no sub-classes to check and so we can answer the instance-of 2261// question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. 2262void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 2263 RegLocation rl_dest, RegLocation rl_src) { 2264 RegLocation object = LoadValue(rl_src, kRefReg); 2265 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 2266 RegStorage result_reg = rl_result.reg; 2267 2268 // For 32-bit, SETcc only works with EAX..EDX. 2269 if (result_reg == object.reg || !IsByteRegister(result_reg)) { 2270 result_reg = AllocateByteRegister(); 2271 } 2272 2273 // Assume that there is no match. 2274 LoadConstant(result_reg, 0); 2275 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 2276 2277 // We will use this register to compare to memory below. 2278 // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). 2279 // For this reason, force allocation of a 32 bit register to use, so that the 2280 // compare to memory will be done using a 32 bit comparision. 2281 // The LoadRefDisp(s) below will work normally, even in 64 bit mode. 2282 RegStorage check_class = AllocTemp(); 2283 2284 // If Method* is already in a register, we can save a copy. 2285 RegLocation rl_method = mir_graph_->GetMethodLoc(); 2286 int32_t offset_of_type = mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 2287 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 2288 2289 if (rl_method.location == kLocPhysReg) { 2290 if (use_declaring_class) { 2291 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2292 check_class); 2293 } else { 2294 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2295 check_class); 2296 LoadRefDisp(check_class, offset_of_type, check_class); 2297 } 2298 } else { 2299 LoadCurrMethodDirect(check_class); 2300 if (use_declaring_class) { 2301 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2302 check_class); 2303 } else { 2304 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2305 check_class); 2306 LoadRefDisp(check_class, offset_of_type, check_class); 2307 } 2308 } 2309 2310 // Compare the computed class to the class in the object. 2311 DCHECK_EQ(object.location, kLocPhysReg); 2312 OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); 2313 2314 // Set the low byte of the result to 0 or 1 from the compare condition code. 2315 NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); 2316 2317 LIR* target = NewLIR0(kPseudoTargetLabel); 2318 null_branchover->target = target; 2319 FreeTemp(check_class); 2320 if (IsTemp(result_reg)) { 2321 OpRegCopy(rl_result.reg, result_reg); 2322 FreeTemp(result_reg); 2323 } 2324 StoreValue(rl_dest, rl_result); 2325} 2326 2327void X86Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 2328 bool type_known_abstract, bool use_declaring_class, 2329 bool can_assume_type_is_in_dex_cache, 2330 uint32_t type_idx, RegLocation rl_dest, 2331 RegLocation rl_src) { 2332 FlushAllRegs(); 2333 // May generate a call - use explicit registers. 2334 LockCallTemps(); 2335 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 gets current Method*. 2336 RegStorage class_reg = TargetReg(kArg2); // kArg2 will hold the Class*. 2337 // Reference must end up in kArg0. 2338 if (needs_access_check) { 2339 // Check we have access to type_idx and if not throw IllegalAccessError, 2340 // Caller function returns Class* in kArg0. 2341 if (cu_->target64) { 2342 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 2343 type_idx, true); 2344 } else { 2345 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 2346 type_idx, true); 2347 } 2348 OpRegCopy(class_reg, TargetReg(kRet0)); 2349 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2350 } else if (use_declaring_class) { 2351 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2352 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2353 class_reg); 2354 } else { 2355 // Load dex cache entry into class_reg (kArg2). 2356 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2357 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2358 class_reg); 2359 int32_t offset_of_type = 2360 mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 2361 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 2362 LoadRefDisp(class_reg, offset_of_type, class_reg); 2363 if (!can_assume_type_is_in_dex_cache) { 2364 // Need to test presence of type in dex cache at runtime. 2365 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 2366 // Type is not resolved. Call out to helper, which will return resolved type in kRet0/kArg0. 2367 if (cu_->target64) { 2368 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx, true); 2369 } else { 2370 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); 2371 } 2372 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path. 2373 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* Reload Ref. */ 2374 // Rejoin code paths 2375 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 2376 hop_branch->target = hop_target; 2377 } 2378 } 2379 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result. */ 2380 RegLocation rl_result = GetReturn(kRefReg); 2381 2382 // On x86-64 kArg0 is not EAX, so we have to copy ref from kArg0 to EAX. 2383 if (Gen64Bit()) { 2384 OpRegCopy(rl_result.reg, TargetReg(kArg0)); 2385 } 2386 2387 // For 32-bit, SETcc only works with EAX..EDX. 2388 DCHECK_LT(rl_result.reg.GetRegNum(), 4); 2389 2390 // Is the class NULL? 2391 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 2392 2393 /* Load object->klass_. */ 2394 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 2395 LoadRefDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 2396 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class. */ 2397 LIR* branchover = nullptr; 2398 if (type_known_final) { 2399 // Ensure top 3 bytes of result are 0. 2400 LoadConstant(rl_result.reg, 0); 2401 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); 2402 // Set the low byte of the result to 0 or 1 from the compare condition code. 2403 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondEq); 2404 } else { 2405 if (!type_known_abstract) { 2406 LoadConstant(rl_result.reg, 1); // Assume result succeeds. 2407 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 2408 } 2409 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 2410 if (cu_->target64) { 2411 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)); 2412 } else { 2413 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 2414 } 2415 } 2416 // TODO: only clobber when type isn't final? 2417 ClobberCallerSave(); 2418 /* Branch targets here. */ 2419 LIR* target = NewLIR0(kPseudoTargetLabel); 2420 StoreValue(rl_dest, rl_result); 2421 branch1->target = target; 2422 if (branchover != nullptr) { 2423 branchover->target = target; 2424 } 2425} 2426 2427void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 2428 RegLocation rl_lhs, RegLocation rl_rhs) { 2429 OpKind op = kOpBkpt; 2430 bool is_div_rem = false; 2431 bool unary = false; 2432 bool shift_op = false; 2433 bool is_two_addr = false; 2434 RegLocation rl_result; 2435 switch (opcode) { 2436 case Instruction::NEG_INT: 2437 op = kOpNeg; 2438 unary = true; 2439 break; 2440 case Instruction::NOT_INT: 2441 op = kOpMvn; 2442 unary = true; 2443 break; 2444 case Instruction::ADD_INT_2ADDR: 2445 is_two_addr = true; 2446 // Fallthrough 2447 case Instruction::ADD_INT: 2448 op = kOpAdd; 2449 break; 2450 case Instruction::SUB_INT_2ADDR: 2451 is_two_addr = true; 2452 // Fallthrough 2453 case Instruction::SUB_INT: 2454 op = kOpSub; 2455 break; 2456 case Instruction::MUL_INT_2ADDR: 2457 is_two_addr = true; 2458 // Fallthrough 2459 case Instruction::MUL_INT: 2460 op = kOpMul; 2461 break; 2462 case Instruction::DIV_INT_2ADDR: 2463 is_two_addr = true; 2464 // Fallthrough 2465 case Instruction::DIV_INT: 2466 op = kOpDiv; 2467 is_div_rem = true; 2468 break; 2469 /* NOTE: returns in kArg1 */ 2470 case Instruction::REM_INT_2ADDR: 2471 is_two_addr = true; 2472 // Fallthrough 2473 case Instruction::REM_INT: 2474 op = kOpRem; 2475 is_div_rem = true; 2476 break; 2477 case Instruction::AND_INT_2ADDR: 2478 is_two_addr = true; 2479 // Fallthrough 2480 case Instruction::AND_INT: 2481 op = kOpAnd; 2482 break; 2483 case Instruction::OR_INT_2ADDR: 2484 is_two_addr = true; 2485 // Fallthrough 2486 case Instruction::OR_INT: 2487 op = kOpOr; 2488 break; 2489 case Instruction::XOR_INT_2ADDR: 2490 is_two_addr = true; 2491 // Fallthrough 2492 case Instruction::XOR_INT: 2493 op = kOpXor; 2494 break; 2495 case Instruction::SHL_INT_2ADDR: 2496 is_two_addr = true; 2497 // Fallthrough 2498 case Instruction::SHL_INT: 2499 shift_op = true; 2500 op = kOpLsl; 2501 break; 2502 case Instruction::SHR_INT_2ADDR: 2503 is_two_addr = true; 2504 // Fallthrough 2505 case Instruction::SHR_INT: 2506 shift_op = true; 2507 op = kOpAsr; 2508 break; 2509 case Instruction::USHR_INT_2ADDR: 2510 is_two_addr = true; 2511 // Fallthrough 2512 case Instruction::USHR_INT: 2513 shift_op = true; 2514 op = kOpLsr; 2515 break; 2516 default: 2517 LOG(FATAL) << "Invalid word arith op: " << opcode; 2518 } 2519 2520 // Can we convert to a two address instruction? 2521 if (!is_two_addr && 2522 (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == 2523 mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { 2524 is_two_addr = true; 2525 } 2526 2527 if (!GenerateTwoOperandInstructions()) { 2528 is_two_addr = false; 2529 } 2530 2531 // Get the div/rem stuff out of the way. 2532 if (is_div_rem) { 2533 rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); 2534 StoreValue(rl_dest, rl_result); 2535 return; 2536 } 2537 2538 // If we generate any memory access below, it will reference a dalvik reg. 2539 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2540 2541 if (unary) { 2542 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2543 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2544 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2545 OpRegReg(op, rl_result.reg, rl_lhs.reg); 2546 } else { 2547 if (shift_op) { 2548 // X86 doesn't require masking and must use ECX. 2549 RegStorage t_reg = TargetReg(kCount); // rCX 2550 LoadValueDirectFixed(rl_rhs, t_reg); 2551 if (is_two_addr) { 2552 // Can we do this directly into memory? 2553 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2554 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2555 if (rl_result.location != kLocPhysReg) { 2556 // Okay, we can do this into memory 2557 OpMemReg(op, rl_result, t_reg.GetReg()); 2558 FreeTemp(t_reg); 2559 return; 2560 } else if (!rl_result.reg.IsFloat()) { 2561 // Can do this directly into the result register 2562 OpRegReg(op, rl_result.reg, t_reg); 2563 FreeTemp(t_reg); 2564 StoreFinalValue(rl_dest, rl_result); 2565 return; 2566 } 2567 } 2568 // Three address form, or we can't do directly. 2569 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2570 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2571 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); 2572 FreeTemp(t_reg); 2573 } else { 2574 // Multiply is 3 operand only (sort of). 2575 if (is_two_addr && op != kOpMul) { 2576 // Can we do this directly into memory? 2577 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2578 if (rl_result.location == kLocPhysReg) { 2579 // Ensure res is in a core reg 2580 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2581 // Can we do this from memory directly? 2582 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2583 if (rl_rhs.location != kLocPhysReg) { 2584 OpRegMem(op, rl_result.reg, rl_rhs); 2585 StoreFinalValue(rl_dest, rl_result); 2586 return; 2587 } else if (!rl_rhs.reg.IsFloat()) { 2588 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2589 StoreFinalValue(rl_dest, rl_result); 2590 return; 2591 } 2592 } 2593 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2594 // It might happen rl_rhs and rl_dest are the same VR 2595 // in this case rl_dest is in reg after LoadValue while 2596 // rl_result is not updated yet, so do this 2597 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2598 if (rl_result.location != kLocPhysReg) { 2599 // Okay, we can do this into memory. 2600 OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); 2601 return; 2602 } else if (!rl_result.reg.IsFloat()) { 2603 // Can do this directly into the result register. 2604 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2605 StoreFinalValue(rl_dest, rl_result); 2606 return; 2607 } else { 2608 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2609 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2610 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2611 } 2612 } else { 2613 // Try to use reg/memory instructions. 2614 rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); 2615 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2616 // We can't optimize with FP registers. 2617 if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { 2618 // Something is difficult, so fall back to the standard case. 2619 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2620 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2621 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2622 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2623 } else { 2624 // We can optimize by moving to result and using memory operands. 2625 if (rl_rhs.location != kLocPhysReg) { 2626 // Force LHS into result. 2627 // We should be careful with order here 2628 // If rl_dest and rl_lhs points to the same VR we should load first 2629 // If the are different we should find a register first for dest 2630 if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == 2631 mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { 2632 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2633 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2634 // No-op if these are the same. 2635 OpRegCopy(rl_result.reg, rl_lhs.reg); 2636 } else { 2637 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2638 LoadValueDirect(rl_lhs, rl_result.reg); 2639 } 2640 OpRegMem(op, rl_result.reg, rl_rhs); 2641 } else if (rl_lhs.location != kLocPhysReg) { 2642 // RHS is in a register; LHS is in memory. 2643 if (op != kOpSub) { 2644 // Force RHS into result and operate on memory. 2645 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2646 OpRegCopy(rl_result.reg, rl_rhs.reg); 2647 OpRegMem(op, rl_result.reg, rl_lhs); 2648 } else { 2649 // Subtraction isn't commutative. 2650 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2651 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2652 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2653 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2654 } 2655 } else { 2656 // Both are in registers. 2657 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2658 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2659 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2660 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2661 } 2662 } 2663 } 2664 } 2665 } 2666 StoreValue(rl_dest, rl_result); 2667} 2668 2669bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { 2670 // If we have non-core registers, then we can't do good things. 2671 if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { 2672 return false; 2673 } 2674 if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { 2675 return false; 2676 } 2677 2678 // Everything will be fine :-). 2679 return true; 2680} 2681 2682void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 2683 if (!Gen64Bit()) { 2684 Mir2Lir::GenIntToLong(rl_dest, rl_src); 2685 return; 2686 } 2687 rl_src = UpdateLoc(rl_src); 2688 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 2689 if (rl_src.location == kLocPhysReg) { 2690 NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 2691 } else { 2692 int displacement = SRegOffset(rl_src.s_reg_low); 2693 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2694 LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(), 2695 displacement + LOWORD_OFFSET); 2696 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 2697 true /* is_load */, true /* is_64bit */); 2698 } 2699 StoreValueWide(rl_dest, rl_result); 2700} 2701 2702void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 2703 RegLocation rl_src1, RegLocation rl_shift) { 2704 if (!Gen64Bit()) { 2705 Mir2Lir::GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); 2706 return; 2707 } 2708 2709 bool is_two_addr = false; 2710 OpKind op = kOpBkpt; 2711 RegLocation rl_result; 2712 2713 switch (opcode) { 2714 case Instruction::SHL_LONG_2ADDR: 2715 is_two_addr = true; 2716 // Fallthrough 2717 case Instruction::SHL_LONG: 2718 op = kOpLsl; 2719 break; 2720 case Instruction::SHR_LONG_2ADDR: 2721 is_two_addr = true; 2722 // Fallthrough 2723 case Instruction::SHR_LONG: 2724 op = kOpAsr; 2725 break; 2726 case Instruction::USHR_LONG_2ADDR: 2727 is_two_addr = true; 2728 // Fallthrough 2729 case Instruction::USHR_LONG: 2730 op = kOpLsr; 2731 break; 2732 default: 2733 op = kOpBkpt; 2734 } 2735 2736 // X86 doesn't require masking and must use ECX. 2737 RegStorage t_reg = TargetReg(kCount); // rCX 2738 LoadValueDirectFixed(rl_shift, t_reg); 2739 if (is_two_addr) { 2740 // Can we do this directly into memory? 2741 rl_result = UpdateLocWideTyped(rl_dest, kCoreReg); 2742 if (rl_result.location != kLocPhysReg) { 2743 // Okay, we can do this into memory 2744 ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); 2745 OpMemReg(op, rl_result, t_reg.GetReg()); 2746 } else if (!rl_result.reg.IsFloat()) { 2747 // Can do this directly into the result register 2748 OpRegReg(op, rl_result.reg, t_reg); 2749 StoreFinalValueWide(rl_dest, rl_result); 2750 } 2751 } else { 2752 // Three address form, or we can't do directly. 2753 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 2754 rl_result = EvalLocWide(rl_dest, kCoreReg, true); 2755 OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); 2756 StoreFinalValueWide(rl_dest, rl_result); 2757 } 2758 2759 FreeTemp(t_reg); 2760} 2761 2762} // namespace art 2763