int_x86.cc revision e0ccdc0dd166136cd43e5f54201179a4496d33e8
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* This file contains codegen for the X86 ISA */ 18 19#include "codegen_x86.h" 20#include "dex/quick/mir_to_lir-inl.h" 21#include "mirror/array.h" 22#include "x86_lir.h" 23 24namespace art { 25 26/* 27 * Compare two 64-bit values 28 * x = y return 0 29 * x < y return -1 30 * x > y return 1 31 */ 32void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, 33 RegLocation rl_src2) { 34 FlushAllRegs(); 35 LockCallTemps(); // Prepare for explicit register usage 36 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 37 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 38 LoadValueDirectWideFixed(rl_src1, r_tmp1); 39 LoadValueDirectWideFixed(rl_src2, r_tmp2); 40 // Compute (r1:r0) = (r1:r0) - (r3:r2) 41 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 42 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 43 NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 44 NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); 45 OpReg(kOpNeg, rs_r2); // r2 = -r2 46 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF 47 NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 48 NewLIR2(kX86Movzx8RR, r0, r0); 49 OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 50 RegLocation rl_result = LocCReturn(); 51 StoreValue(rl_dest, rl_result); 52} 53 54X86ConditionCode X86ConditionEncoding(ConditionCode cond) { 55 switch (cond) { 56 case kCondEq: return kX86CondEq; 57 case kCondNe: return kX86CondNe; 58 case kCondCs: return kX86CondC; 59 case kCondCc: return kX86CondNc; 60 case kCondUlt: return kX86CondC; 61 case kCondUge: return kX86CondNc; 62 case kCondMi: return kX86CondS; 63 case kCondPl: return kX86CondNs; 64 case kCondVs: return kX86CondO; 65 case kCondVc: return kX86CondNo; 66 case kCondHi: return kX86CondA; 67 case kCondLs: return kX86CondBe; 68 case kCondGe: return kX86CondGe; 69 case kCondLt: return kX86CondL; 70 case kCondGt: return kX86CondG; 71 case kCondLe: return kX86CondLe; 72 case kCondAl: 73 case kCondNv: LOG(FATAL) << "Should not reach here"; 74 } 75 return kX86CondO; 76} 77 78LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { 79 NewLIR2(kX86Cmp32RR, src1.GetReg(), src2.GetReg()); 80 X86ConditionCode cc = X86ConditionEncoding(cond); 81 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , 82 cc); 83 branch->target = target; 84 return branch; 85} 86 87LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, 88 int check_value, LIR* target) { 89 if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { 90 // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode 91 NewLIR2(kX86Test32RR, reg.GetReg(), reg.GetReg()); 92 } else { 93 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); 94 } 95 X86ConditionCode cc = X86ConditionEncoding(cond); 96 LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); 97 branch->target = target; 98 return branch; 99} 100 101LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 102 // If src or dest is a pair, we'll be using low reg. 103 if (r_dest.IsPair()) { 104 r_dest = r_dest.GetLow(); 105 } 106 if (r_src.IsPair()) { 107 r_src = r_src.GetLow(); 108 } 109 if (r_dest.IsFloat() || r_src.IsFloat()) 110 return OpFpRegCopy(r_dest, r_src); 111 LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, 112 r_dest.GetReg(), r_src.GetReg()); 113 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 114 res->flags.is_nop = true; 115 } 116 return res; 117} 118 119void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 120 if (r_dest != r_src) { 121 LIR *res = OpRegCopyNoInsert(r_dest, r_src); 122 AppendLIR(res); 123 } 124} 125 126void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { 127 if (r_dest != r_src) { 128 bool dest_fp = r_dest.IsFloat(); 129 bool src_fp = r_src.IsFloat(); 130 if (dest_fp) { 131 if (src_fp) { 132 OpRegCopy(r_dest, r_src); 133 } else { 134 // TODO: Prevent this from happening in the code. The result is often 135 // unused or could have been loaded more easily from memory. 136 if (!r_src.IsPair()) { 137 DCHECK(!r_dest.IsPair()); 138 NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); 139 } else { 140 NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); 141 RegStorage r_tmp = AllocTempDouble(); 142 NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); 143 NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); 144 FreeTemp(r_tmp); 145 } 146 } 147 } else { 148 if (src_fp) { 149 if (!r_dest.IsPair()) { 150 DCHECK(!r_src.IsPair()); 151 NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); 152 } else { 153 NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); 154 RegStorage temp_reg = AllocTempDouble(); 155 NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); 156 NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); 157 NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); 158 } 159 } else { 160 DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); 161 if (!r_src.IsPair()) { 162 // Just copy the register directly. 163 OpRegCopy(r_dest, r_src); 164 } else { 165 // Handle overlap 166 if (r_src.GetHighReg() == r_dest.GetLowReg() && 167 r_src.GetLowReg() == r_dest.GetHighReg()) { 168 // Deal with cycles. 169 RegStorage temp_reg = AllocTemp(); 170 OpRegCopy(temp_reg, r_dest.GetHigh()); 171 OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); 172 OpRegCopy(r_dest.GetLow(), temp_reg); 173 FreeTemp(temp_reg); 174 } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { 175 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 176 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 177 } else { 178 OpRegCopy(r_dest.GetLow(), r_src.GetLow()); 179 OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); 180 } 181 } 182 } 183 } 184 } 185} 186 187void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { 188 RegLocation rl_result; 189 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); 190 RegLocation rl_dest = mir_graph_->GetDest(mir); 191 // Avoid using float regs here. 192 RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; 193 RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; 194 rl_src = LoadValue(rl_src, src_reg_class); 195 ConditionCode ccode = mir->meta.ccode; 196 197 // The kMirOpSelect has two variants, one for constants and one for moves. 198 const bool is_constant_case = (mir->ssa_rep->num_uses == 1); 199 200 if (is_constant_case) { 201 int true_val = mir->dalvikInsn.vB; 202 int false_val = mir->dalvikInsn.vC; 203 rl_result = EvalLoc(rl_dest, result_reg_class, true); 204 205 /* 206 * For ccode == kCondEq: 207 * 208 * 1) When the true case is zero and result_reg is not same as src_reg: 209 * xor result_reg, result_reg 210 * cmp $0, src_reg 211 * mov t1, $false_case 212 * cmovnz result_reg, t1 213 * 2) When the false case is zero and result_reg is not same as src_reg: 214 * xor result_reg, result_reg 215 * cmp $0, src_reg 216 * mov t1, $true_case 217 * cmovz result_reg, t1 218 * 3) All other cases (we do compare first to set eflags): 219 * cmp $0, src_reg 220 * mov result_reg, $false_case 221 * mov t1, $true_case 222 * cmovz result_reg, t1 223 */ 224 // FIXME: depending on how you use registers you could get a false != mismatch when dealing 225 // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). 226 const bool result_reg_same_as_src = 227 (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg()); 228 const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); 229 const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); 230 const bool catch_all_case = !(true_zero_case || false_zero_case); 231 232 if (true_zero_case || false_zero_case) { 233 OpRegReg(kOpXor, rl_result.reg, rl_result.reg); 234 } 235 236 if (true_zero_case || false_zero_case || catch_all_case) { 237 OpRegImm(kOpCmp, rl_src.reg, 0); 238 } 239 240 if (catch_all_case) { 241 OpRegImm(kOpMov, rl_result.reg, false_val); 242 } 243 244 if (true_zero_case || false_zero_case || catch_all_case) { 245 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; 246 int immediateForTemp = true_zero_case ? false_val : true_val; 247 RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); 248 OpRegImm(kOpMov, temp1_reg, immediateForTemp); 249 250 OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); 251 252 FreeTemp(temp1_reg); 253 } 254 } else { 255 RegLocation rl_true = mir_graph_->GetSrc(mir, 1); 256 RegLocation rl_false = mir_graph_->GetSrc(mir, 2); 257 rl_true = LoadValue(rl_true, result_reg_class); 258 rl_false = LoadValue(rl_false, result_reg_class); 259 rl_result = EvalLoc(rl_dest, result_reg_class, true); 260 261 /* 262 * For ccode == kCondEq: 263 * 264 * 1) When true case is already in place: 265 * cmp $0, src_reg 266 * cmovnz result_reg, false_reg 267 * 2) When false case is already in place: 268 * cmp $0, src_reg 269 * cmovz result_reg, true_reg 270 * 3) When neither cases are in place: 271 * cmp $0, src_reg 272 * mov result_reg, false_reg 273 * cmovz result_reg, true_reg 274 */ 275 276 // kMirOpSelect is generated just for conditional cases when comparison is done with zero. 277 OpRegImm(kOpCmp, rl_src.reg, 0); 278 279 if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { 280 OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); 281 } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { 282 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 283 } else { 284 OpRegCopy(rl_result.reg, rl_false.reg); 285 OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); 286 } 287 } 288 289 StoreValue(rl_dest, rl_result); 290} 291 292void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { 293 LIR* taken = &block_label_list_[bb->taken]; 294 RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); 295 RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); 296 ConditionCode ccode = mir->meta.ccode; 297 298 if (rl_src1.is_const) { 299 std::swap(rl_src1, rl_src2); 300 ccode = FlipComparisonOrder(ccode); 301 } 302 if (rl_src2.is_const) { 303 // Do special compare/branch against simple const operand 304 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 305 GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); 306 return; 307 } 308 309 FlushAllRegs(); 310 LockCallTemps(); // Prepare for explicit register usage 311 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); 312 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); 313 LoadValueDirectWideFixed(rl_src1, r_tmp1); 314 LoadValueDirectWideFixed(rl_src2, r_tmp2); 315 // Swap operands and condition code to prevent use of zero flag. 316 if (ccode == kCondLe || ccode == kCondGt) { 317 // Compute (r3:r2) = (r3:r2) - (r1:r0) 318 OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 319 OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF 320 } else { 321 // Compute (r1:r0) = (r1:r0) - (r3:r2) 322 OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 323 OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF 324 } 325 switch (ccode) { 326 case kCondEq: 327 case kCondNe: 328 OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 329 break; 330 case kCondLe: 331 ccode = kCondGe; 332 break; 333 case kCondGt: 334 ccode = kCondLt; 335 break; 336 case kCondLt: 337 case kCondGe: 338 break; 339 default: 340 LOG(FATAL) << "Unexpected ccode: " << ccode; 341 } 342 OpCondBranch(ccode, taken); 343} 344 345void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 346 int64_t val, ConditionCode ccode) { 347 int32_t val_lo = Low32Bits(val); 348 int32_t val_hi = High32Bits(val); 349 LIR* taken = &block_label_list_[bb->taken]; 350 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 351 bool is_equality_test = ccode == kCondEq || ccode == kCondNe; 352 if (is_equality_test && val != 0) { 353 rl_src1 = ForceTempWide(rl_src1); 354 } 355 RegStorage low_reg = rl_src1.reg.GetLow(); 356 RegStorage high_reg = rl_src1.reg.GetHigh(); 357 358 if (is_equality_test) { 359 // We can simpolify of comparing for ==, != to 0. 360 if (val == 0) { 361 if (IsTemp(low_reg)) { 362 OpRegReg(kOpOr, low_reg, high_reg); 363 // We have now changed it; ignore the old values. 364 Clobber(rl_src1.reg); 365 } else { 366 RegStorage t_reg = AllocTemp(); 367 OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); 368 FreeTemp(t_reg); 369 } 370 OpCondBranch(ccode, taken); 371 return; 372 } 373 374 // Need to compute the actual value for ==, !=. 375 OpRegImm(kOpSub, low_reg, val_lo); 376 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 377 OpRegReg(kOpOr, high_reg, low_reg); 378 Clobber(rl_src1.reg); 379 } else if (ccode == kCondLe || ccode == kCondGt) { 380 // Swap operands and condition code to prevent use of zero flag. 381 RegStorage tmp = AllocTypedTempWide(false, kCoreReg); 382 LoadConstantWide(tmp, val); 383 OpRegReg(kOpSub, tmp.GetLow(), low_reg); 384 OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); 385 ccode = (ccode == kCondLe) ? kCondGe : kCondLt; 386 FreeTemp(tmp); 387 } else { 388 // We can use a compare for the low word to set CF. 389 OpRegImm(kOpCmp, low_reg, val_lo); 390 if (IsTemp(high_reg)) { 391 NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); 392 // We have now changed it; ignore the old values. 393 Clobber(rl_src1.reg); 394 } else { 395 // mov temp_reg, high_reg; sbb temp_reg, high_constant 396 RegStorage t_reg = AllocTemp(); 397 OpRegCopy(t_reg, high_reg); 398 NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); 399 FreeTemp(t_reg); 400 } 401 } 402 403 OpCondBranch(ccode, taken); 404} 405 406void X86Mir2Lir::CalculateMagicAndShift(int divisor, int& magic, int& shift) { 407 // It does not make sense to calculate magic and shift for zero divisor. 408 DCHECK_NE(divisor, 0); 409 410 /* According to H.S.Warren's Hacker's Delight Chapter 10 and 411 * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 412 * The magic number M and shift S can be calculated in the following way: 413 * Let nc be the most positive value of numerator(n) such that nc = kd - 1, 414 * where divisor(d) >=2. 415 * Let nc be the most negative value of numerator(n) such that nc = kd + 1, 416 * where divisor(d) <= -2. 417 * Thus nc can be calculated like: 418 * nc = 2^31 + 2^31 % d - 1, where d >= 2 419 * nc = -2^31 + (2^31 + 1) % d, where d >= 2. 420 * 421 * So the shift p is the smallest p satisfying 422 * 2^p > nc * (d - 2^p % d), where d >= 2 423 * 2^p > nc * (d + 2^p % d), where d <= -2. 424 * 425 * the magic number M is calcuated by 426 * M = (2^p + d - 2^p % d) / d, where d >= 2 427 * M = (2^p - d - 2^p % d) / d, where d <= -2. 428 * 429 * Notice that p is always bigger than or equal to 32, so we just return 32-p as 430 * the shift number S. 431 */ 432 433 int32_t p = 31; 434 const uint32_t two31 = 0x80000000U; 435 436 // Initialize the computations. 437 uint32_t abs_d = (divisor >= 0) ? divisor : -divisor; 438 uint32_t tmp = two31 + (static_cast<uint32_t>(divisor) >> 31); 439 uint32_t abs_nc = tmp - 1 - tmp % abs_d; 440 uint32_t quotient1 = two31 / abs_nc; 441 uint32_t remainder1 = two31 % abs_nc; 442 uint32_t quotient2 = two31 / abs_d; 443 uint32_t remainder2 = two31 % abs_d; 444 445 /* 446 * To avoid handling both positive and negative divisor, Hacker's Delight 447 * introduces a method to handle these 2 cases together to avoid duplication. 448 */ 449 uint32_t delta; 450 do { 451 p++; 452 quotient1 = 2 * quotient1; 453 remainder1 = 2 * remainder1; 454 if (remainder1 >= abs_nc) { 455 quotient1++; 456 remainder1 = remainder1 - abs_nc; 457 } 458 quotient2 = 2 * quotient2; 459 remainder2 = 2 * remainder2; 460 if (remainder2 >= abs_d) { 461 quotient2++; 462 remainder2 = remainder2 - abs_d; 463 } 464 delta = abs_d - remainder2; 465 } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); 466 467 magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); 468 shift = p - 32; 469} 470 471RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { 472 LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; 473 return rl_dest; 474} 475 476RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, 477 int imm, bool is_div) { 478 // Use a multiply (and fixup) to perform an int div/rem by a constant. 479 480 // We have to use fixed registers, so flush all the temps. 481 FlushAllRegs(); 482 LockCallTemps(); // Prepare for explicit register usage. 483 484 // Assume that the result will be in EDX. 485 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; 486 487 // handle div/rem by 1 special case. 488 if (imm == 1) { 489 if (is_div) { 490 // x / 1 == x. 491 StoreValue(rl_result, rl_src); 492 } else { 493 // x % 1 == 0. 494 LoadConstantNoClobber(rs_r0, 0); 495 // For this case, return the result in EAX. 496 rl_result.reg.SetReg(r0); 497 } 498 } else if (imm == -1) { // handle 0x80000000 / -1 special case. 499 if (is_div) { 500 LIR *minint_branch = 0; 501 LoadValueDirectFixed(rl_src, rs_r0); 502 OpRegImm(kOpCmp, rs_r0, 0x80000000); 503 minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); 504 505 // for x != MIN_INT, x / -1 == -x. 506 NewLIR1(kX86Neg32R, r0); 507 508 LIR* branch_around = NewLIR1(kX86Jmp8, 0); 509 // The target for cmp/jmp above. 510 minint_branch->target = NewLIR0(kPseudoTargetLabel); 511 // EAX already contains the right value (0x80000000), 512 branch_around->target = NewLIR0(kPseudoTargetLabel); 513 } else { 514 // x % -1 == 0. 515 LoadConstantNoClobber(rs_r0, 0); 516 } 517 // For this case, return the result in EAX. 518 rl_result.reg.SetReg(r0); 519 } else { 520 CHECK(imm <= -2 || imm >= 2); 521 // Use H.S.Warren's Hacker's Delight Chapter 10 and 522 // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. 523 int magic, shift; 524 CalculateMagicAndShift(imm, magic, shift); 525 526 /* 527 * For imm >= 2, 528 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 529 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. 530 * For imm <= -2, 531 * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 532 * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. 533 * We implement this algorithm in the following way: 534 * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX 535 * 2. if imm > 0 and magic < 0, add numerator to EDX 536 * if imm < 0 and magic > 0, sub numerator from EDX 537 * 3. if S !=0, SAR S bits for EDX 538 * 4. add 1 to EDX if EDX < 0 539 * 5. Thus, EDX is the quotient 540 */ 541 542 // Numerator into EAX. 543 RegStorage numerator_reg; 544 if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { 545 // We will need the value later. 546 if (rl_src.location == kLocPhysReg) { 547 // We can use it directly. 548 DCHECK(rl_src.reg.GetReg() != rs_r0.GetReg() && rl_src.reg.GetReg() != rs_r2.GetReg()); 549 numerator_reg = rl_src.reg; 550 } else { 551 numerator_reg = rs_r1; 552 LoadValueDirectFixed(rl_src, numerator_reg); 553 } 554 OpRegCopy(rs_r0, numerator_reg); 555 } else { 556 // Only need this once. Just put it into EAX. 557 LoadValueDirectFixed(rl_src, rs_r0); 558 } 559 560 // EDX = magic. 561 LoadConstantNoClobber(rs_r2, magic); 562 563 // EDX:EAX = magic & dividend. 564 NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); 565 566 if (imm > 0 && magic < 0) { 567 // Add numerator to EDX. 568 DCHECK(numerator_reg.Valid()); 569 NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 570 } else if (imm < 0 && magic > 0) { 571 DCHECK(numerator_reg.Valid()); 572 NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); 573 } 574 575 // Do we need the shift? 576 if (shift != 0) { 577 // Shift EDX by 'shift' bits. 578 NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); 579 } 580 581 // Add 1 to EDX if EDX < 0. 582 583 // Move EDX to EAX. 584 OpRegCopy(rs_r0, rs_r2); 585 586 // Move sign bit to bit 0, zeroing the rest. 587 NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); 588 589 // EDX = EDX + EAX. 590 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); 591 592 // Quotient is in EDX. 593 if (!is_div) { 594 // We need to compute the remainder. 595 // Remainder is divisor - (quotient * imm). 596 DCHECK(numerator_reg.Valid()); 597 OpRegCopy(rs_r0, numerator_reg); 598 599 // EAX = numerator * imm. 600 OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); 601 602 // EDX -= EAX. 603 NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); 604 605 // For this case, return the result in EAX. 606 rl_result.reg.SetReg(r0); 607 } 608 } 609 610 return rl_result; 611} 612 613RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, 614 bool is_div) { 615 LOG(FATAL) << "Unexpected use of GenDivRem for x86"; 616 return rl_dest; 617} 618 619RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, 620 RegLocation rl_src2, bool is_div, bool check_zero) { 621 // We have to use fixed registers, so flush all the temps. 622 FlushAllRegs(); 623 LockCallTemps(); // Prepare for explicit register usage. 624 625 // Load LHS into EAX. 626 LoadValueDirectFixed(rl_src1, rs_r0); 627 628 // Load RHS into EBX. 629 LoadValueDirectFixed(rl_src2, rs_r1); 630 631 // Copy LHS sign bit into EDX. 632 NewLIR0(kx86Cdq32Da); 633 634 if (check_zero) { 635 // Handle division by zero case. 636 GenDivZeroCheck(rs_r1); 637 } 638 639 // Have to catch 0x80000000/-1 case, or we will get an exception! 640 OpRegImm(kOpCmp, rs_r1, -1); 641 LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 642 643 // RHS is -1. 644 OpRegImm(kOpCmp, rs_r0, 0x80000000); 645 LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 646 647 // In 0x80000000/-1 case. 648 if (!is_div) { 649 // For DIV, EAX is already right. For REM, we need EDX 0. 650 LoadConstantNoClobber(rs_r2, 0); 651 } 652 LIR* done = NewLIR1(kX86Jmp8, 0); 653 654 // Expected case. 655 minus_one_branch->target = NewLIR0(kPseudoTargetLabel); 656 minint_branch->target = minus_one_branch->target; 657 NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); 658 done->target = NewLIR0(kPseudoTargetLabel); 659 660 // Result is in EAX for div and EDX for rem. 661 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; 662 if (!is_div) { 663 rl_result.reg.SetReg(r2); 664 } 665 return rl_result; 666} 667 668bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { 669 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 670 671 // Get the two arguments to the invoke and place them in GP registers. 672 RegLocation rl_src1 = info->args[0]; 673 RegLocation rl_src2 = info->args[1]; 674 rl_src1 = LoadValue(rl_src1, kCoreReg); 675 rl_src2 = LoadValue(rl_src2, kCoreReg); 676 677 RegLocation rl_dest = InlineTarget(info); 678 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 679 680 /* 681 * If the result register is the same as the second element, then we need to be careful. 682 * The reason is that the first copy will inadvertently clobber the second element with 683 * the first one thus yielding the wrong result. Thus we do a swap in that case. 684 */ 685 if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { 686 std::swap(rl_src1, rl_src2); 687 } 688 689 // Pick the first integer as min/max. 690 OpRegCopy(rl_result.reg, rl_src1.reg); 691 692 // If the integers are both in the same register, then there is nothing else to do 693 // because they are equal and we have already moved one into the result. 694 if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { 695 // It is possible we didn't pick correctly so do the actual comparison now. 696 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); 697 698 // Conditionally move the other integer into the destination register. 699 ConditionCode condition_code = is_min ? kCondGt : kCondLt; 700 OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); 701 } 702 703 StoreValue(rl_dest, rl_result); 704 return true; 705} 706 707bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { 708 RegLocation rl_src_address = info->args[0]; // long address 709 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 710 RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); 711 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 712 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 713 // Unaligned access is allowed on x86. 714 LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size); 715 if (size == k64) { 716 StoreValueWide(rl_dest, rl_result); 717 } else { 718 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 719 StoreValue(rl_dest, rl_result); 720 } 721 return true; 722} 723 724bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { 725 RegLocation rl_src_address = info->args[0]; // long address 726 rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] 727 RegLocation rl_src_value = info->args[2]; // [size] value 728 RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); 729 if (size == k64) { 730 // Unaligned access is allowed on x86. 731 RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); 732 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 733 } else { 734 DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); 735 // Unaligned access is allowed on x86. 736 RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); 737 StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); 738 } 739 return true; 740} 741 742void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { 743 NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); 744} 745 746void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { 747 DCHECK_EQ(kX86, cu_->instruction_set); 748 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 749} 750 751void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { 752 DCHECK_EQ(kX86_64, cu_->instruction_set); 753 NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); 754} 755 756static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { 757 return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); 758} 759 760bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { 761 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 762 // Unused - RegLocation rl_src_unsafe = info->args[0]; 763 RegLocation rl_src_obj = info->args[1]; // Object - known non-null 764 RegLocation rl_src_offset = info->args[2]; // long low 765 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 766 RegLocation rl_src_expected = info->args[4]; // int, long or Object 767 // If is_long, high half is in info->args[5] 768 RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object 769 // If is_long, high half is in info->args[7] 770 771 if (is_long) { 772 // TODO: avoid unnecessary loads of SI and DI when the values are in registers. 773 // TODO: CFI support. 774 FlushAllRegs(); 775 LockCallTemps(); 776 RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); 777 RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); 778 LoadValueDirectWideFixed(rl_src_expected, r_tmp1); 779 LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); 780 NewLIR1(kX86Push32R, rs_rDI.GetReg()); 781 MarkTemp(rs_rDI); 782 LockTemp(rs_rDI); 783 NewLIR1(kX86Push32R, rs_rSI.GetReg()); 784 MarkTemp(rs_rSI); 785 LockTemp(rs_rSI); 786 const int push_offset = 4 /* push edi */ + 4 /* push esi */; 787 int srcObjSp = IsInReg(this, rl_src_obj, rs_rSI) ? 0 788 : (IsInReg(this, rl_src_obj, rs_rDI) ? 4 789 : (SRegOffset(rl_src_obj.s_reg_low) + push_offset)); 790 // FIXME: needs 64-bit update. 791 LoadWordDisp(TargetReg(kSp), srcObjSp, rs_rDI); 792 int srcOffsetSp = IsInReg(this, rl_src_offset, rs_rSI) ? 0 793 : (IsInReg(this, rl_src_offset, rs_rDI) ? 4 794 : (SRegOffset(rl_src_offset.s_reg_low) + push_offset)); 795 LoadWordDisp(TargetReg(kSp), srcOffsetSp, rs_rSI); 796 NewLIR4(kX86LockCmpxchg8bA, rs_rDI.GetReg(), rs_rSI.GetReg(), 0, 0); 797 798 // After a store we need to insert barrier in case of potential load. Since the 799 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 800 GenMemBarrier(kStoreLoad); 801 802 FreeTemp(rs_rSI); 803 UnmarkTemp(rs_rSI); 804 NewLIR1(kX86Pop32R, rs_rSI.GetReg()); 805 FreeTemp(rs_rDI); 806 UnmarkTemp(rs_rDI); 807 NewLIR1(kX86Pop32R, rs_rDI.GetReg()); 808 FreeCallTemps(); 809 } else { 810 // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. 811 FlushReg(rs_r0); 812 Clobber(rs_r0); 813 LockTemp(rs_r0); 814 815 RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); 816 RegLocation rl_new_value = LoadValue(rl_src_new_value); 817 818 if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { 819 // Mark card for object assuming new value is stored. 820 FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). 821 MarkGCCard(rl_new_value.reg, rl_object.reg); 822 LockTemp(rs_r0); 823 } 824 825 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 826 LoadValueDirect(rl_src_expected, rs_r0); 827 NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, rl_new_value.reg.GetReg()); 828 829 // After a store we need to insert barrier in case of potential load. Since the 830 // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. 831 GenMemBarrier(kStoreLoad); 832 833 FreeTemp(rs_r0); 834 } 835 836 // Convert ZF to boolean 837 RegLocation rl_dest = InlineTarget(info); // boolean place for result 838 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 839 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondZ); 840 NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); 841 StoreValue(rl_dest, rl_result); 842 return true; 843} 844 845LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { 846 CHECK(base_of_code_ != nullptr); 847 848 // Address the start of the method 849 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 850 if (rl_method.wide) { 851 LoadValueDirectWideFixed(rl_method, reg); 852 } else { 853 LoadValueDirectFixed(rl_method, reg); 854 } 855 store_method_addr_used_ = true; 856 857 // Load the proper value from the literal area. 858 // We don't know the proper offset for the value, so pick one that will force 859 // 4 byte offset. We will fix this up in the assembler later to have the right 860 // value. 861 LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, 862 0, 0, target); 863 res->target = target; 864 res->flags.fixup = kFixupLoad; 865 SetMemRefType(res, true, kLiteral); 866 store_method_addr_used_ = true; 867 return res; 868} 869 870LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { 871 LOG(FATAL) << "Unexpected use of OpVldm for x86"; 872 return NULL; 873} 874 875LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { 876 LOG(FATAL) << "Unexpected use of OpVstm for x86"; 877 return NULL; 878} 879 880void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, 881 RegLocation rl_result, int lit, 882 int first_bit, int second_bit) { 883 RegStorage t_reg = AllocTemp(); 884 OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); 885 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); 886 FreeTemp(t_reg); 887 if (first_bit != 0) { 888 OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); 889 } 890} 891 892void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { 893 DCHECK(reg.IsPair()); // TODO: allow 64BitSolo. 894 // We are not supposed to clobber the incoming storage, so allocate a temporary. 895 RegStorage t_reg = AllocTemp(); 896 897 // Doing an OR is a quick way to check if both registers are zero. This will set the flags. 898 OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); 899 900 // In case of zero, throw ArithmeticException. 901 GenDivZeroCheck(kCondEq); 902 903 // The temp is no longer needed so free it at this time. 904 FreeTemp(t_reg); 905} 906 907void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, 908 RegStorage array_base, 909 int len_offset) { 910 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 911 public: 912 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 913 RegStorage index, RegStorage array_base, int32_t len_offset) 914 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 915 index_(index), array_base_(array_base), len_offset_(len_offset) { 916 } 917 918 void Compile() OVERRIDE { 919 m2l_->ResetRegPool(); 920 m2l_->ResetDefTracking(); 921 GenerateTargetLabel(kPseudoThrowTarget); 922 923 RegStorage new_index = index_; 924 // Move index out of kArg1, either directly to kArg0, or to kArg2. 925 if (index_.GetReg() == m2l_->TargetReg(kArg1).GetReg()) { 926 if (array_base_.GetReg() == m2l_->TargetReg(kArg0).GetReg()) { 927 m2l_->OpRegCopy(m2l_->TargetReg(kArg2), index_); 928 new_index = m2l_->TargetReg(kArg2); 929 } else { 930 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), index_); 931 new_index = m2l_->TargetReg(kArg0); 932 } 933 } 934 // Load array length to kArg1. 935 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 936 if (Is64BitInstructionSet(cu_->instruction_set)) { 937 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 938 new_index, m2l_->TargetReg(kArg1), true); 939 } else { 940 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 941 new_index, m2l_->TargetReg(kArg1), true); 942 } 943 } 944 945 private: 946 const RegStorage index_; 947 const RegStorage array_base_; 948 const int32_t len_offset_; 949 }; 950 951 OpRegMem(kOpCmp, index, array_base, len_offset); 952 LIR* branch = OpCondBranch(kCondUge, nullptr); 953 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 954 index, array_base, len_offset)); 955} 956 957void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, 958 RegStorage array_base, 959 int32_t len_offset) { 960 class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { 961 public: 962 ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, 963 int32_t index, RegStorage array_base, int32_t len_offset) 964 : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), 965 index_(index), array_base_(array_base), len_offset_(len_offset) { 966 } 967 968 void Compile() OVERRIDE { 969 m2l_->ResetRegPool(); 970 m2l_->ResetDefTracking(); 971 GenerateTargetLabel(kPseudoThrowTarget); 972 973 // Load array length to kArg1. 974 m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); 975 m2l_->LoadConstant(m2l_->TargetReg(kArg0), index_); 976 if (Is64BitInstructionSet(cu_->instruction_set)) { 977 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(8, pThrowArrayBounds), 978 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 979 } else { 980 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), 981 m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); 982 } 983 } 984 985 private: 986 const int32_t index_; 987 const RegStorage array_base_; 988 const int32_t len_offset_; 989 }; 990 991 NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); 992 LIR* branch = OpCondBranch(kCondLs, nullptr); 993 AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, 994 index, array_base, len_offset)); 995} 996 997// Test suspend flag, return target of taken suspend branch 998LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { 999 if (Is64BitInstructionSet(cu_->instruction_set)) { 1000 OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); 1001 } else { 1002 OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); 1003 } 1004 return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); 1005} 1006 1007// Decrement register and branch on condition 1008LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { 1009 OpRegImm(kOpSub, reg, 1); 1010 return OpCondBranch(c_code, target); 1011} 1012 1013bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, 1014 RegLocation rl_src, RegLocation rl_dest, int lit) { 1015 LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; 1016 return false; 1017} 1018 1019bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1020 LOG(FATAL) << "Unexpected use of easyMultiply in x86"; 1021 return false; 1022} 1023 1024LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { 1025 LOG(FATAL) << "Unexpected use of OpIT in x86"; 1026 return NULL; 1027} 1028 1029void X86Mir2Lir::OpEndIT(LIR* it) { 1030 LOG(FATAL) << "Unexpected use of OpEndIT in x86"; 1031} 1032 1033void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { 1034 switch (val) { 1035 case 0: 1036 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1037 break; 1038 case 1: 1039 OpRegCopy(dest, src); 1040 break; 1041 default: 1042 OpRegRegImm(kOpMul, dest, src, val); 1043 break; 1044 } 1045} 1046 1047void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { 1048 LIR *m; 1049 switch (val) { 1050 case 0: 1051 NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); 1052 break; 1053 case 1: 1054 LoadBaseDisp(rs_rX86_SP, displacement, dest, k32); 1055 break; 1056 default: 1057 m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), 1058 rs_rX86_SP.GetReg(), displacement, val); 1059 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); 1060 break; 1061 } 1062} 1063 1064void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1065 RegLocation rl_src2) { 1066 if (rl_src1.is_const) { 1067 std::swap(rl_src1, rl_src2); 1068 } 1069 // Are we multiplying by a constant? 1070 if (rl_src2.is_const) { 1071 // Do special compare/branch against simple const operand 1072 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1073 if (val == 0) { 1074 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1075 OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); 1076 OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); 1077 StoreValueWide(rl_dest, rl_result); 1078 return; 1079 } else if (val == 1) { 1080 StoreValueWide(rl_dest, rl_src1); 1081 return; 1082 } else if (val == 2) { 1083 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); 1084 return; 1085 } else if (IsPowerOfTwo(val)) { 1086 int shift_amount = LowestSetBit(val); 1087 if (!BadOverlap(rl_src1, rl_dest)) { 1088 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1089 RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, 1090 rl_src1, shift_amount); 1091 StoreValueWide(rl_dest, rl_result); 1092 return; 1093 } 1094 } 1095 1096 // Okay, just bite the bullet and do it. 1097 int32_t val_lo = Low32Bits(val); 1098 int32_t val_hi = High32Bits(val); 1099 FlushAllRegs(); 1100 LockCallTemps(); // Prepare for explicit register usage. 1101 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1102 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1103 int displacement = SRegOffset(rl_src1.s_reg_low); 1104 1105 // ECX <- 1H * 2L 1106 // EAX <- 1L * 2H 1107 if (src1_in_reg) { 1108 GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); 1109 GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); 1110 } else { 1111 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); 1112 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); 1113 } 1114 1115 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1116 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1117 1118 // EAX <- 2L 1119 LoadConstantNoClobber(rs_r0, val_lo); 1120 1121 // EDX:EAX <- 2L * 1L (double precision) 1122 if (src1_in_reg) { 1123 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1124 } else { 1125 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1126 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1127 true /* is_load */, true /* is_64bit */); 1128 } 1129 1130 // EDX <- EDX + ECX (add high words) 1131 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1132 1133 // Result is EDX:EAX 1134 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1135 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1136 StoreValueWide(rl_dest, rl_result); 1137 return; 1138 } 1139 1140 // Nope. Do it the hard way 1141 // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. 1142 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == 1143 mir_graph_->SRegToVReg(rl_src2.s_reg_low); 1144 1145 FlushAllRegs(); 1146 LockCallTemps(); // Prepare for explicit register usage. 1147 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1148 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1149 1150 // At this point, the VRs are in their home locations. 1151 bool src1_in_reg = rl_src1.location == kLocPhysReg; 1152 bool src2_in_reg = rl_src2.location == kLocPhysReg; 1153 1154 // ECX <- 1H 1155 if (src1_in_reg) { 1156 NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); 1157 } else { 1158 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32); 1159 } 1160 1161 if (is_square) { 1162 // Take advantage of the fact that the values are the same. 1163 // ECX <- ECX * 2L (1H * 2L) 1164 if (src2_in_reg) { 1165 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1166 } else { 1167 int displacement = SRegOffset(rl_src2.s_reg_low); 1168 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1169 displacement + LOWORD_OFFSET); 1170 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1171 true /* is_load */, true /* is_64bit */); 1172 } 1173 1174 // ECX <- 2*ECX (2H * 1L) + (1H * 2L) 1175 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); 1176 } else { 1177 // EAX <- 2H 1178 if (src2_in_reg) { 1179 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); 1180 } else { 1181 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32); 1182 } 1183 1184 // EAX <- EAX * 1L (2H * 1L) 1185 if (src1_in_reg) { 1186 NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); 1187 } else { 1188 int displacement = SRegOffset(rl_src1.s_reg_low); 1189 LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), 1190 displacement + LOWORD_OFFSET); 1191 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1192 true /* is_load */, true /* is_64bit */); 1193 } 1194 1195 // ECX <- ECX * 2L (1H * 2L) 1196 if (src2_in_reg) { 1197 NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); 1198 } else { 1199 int displacement = SRegOffset(rl_src2.s_reg_low); 1200 LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), 1201 displacement + LOWORD_OFFSET); 1202 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1203 true /* is_load */, true /* is_64bit */); 1204 } 1205 1206 // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) 1207 NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); 1208 } 1209 1210 // EAX <- 2L 1211 if (src2_in_reg) { 1212 NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); 1213 } else { 1214 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32); 1215 } 1216 1217 // EDX:EAX <- 2L * 1L (double precision) 1218 if (src1_in_reg) { 1219 NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); 1220 } else { 1221 int displacement = SRegOffset(rl_src1.s_reg_low); 1222 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); 1223 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, 1224 true /* is_load */, true /* is_64bit */); 1225 } 1226 1227 // EDX <- EDX + ECX (add high words) 1228 NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); 1229 1230 // Result is EDX:EAX 1231 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, 1232 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; 1233 StoreValueWide(rl_dest, rl_result); 1234} 1235 1236void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, 1237 Instruction::Code op) { 1238 DCHECK_EQ(rl_dest.location, kLocPhysReg); 1239 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1240 if (rl_src.location == kLocPhysReg) { 1241 // Both operands are in registers. 1242 // But we must ensure that rl_src is in pair 1243 rl_src = LoadValueWide(rl_src, kCoreReg); 1244 if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1245 // The registers are the same, so we would clobber it before the use. 1246 RegStorage temp_reg = AllocTemp(); 1247 OpRegCopy(temp_reg, rl_dest.reg); 1248 rl_src.reg.SetHighReg(temp_reg.GetReg()); 1249 } 1250 NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); 1251 1252 x86op = GetOpcode(op, rl_dest, rl_src, true); 1253 NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); 1254 FreeTemp(rl_src.reg); 1255 return; 1256 } 1257 1258 // RHS is in memory. 1259 DCHECK((rl_src.location == kLocDalvikFrame) || 1260 (rl_src.location == kLocCompilerTemp)); 1261 int r_base = TargetReg(kSp).GetReg(); 1262 int displacement = SRegOffset(rl_src.s_reg_low); 1263 1264 LIR *lir = NewLIR3(x86op, rl_dest.reg.GetLowReg(), r_base, displacement + LOWORD_OFFSET); 1265 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1266 true /* is_load */, true /* is64bit */); 1267 x86op = GetOpcode(op, rl_dest, rl_src, true); 1268 lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); 1269 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1270 true /* is_load */, true /* is64bit */); 1271} 1272 1273void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 1274 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 1275 if (rl_dest.location == kLocPhysReg) { 1276 // Ensure we are in a register pair 1277 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1278 1279 rl_src = UpdateLocWideTyped(rl_src, kCoreReg); 1280 GenLongRegOrMemOp(rl_result, rl_src, op); 1281 StoreFinalValueWide(rl_dest, rl_result); 1282 return; 1283 } 1284 1285 // It wasn't in registers, so it better be in memory. 1286 DCHECK((rl_dest.location == kLocDalvikFrame) || 1287 (rl_dest.location == kLocCompilerTemp)); 1288 rl_src = LoadValueWide(rl_src, kCoreReg); 1289 1290 // Operate directly into memory. 1291 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); 1292 int r_base = TargetReg(kSp).GetReg(); 1293 int displacement = SRegOffset(rl_dest.s_reg_low); 1294 1295 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, rl_src.reg.GetLowReg()); 1296 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1297 true /* is_load */, true /* is64bit */); 1298 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1299 false /* is_load */, true /* is64bit */); 1300 x86op = GetOpcode(op, rl_dest, rl_src, true); 1301 lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); 1302 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1303 true /* is_load */, true /* is64bit */); 1304 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1305 false /* is_load */, true /* is64bit */); 1306 FreeTemp(rl_src.reg); 1307} 1308 1309void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, 1310 RegLocation rl_src2, Instruction::Code op, 1311 bool is_commutative) { 1312 // Is this really a 2 operand operation? 1313 switch (op) { 1314 case Instruction::ADD_LONG_2ADDR: 1315 case Instruction::SUB_LONG_2ADDR: 1316 case Instruction::AND_LONG_2ADDR: 1317 case Instruction::OR_LONG_2ADDR: 1318 case Instruction::XOR_LONG_2ADDR: 1319 if (GenerateTwoOperandInstructions()) { 1320 GenLongArith(rl_dest, rl_src2, op); 1321 return; 1322 } 1323 break; 1324 1325 default: 1326 break; 1327 } 1328 1329 if (rl_dest.location == kLocPhysReg) { 1330 RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); 1331 1332 // We are about to clobber the LHS, so it needs to be a temp. 1333 rl_result = ForceTempWide(rl_result); 1334 1335 // Perform the operation using the RHS. 1336 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1337 GenLongRegOrMemOp(rl_result, rl_src2, op); 1338 1339 // And now record that the result is in the temp. 1340 StoreFinalValueWide(rl_dest, rl_result); 1341 return; 1342 } 1343 1344 // It wasn't in registers, so it better be in memory. 1345 DCHECK((rl_dest.location == kLocDalvikFrame) || 1346 (rl_dest.location == kLocCompilerTemp)); 1347 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1348 rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); 1349 1350 // Get one of the source operands into temporary register. 1351 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1352 if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { 1353 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1354 } else if (is_commutative) { 1355 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1356 // We need at least one of them to be a temporary. 1357 if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { 1358 rl_src1 = ForceTempWide(rl_src1); 1359 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1360 } else { 1361 GenLongRegOrMemOp(rl_src2, rl_src1, op); 1362 StoreFinalValueWide(rl_dest, rl_src2); 1363 return; 1364 } 1365 } else { 1366 // Need LHS to be the temp. 1367 rl_src1 = ForceTempWide(rl_src1); 1368 GenLongRegOrMemOp(rl_src1, rl_src2, op); 1369 } 1370 1371 StoreFinalValueWide(rl_dest, rl_src1); 1372} 1373 1374void X86Mir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, 1375 RegLocation rl_src1, RegLocation rl_src2) { 1376 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1377} 1378 1379void X86Mir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, 1380 RegLocation rl_src1, RegLocation rl_src2) { 1381 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); 1382} 1383 1384void X86Mir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, 1385 RegLocation rl_src1, RegLocation rl_src2) { 1386 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1387} 1388 1389void X86Mir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, 1390 RegLocation rl_src1, RegLocation rl_src2) { 1391 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1392} 1393 1394void X86Mir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, 1395 RegLocation rl_src1, RegLocation rl_src2) { 1396 GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); 1397} 1398 1399void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { 1400 LOG(FATAL) << "Unexpected use GenNotLong()"; 1401} 1402 1403void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 1404 RegLocation rl_src2, bool is_div) { 1405 LOG(FATAL) << "Unexpected use GenDivRemLong()"; 1406} 1407 1408void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { 1409 rl_src = LoadValueWide(rl_src, kCoreReg); 1410 RegLocation rl_result = ForceTempWide(rl_src); 1411 if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && 1412 ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { 1413 // The registers are the same, so we would clobber it before the use. 1414 RegStorage temp_reg = AllocTemp(); 1415 OpRegCopy(temp_reg, rl_result.reg); 1416 rl_result.reg.SetHighReg(temp_reg.GetReg()); 1417 } 1418 OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow 1419 OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF 1420 OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh 1421 StoreValueWide(rl_dest, rl_result); 1422} 1423 1424void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { 1425 DCHECK_EQ(kX86, cu_->instruction_set); 1426 X86OpCode opcode = kX86Bkpt; 1427 switch (op) { 1428 case kOpCmp: opcode = kX86Cmp32RT; break; 1429 case kOpMov: opcode = kX86Mov32RT; break; 1430 default: 1431 LOG(FATAL) << "Bad opcode: " << op; 1432 break; 1433 } 1434 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1435} 1436 1437void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { 1438 DCHECK_EQ(kX86_64, cu_->instruction_set); 1439 X86OpCode opcode = kX86Bkpt; 1440 if (Gen64Bit() && r_dest.Is64BitSolo()) { 1441 switch (op) { 1442 case kOpCmp: opcode = kX86Cmp64RT; break; 1443 case kOpMov: opcode = kX86Mov64RT; break; 1444 default: 1445 LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; 1446 break; 1447 } 1448 } else { 1449 switch (op) { 1450 case kOpCmp: opcode = kX86Cmp32RT; break; 1451 case kOpMov: opcode = kX86Mov32RT; break; 1452 default: 1453 LOG(FATAL) << "Bad opcode: " << op; 1454 break; 1455 } 1456 } 1457 NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); 1458} 1459 1460/* 1461 * Generate array load 1462 */ 1463void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, 1464 RegLocation rl_index, RegLocation rl_dest, int scale) { 1465 RegisterClass reg_class = RegClassBySize(size); 1466 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1467 RegLocation rl_result; 1468 rl_array = LoadValue(rl_array, kRefReg); 1469 1470 int data_offset; 1471 if (size == k64 || size == kDouble) { 1472 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1473 } else { 1474 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1475 } 1476 1477 bool constant_index = rl_index.is_const; 1478 int32_t constant_index_value = 0; 1479 if (!constant_index) { 1480 rl_index = LoadValue(rl_index, kCoreReg); 1481 } else { 1482 constant_index_value = mir_graph_->ConstantValue(rl_index); 1483 // If index is constant, just fold it into the data offset 1484 data_offset += constant_index_value << scale; 1485 // treat as non array below 1486 rl_index.reg = RegStorage::InvalidReg(); 1487 } 1488 1489 /* null object? */ 1490 GenNullCheck(rl_array.reg, opt_flags); 1491 1492 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1493 if (constant_index) { 1494 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1495 } else { 1496 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1497 } 1498 } 1499 rl_result = EvalLoc(rl_dest, reg_class, true); 1500 LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); 1501 if ((size == k64) || (size == kDouble)) { 1502 StoreValueWide(rl_dest, rl_result); 1503 } else { 1504 StoreValue(rl_dest, rl_result); 1505 } 1506} 1507 1508/* 1509 * Generate array store 1510 * 1511 */ 1512void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 1513 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { 1514 RegisterClass reg_class = RegClassBySize(size); 1515 int len_offset = mirror::Array::LengthOffset().Int32Value(); 1516 int data_offset; 1517 1518 if (size == k64 || size == kDouble) { 1519 data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); 1520 } else { 1521 data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); 1522 } 1523 1524 rl_array = LoadValue(rl_array, kRefReg); 1525 bool constant_index = rl_index.is_const; 1526 int32_t constant_index_value = 0; 1527 if (!constant_index) { 1528 rl_index = LoadValue(rl_index, kCoreReg); 1529 } else { 1530 // If index is constant, just fold it into the data offset 1531 constant_index_value = mir_graph_->ConstantValue(rl_index); 1532 data_offset += constant_index_value << scale; 1533 // treat as non array below 1534 rl_index.reg = RegStorage::InvalidReg(); 1535 } 1536 1537 /* null object? */ 1538 GenNullCheck(rl_array.reg, opt_flags); 1539 1540 if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { 1541 if (constant_index) { 1542 GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); 1543 } else { 1544 GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); 1545 } 1546 } 1547 if ((size == k64) || (size == kDouble)) { 1548 rl_src = LoadValueWide(rl_src, reg_class); 1549 } else { 1550 rl_src = LoadValue(rl_src, reg_class); 1551 } 1552 // If the src reg can't be byte accessed, move it to a temp first. 1553 if ((size == kSignedByte || size == kUnsignedByte) && 1554 rl_src.reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 1555 RegStorage temp = AllocTemp(); 1556 OpRegCopy(temp, rl_src.reg); 1557 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); 1558 } else { 1559 StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); 1560 } 1561 if (card_mark) { 1562 // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. 1563 if (!constant_index) { 1564 FreeTemp(rl_index.reg); 1565 } 1566 MarkGCCard(rl_src.reg, rl_array.reg); 1567 } 1568} 1569 1570RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1571 RegLocation rl_src, int shift_amount) { 1572 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1573 switch (opcode) { 1574 case Instruction::SHL_LONG: 1575 case Instruction::SHL_LONG_2ADDR: 1576 DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. 1577 if (shift_amount == 32) { 1578 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1579 LoadConstant(rl_result.reg.GetLow(), 0); 1580 } else if (shift_amount > 31) { 1581 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); 1582 NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); 1583 LoadConstant(rl_result.reg.GetLow(), 0); 1584 } else { 1585 OpRegCopy(rl_result.reg, rl_src.reg); 1586 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1587 NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), shift_amount); 1588 NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); 1589 } 1590 break; 1591 case Instruction::SHR_LONG: 1592 case Instruction::SHR_LONG_2ADDR: 1593 if (shift_amount == 32) { 1594 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1595 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1596 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1597 } else if (shift_amount > 31) { 1598 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1599 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1600 NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1601 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); 1602 } else { 1603 OpRegCopy(rl_result.reg, rl_src.reg); 1604 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1605 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount); 1606 NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); 1607 } 1608 break; 1609 case Instruction::USHR_LONG: 1610 case Instruction::USHR_LONG_2ADDR: 1611 if (shift_amount == 32) { 1612 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1613 LoadConstant(rl_result.reg.GetHigh(), 0); 1614 } else if (shift_amount > 31) { 1615 OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); 1616 NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); 1617 LoadConstant(rl_result.reg.GetHigh(), 0); 1618 } else { 1619 OpRegCopy(rl_result.reg, rl_src.reg); 1620 OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); 1621 NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount); 1622 NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); 1623 } 1624 break; 1625 default: 1626 LOG(FATAL) << "Unexpected case"; 1627 } 1628 return rl_result; 1629} 1630 1631void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 1632 RegLocation rl_src, RegLocation rl_shift) { 1633 // Per spec, we only care about low 6 bits of shift amount. 1634 int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; 1635 if (shift_amount == 0) { 1636 rl_src = LoadValueWide(rl_src, kCoreReg); 1637 StoreValueWide(rl_dest, rl_src); 1638 return; 1639 } else if (shift_amount == 1 && 1640 (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { 1641 // Need to handle this here to avoid calling StoreValueWide twice. 1642 GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); 1643 return; 1644 } 1645 if (BadOverlap(rl_src, rl_dest)) { 1646 GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); 1647 return; 1648 } 1649 rl_src = LoadValueWide(rl_src, kCoreReg); 1650 RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); 1651 StoreValueWide(rl_dest, rl_result); 1652} 1653 1654void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, 1655 RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { 1656 switch (opcode) { 1657 case Instruction::ADD_LONG: 1658 case Instruction::AND_LONG: 1659 case Instruction::OR_LONG: 1660 case Instruction::XOR_LONG: 1661 if (rl_src2.is_const) { 1662 GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1663 } else { 1664 DCHECK(rl_src1.is_const); 1665 GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1666 } 1667 break; 1668 case Instruction::SUB_LONG: 1669 case Instruction::SUB_LONG_2ADDR: 1670 if (rl_src2.is_const) { 1671 GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1672 } else { 1673 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1674 } 1675 break; 1676 case Instruction::ADD_LONG_2ADDR: 1677 case Instruction::OR_LONG_2ADDR: 1678 case Instruction::XOR_LONG_2ADDR: 1679 case Instruction::AND_LONG_2ADDR: 1680 if (rl_src2.is_const) { 1681 if (GenerateTwoOperandInstructions()) { 1682 GenLongImm(rl_dest, rl_src2, opcode); 1683 } else { 1684 GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); 1685 } 1686 } else { 1687 DCHECK(rl_src1.is_const); 1688 GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); 1689 } 1690 break; 1691 default: 1692 // Default - bail to non-const handler. 1693 GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); 1694 break; 1695 } 1696} 1697 1698bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { 1699 switch (op) { 1700 case Instruction::AND_LONG_2ADDR: 1701 case Instruction::AND_LONG: 1702 return value == -1; 1703 case Instruction::OR_LONG: 1704 case Instruction::OR_LONG_2ADDR: 1705 case Instruction::XOR_LONG: 1706 case Instruction::XOR_LONG_2ADDR: 1707 return value == 0; 1708 default: 1709 return false; 1710 } 1711} 1712 1713X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 1714 bool is_high_op) { 1715 bool rhs_in_mem = rhs.location != kLocPhysReg; 1716 bool dest_in_mem = dest.location != kLocPhysReg; 1717 bool is64Bit = Gen64Bit(); 1718 DCHECK(!rhs_in_mem || !dest_in_mem); 1719 switch (op) { 1720 case Instruction::ADD_LONG: 1721 case Instruction::ADD_LONG_2ADDR: 1722 if (dest_in_mem) { 1723 return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; 1724 } else if (rhs_in_mem) { 1725 return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; 1726 } 1727 return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; 1728 case Instruction::SUB_LONG: 1729 case Instruction::SUB_LONG_2ADDR: 1730 if (dest_in_mem) { 1731 return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; 1732 } else if (rhs_in_mem) { 1733 return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; 1734 } 1735 return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; 1736 case Instruction::AND_LONG_2ADDR: 1737 case Instruction::AND_LONG: 1738 if (dest_in_mem) { 1739 return is64Bit ? kX86And64MR : kX86And32MR; 1740 } 1741 if (is64Bit) { 1742 return rhs_in_mem ? kX86And64RM : kX86And64RR; 1743 } 1744 return rhs_in_mem ? kX86And32RM : kX86And32RR; 1745 case Instruction::OR_LONG: 1746 case Instruction::OR_LONG_2ADDR: 1747 if (dest_in_mem) { 1748 return is64Bit ? kX86Or64MR : kX86Or32MR; 1749 } 1750 if (is64Bit) { 1751 return rhs_in_mem ? kX86Or64RM : kX86Or64RR; 1752 } 1753 return rhs_in_mem ? kX86Or32RM : kX86Or32RR; 1754 case Instruction::XOR_LONG: 1755 case Instruction::XOR_LONG_2ADDR: 1756 if (dest_in_mem) { 1757 return is64Bit ? kX86Xor64MR : kX86Xor32MR; 1758 } 1759 if (is64Bit) { 1760 return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; 1761 } 1762 return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; 1763 default: 1764 LOG(FATAL) << "Unexpected opcode: " << op; 1765 return kX86Add32RR; 1766 } 1767} 1768 1769X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, 1770 int32_t value) { 1771 bool in_mem = loc.location != kLocPhysReg; 1772 bool is64Bit = Gen64Bit(); 1773 bool byte_imm = IS_SIMM8(value); 1774 DCHECK(in_mem || !loc.reg.IsFloat()); 1775 switch (op) { 1776 case Instruction::ADD_LONG: 1777 case Instruction::ADD_LONG_2ADDR: 1778 if (byte_imm) { 1779 if (in_mem) { 1780 return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; 1781 } 1782 return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; 1783 } 1784 if (in_mem) { 1785 return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; 1786 } 1787 return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; 1788 case Instruction::SUB_LONG: 1789 case Instruction::SUB_LONG_2ADDR: 1790 if (byte_imm) { 1791 if (in_mem) { 1792 return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; 1793 } 1794 return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; 1795 } 1796 if (in_mem) { 1797 return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; 1798 } 1799 return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; 1800 case Instruction::AND_LONG_2ADDR: 1801 case Instruction::AND_LONG: 1802 if (byte_imm) { 1803 if (is64Bit) { 1804 return in_mem ? kX86And64MI8 : kX86And64RI8; 1805 } 1806 return in_mem ? kX86And32MI8 : kX86And32RI8; 1807 } 1808 if (is64Bit) { 1809 return in_mem ? kX86And64MI : kX86And64RI; 1810 } 1811 return in_mem ? kX86And32MI : kX86And32RI; 1812 case Instruction::OR_LONG: 1813 case Instruction::OR_LONG_2ADDR: 1814 if (byte_imm) { 1815 if (is64Bit) { 1816 return in_mem ? kX86Or64MI8 : kX86Or64RI8; 1817 } 1818 return in_mem ? kX86Or32MI8 : kX86Or32RI8; 1819 } 1820 if (is64Bit) { 1821 return in_mem ? kX86Or64MI : kX86Or64RI; 1822 } 1823 return in_mem ? kX86Or32MI : kX86Or32RI; 1824 case Instruction::XOR_LONG: 1825 case Instruction::XOR_LONG_2ADDR: 1826 if (byte_imm) { 1827 if (is64Bit) { 1828 return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; 1829 } 1830 return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; 1831 } 1832 if (is64Bit) { 1833 return in_mem ? kX86Xor64MI : kX86Xor64RI; 1834 } 1835 return in_mem ? kX86Xor32MI : kX86Xor32RI; 1836 default: 1837 LOG(FATAL) << "Unexpected opcode: " << op; 1838 return kX86Add32MI; 1839 } 1840} 1841 1842void X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { 1843 DCHECK(rl_src.is_const); 1844 int64_t val = mir_graph_->ConstantValueWide(rl_src); 1845 int32_t val_lo = Low32Bits(val); 1846 int32_t val_hi = High32Bits(val); 1847 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 1848 1849 // Can we just do this into memory? 1850 if ((rl_dest.location == kLocDalvikFrame) || 1851 (rl_dest.location == kLocCompilerTemp)) { 1852 int r_base = TargetReg(kSp).GetReg(); 1853 int displacement = SRegOffset(rl_dest.s_reg_low); 1854 1855 if (!IsNoOp(op, val_lo)) { 1856 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 1857 LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); 1858 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1859 true /* is_load */, true /* is64bit */); 1860 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, 1861 false /* is_load */, true /* is64bit */); 1862 } 1863 if (!IsNoOp(op, val_hi)) { 1864 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 1865 LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); 1866 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1867 true /* is_load */, true /* is64bit */); 1868 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, 1869 false /* is_load */, true /* is64bit */); 1870 } 1871 return; 1872 } 1873 1874 RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); 1875 DCHECK_EQ(rl_result.location, kLocPhysReg); 1876 DCHECK(!rl_result.reg.IsFloat()); 1877 1878 if (!IsNoOp(op, val_lo)) { 1879 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 1880 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 1881 } 1882 if (!IsNoOp(op, val_hi)) { 1883 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 1884 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 1885 } 1886 StoreValueWide(rl_dest, rl_result); 1887} 1888 1889void X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, 1890 RegLocation rl_src2, Instruction::Code op) { 1891 DCHECK(rl_src2.is_const); 1892 int64_t val = mir_graph_->ConstantValueWide(rl_src2); 1893 int32_t val_lo = Low32Bits(val); 1894 int32_t val_hi = High32Bits(val); 1895 rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); 1896 rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); 1897 1898 // Can we do this directly into the destination registers? 1899 if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && 1900 rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && 1901 rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { 1902 if (!IsNoOp(op, val_lo)) { 1903 X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); 1904 NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); 1905 } 1906 if (!IsNoOp(op, val_hi)) { 1907 X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); 1908 NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); 1909 } 1910 1911 StoreFinalValueWide(rl_dest, rl_dest); 1912 return; 1913 } 1914 1915 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1916 DCHECK_EQ(rl_src1.location, kLocPhysReg); 1917 1918 // We need the values to be in a temporary 1919 RegLocation rl_result = ForceTempWide(rl_src1); 1920 if (!IsNoOp(op, val_lo)) { 1921 X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); 1922 NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); 1923 } 1924 if (!IsNoOp(op, val_hi)) { 1925 X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); 1926 NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); 1927 } 1928 1929 StoreFinalValueWide(rl_dest, rl_result); 1930} 1931 1932// For final classes there are no sub-classes to check and so we can answer the instance-of 1933// question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. 1934void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, 1935 RegLocation rl_dest, RegLocation rl_src) { 1936 RegLocation object = LoadValue(rl_src, kRefReg); 1937 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1938 RegStorage result_reg = rl_result.reg; 1939 1940 // SETcc only works with EAX..EDX. 1941 if (result_reg == object.reg || result_reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 1942 result_reg = AllocateByteRegister(); 1943 DCHECK_LT(result_reg.GetRegNum(), rs_rX86_SP.GetRegNum()); 1944 } 1945 1946 // Assume that there is no match. 1947 LoadConstant(result_reg, 0); 1948 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); 1949 1950 RegStorage check_class = AllocTypedTemp(false, kRefReg); 1951 1952 // If Method* is already in a register, we can save a copy. 1953 RegLocation rl_method = mir_graph_->GetMethodLoc(); 1954 int32_t offset_of_type = mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 1955 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 1956 1957 if (rl_method.location == kLocPhysReg) { 1958 if (use_declaring_class) { 1959 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1960 check_class); 1961 } else { 1962 LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1963 check_class); 1964 LoadRefDisp(check_class, offset_of_type, check_class); 1965 } 1966 } else { 1967 LoadCurrMethodDirect(check_class); 1968 if (use_declaring_class) { 1969 LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1970 check_class); 1971 } else { 1972 LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1973 check_class); 1974 LoadRefDisp(check_class, offset_of_type, check_class); 1975 } 1976 } 1977 1978 // Compare the computed class to the class in the object. 1979 DCHECK_EQ(object.location, kLocPhysReg); 1980 OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); 1981 1982 // Set the low byte of the result to 0 or 1 from the compare condition code. 1983 NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); 1984 1985 LIR* target = NewLIR0(kPseudoTargetLabel); 1986 null_branchover->target = target; 1987 FreeTemp(check_class); 1988 if (IsTemp(result_reg)) { 1989 OpRegCopy(rl_result.reg, result_reg); 1990 FreeTemp(result_reg); 1991 } 1992 StoreValue(rl_dest, rl_result); 1993} 1994 1995void X86Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1996 bool type_known_abstract, bool use_declaring_class, 1997 bool can_assume_type_is_in_dex_cache, 1998 uint32_t type_idx, RegLocation rl_dest, 1999 RegLocation rl_src) { 2000 FlushAllRegs(); 2001 // May generate a call - use explicit registers. 2002 LockCallTemps(); 2003 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 gets current Method*. 2004 RegStorage class_reg = TargetReg(kArg2); // kArg2 will hold the Class*. 2005 // Reference must end up in kArg0. 2006 if (needs_access_check) { 2007 // Check we have access to type_idx and if not throw IllegalAccessError, 2008 // Caller function returns Class* in kArg0. 2009 if (Is64BitInstructionSet(cu_->instruction_set)) { 2010 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeTypeAndVerifyAccess), 2011 type_idx, true); 2012 } else { 2013 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), 2014 type_idx, true); 2015 } 2016 OpRegCopy(class_reg, TargetReg(kRet0)); 2017 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2018 } else if (use_declaring_class) { 2019 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2020 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 2021 class_reg); 2022 } else { 2023 // Load dex cache entry into class_reg (kArg2). 2024 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 2025 LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 2026 class_reg); 2027 int32_t offset_of_type = 2028 mirror::Array::DataOffset(sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + 2029 (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); 2030 LoadRefDisp(class_reg, offset_of_type, class_reg); 2031 if (!can_assume_type_is_in_dex_cache) { 2032 // Need to test presence of type in dex cache at runtime. 2033 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 2034 // Type is not resolved. Call out to helper, which will return resolved type in kRet0/kArg0. 2035 if (Is64BitInstructionSet(cu_->instruction_set)) { 2036 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(8, pInitializeType), type_idx, true); 2037 } else { 2038 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); 2039 } 2040 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path. 2041 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* Reload Ref. */ 2042 // Rejoin code paths 2043 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 2044 hop_branch->target = hop_target; 2045 } 2046 } 2047 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result. */ 2048 RegLocation rl_result = GetReturn(kRefReg); 2049 2050 // SETcc only works with EAX..EDX. 2051 DCHECK_LT(rl_result.reg.GetRegNum(), 4); 2052 2053 // Is the class NULL? 2054 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 2055 2056 /* Load object->klass_. */ 2057 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 2058 LoadRefDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 2059 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class. */ 2060 LIR* branchover = nullptr; 2061 if (type_known_final) { 2062 // Ensure top 3 bytes of result are 0. 2063 LoadConstant(rl_result.reg, 0); 2064 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); 2065 // Set the low byte of the result to 0 or 1 from the compare condition code. 2066 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondEq); 2067 } else { 2068 if (!type_known_abstract) { 2069 LoadConstant(rl_result.reg, 1); // Assume result succeeds. 2070 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 2071 } 2072 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 2073 if (Is64BitInstructionSet(cu_->instruction_set)) { 2074 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(8, pInstanceofNonTrivial)); 2075 } else { 2076 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); 2077 } 2078 } 2079 // TODO: only clobber when type isn't final? 2080 ClobberCallerSave(); 2081 /* Branch targets here. */ 2082 LIR* target = NewLIR0(kPseudoTargetLabel); 2083 StoreValue(rl_dest, rl_result); 2084 branch1->target = target; 2085 if (branchover != nullptr) { 2086 branchover->target = target; 2087 } 2088} 2089 2090void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 2091 RegLocation rl_lhs, RegLocation rl_rhs) { 2092 OpKind op = kOpBkpt; 2093 bool is_div_rem = false; 2094 bool unary = false; 2095 bool shift_op = false; 2096 bool is_two_addr = false; 2097 RegLocation rl_result; 2098 switch (opcode) { 2099 case Instruction::NEG_INT: 2100 op = kOpNeg; 2101 unary = true; 2102 break; 2103 case Instruction::NOT_INT: 2104 op = kOpMvn; 2105 unary = true; 2106 break; 2107 case Instruction::ADD_INT_2ADDR: 2108 is_two_addr = true; 2109 // Fallthrough 2110 case Instruction::ADD_INT: 2111 op = kOpAdd; 2112 break; 2113 case Instruction::SUB_INT_2ADDR: 2114 is_two_addr = true; 2115 // Fallthrough 2116 case Instruction::SUB_INT: 2117 op = kOpSub; 2118 break; 2119 case Instruction::MUL_INT_2ADDR: 2120 is_two_addr = true; 2121 // Fallthrough 2122 case Instruction::MUL_INT: 2123 op = kOpMul; 2124 break; 2125 case Instruction::DIV_INT_2ADDR: 2126 is_two_addr = true; 2127 // Fallthrough 2128 case Instruction::DIV_INT: 2129 op = kOpDiv; 2130 is_div_rem = true; 2131 break; 2132 /* NOTE: returns in kArg1 */ 2133 case Instruction::REM_INT_2ADDR: 2134 is_two_addr = true; 2135 // Fallthrough 2136 case Instruction::REM_INT: 2137 op = kOpRem; 2138 is_div_rem = true; 2139 break; 2140 case Instruction::AND_INT_2ADDR: 2141 is_two_addr = true; 2142 // Fallthrough 2143 case Instruction::AND_INT: 2144 op = kOpAnd; 2145 break; 2146 case Instruction::OR_INT_2ADDR: 2147 is_two_addr = true; 2148 // Fallthrough 2149 case Instruction::OR_INT: 2150 op = kOpOr; 2151 break; 2152 case Instruction::XOR_INT_2ADDR: 2153 is_two_addr = true; 2154 // Fallthrough 2155 case Instruction::XOR_INT: 2156 op = kOpXor; 2157 break; 2158 case Instruction::SHL_INT_2ADDR: 2159 is_two_addr = true; 2160 // Fallthrough 2161 case Instruction::SHL_INT: 2162 shift_op = true; 2163 op = kOpLsl; 2164 break; 2165 case Instruction::SHR_INT_2ADDR: 2166 is_two_addr = true; 2167 // Fallthrough 2168 case Instruction::SHR_INT: 2169 shift_op = true; 2170 op = kOpAsr; 2171 break; 2172 case Instruction::USHR_INT_2ADDR: 2173 is_two_addr = true; 2174 // Fallthrough 2175 case Instruction::USHR_INT: 2176 shift_op = true; 2177 op = kOpLsr; 2178 break; 2179 default: 2180 LOG(FATAL) << "Invalid word arith op: " << opcode; 2181 } 2182 2183 // Can we convert to a two address instruction? 2184 if (!is_two_addr && 2185 (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == 2186 mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { 2187 is_two_addr = true; 2188 } 2189 2190 if (!GenerateTwoOperandInstructions()) { 2191 is_two_addr = false; 2192 } 2193 2194 // Get the div/rem stuff out of the way. 2195 if (is_div_rem) { 2196 rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); 2197 StoreValue(rl_dest, rl_result); 2198 return; 2199 } 2200 2201 if (unary) { 2202 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2203 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2204 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2205 OpRegReg(op, rl_result.reg, rl_lhs.reg); 2206 } else { 2207 if (shift_op) { 2208 // X86 doesn't require masking and must use ECX. 2209 RegStorage t_reg = TargetReg(kCount); // rCX 2210 LoadValueDirectFixed(rl_rhs, t_reg); 2211 if (is_two_addr) { 2212 // Can we do this directly into memory? 2213 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2214 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2215 if (rl_result.location != kLocPhysReg) { 2216 // Okay, we can do this into memory 2217 OpMemReg(op, rl_result, t_reg.GetReg()); 2218 FreeTemp(t_reg); 2219 return; 2220 } else if (!rl_result.reg.IsFloat()) { 2221 // Can do this directly into the result register 2222 OpRegReg(op, rl_result.reg, t_reg); 2223 FreeTemp(t_reg); 2224 StoreFinalValue(rl_dest, rl_result); 2225 return; 2226 } 2227 } 2228 // Three address form, or we can't do directly. 2229 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2230 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2231 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); 2232 FreeTemp(t_reg); 2233 } else { 2234 // Multiply is 3 operand only (sort of). 2235 if (is_two_addr && op != kOpMul) { 2236 // Can we do this directly into memory? 2237 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2238 if (rl_result.location == kLocPhysReg) { 2239 // Ensure res is in a core reg 2240 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2241 // Can we do this from memory directly? 2242 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2243 if (rl_rhs.location != kLocPhysReg) { 2244 OpRegMem(op, rl_result.reg, rl_rhs); 2245 StoreFinalValue(rl_dest, rl_result); 2246 return; 2247 } else if (!rl_rhs.reg.IsFloat()) { 2248 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2249 StoreFinalValue(rl_dest, rl_result); 2250 return; 2251 } 2252 } 2253 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2254 // It might happen rl_rhs and rl_dest are the same VR 2255 // in this case rl_dest is in reg after LoadValue while 2256 // rl_result is not updated yet, so do this 2257 rl_result = UpdateLocTyped(rl_dest, kCoreReg); 2258 if (rl_result.location != kLocPhysReg) { 2259 // Okay, we can do this into memory. 2260 OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); 2261 return; 2262 } else if (!rl_result.reg.IsFloat()) { 2263 // Can do this directly into the result register. 2264 OpRegReg(op, rl_result.reg, rl_rhs.reg); 2265 StoreFinalValue(rl_dest, rl_result); 2266 return; 2267 } else { 2268 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2269 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2270 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2271 } 2272 } else { 2273 // Try to use reg/memory instructions. 2274 rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); 2275 rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); 2276 // We can't optimize with FP registers. 2277 if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { 2278 // Something is difficult, so fall back to the standard case. 2279 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2280 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2281 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2282 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2283 } else { 2284 // We can optimize by moving to result and using memory operands. 2285 if (rl_rhs.location != kLocPhysReg) { 2286 // Force LHS into result. 2287 // We should be careful with order here 2288 // If rl_dest and rl_lhs points to the same VR we should load first 2289 // If the are different we should find a register first for dest 2290 if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { 2291 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2292 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2293 // No-op if these are the same. 2294 OpRegCopy(rl_result.reg, rl_lhs.reg); 2295 } else { 2296 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2297 LoadValueDirect(rl_lhs, rl_result.reg); 2298 } 2299 OpRegMem(op, rl_result.reg, rl_rhs); 2300 } else if (rl_lhs.location != kLocPhysReg) { 2301 // RHS is in a register; LHS is in memory. 2302 if (op != kOpSub) { 2303 // Force RHS into result and operate on memory. 2304 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2305 OpRegCopy(rl_result.reg, rl_rhs.reg); 2306 OpRegMem(op, rl_result.reg, rl_lhs); 2307 } else { 2308 // Subtraction isn't commutative. 2309 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2310 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2311 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2312 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2313 } 2314 } else { 2315 // Both are in registers. 2316 rl_lhs = LoadValue(rl_lhs, kCoreReg); 2317 rl_rhs = LoadValue(rl_rhs, kCoreReg); 2318 rl_result = EvalLoc(rl_dest, kCoreReg, true); 2319 OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); 2320 } 2321 } 2322 } 2323 } 2324 } 2325 StoreValue(rl_dest, rl_result); 2326} 2327 2328bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { 2329 // If we have non-core registers, then we can't do good things. 2330 if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { 2331 return false; 2332 } 2333 if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { 2334 return false; 2335 } 2336 2337 // Everything will be fine :-). 2338 return true; 2339} 2340} // namespace art 2341