utility_x86.cc revision 2c1ed456dcdb027d097825dd98dbe48c71599b6c 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
18#include "dex/quick/mir_to_lir-inl.h"
19#include "dex/dataflow_iterator-inl.h"
20#include "x86_lir.h"
21
22namespace art {
23
24/* This file contains codegen for the X86 ISA */
25
26LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) {
27  int opcode;
28  /* must be both DOUBLE or both not DOUBLE */
29  DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src));
30  if (X86_DOUBLEREG(r_dest)) {
31    opcode = kX86MovsdRR;
32  } else {
33    if (X86_SINGLEREG(r_dest)) {
34      if (X86_SINGLEREG(r_src)) {
35        opcode = kX86MovssRR;
36      } else {  // Fpr <- Gpr
37        opcode = kX86MovdxrRR;
38      }
39    } else {  // Gpr <- Fpr
40      DCHECK(X86_SINGLEREG(r_src));
41      opcode = kX86MovdrxRR;
42    }
43  }
44  DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL);
45  LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src);
46  if (r_dest == r_src) {
47    res->flags.is_nop = true;
48  }
49  return res;
50}
51
52bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) {
53  return true;
54}
55
56bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) {
57  return false;
58}
59
60bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) {
61  return true;
62}
63
64bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) {
65  return value == 0;
66}
67
68/*
69 * Load a immediate using a shortcut if possible; otherwise
70 * grab from the per-translation literal pool.  If target is
71 * a high register, build constant into a low register and copy.
72 *
73 * No additional register clobbering operation performed. Use this version when
74 * 1) r_dest is freshly returned from AllocTemp or
75 * 2) The codegen is under fixed register usage
76 */
77LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) {
78  int r_dest_save = r_dest;
79  if (X86_FPREG(r_dest)) {
80    if (value == 0) {
81      return NewLIR2(kX86XorpsRR, r_dest, r_dest);
82    }
83    DCHECK(X86_SINGLEREG(r_dest));
84    r_dest = AllocTemp();
85  }
86
87  LIR *res;
88  if (value == 0) {
89    res = NewLIR2(kX86Xor32RR, r_dest, r_dest);
90  } else {
91    // Note, there is no byte immediate form of a 32 bit immediate move.
92    res = NewLIR2(kX86Mov32RI, r_dest, value);
93  }
94
95  if (X86_FPREG(r_dest_save)) {
96    NewLIR2(kX86MovdxrRR, r_dest_save, r_dest);
97    FreeTemp(r_dest);
98  }
99
100  return res;
101}
102
103LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
104  LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/);
105  res->target = target;
106  return res;
107}
108
109LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
110  LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */,
111                        X86ConditionEncoding(cc));
112  branch->target = target;
113  return branch;
114}
115
116LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) {
117  X86OpCode opcode = kX86Bkpt;
118  switch (op) {
119    case kOpNeg: opcode = kX86Neg32R; break;
120    case kOpNot: opcode = kX86Not32R; break;
121    case kOpRev: opcode = kX86Bswap32R; break;
122    case kOpBlx: opcode = kX86CallR; break;
123    default:
124      LOG(FATAL) << "Bad case in OpReg " << op;
125  }
126  return NewLIR1(opcode, r_dest_src);
127}
128
129LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
130  X86OpCode opcode = kX86Bkpt;
131  bool byte_imm = IS_SIMM8(value);
132  DCHECK(!X86_FPREG(r_dest_src1));
133  switch (op) {
134    case kOpLsl: opcode = kX86Sal32RI; break;
135    case kOpLsr: opcode = kX86Shr32RI; break;
136    case kOpAsr: opcode = kX86Sar32RI; break;
137    case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break;
138    case kOpOr:  opcode = byte_imm ? kX86Or32RI8  : kX86Or32RI;  break;
139    case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break;
140    // case kOpSbb: opcode = kX86Sbb32RI; break;
141    case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break;
142    case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break;
143    case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break;
144    case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break;
145    case kOpMov:
146      /*
147       * Moving the constant zero into register can be specialized as an xor of the register.
148       * However, that sets eflags while the move does not. For that reason here, always do
149       * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead.
150       */
151      opcode = kX86Mov32RI;
152      break;
153    case kOpMul:
154      opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI;
155      return NewLIR3(opcode, r_dest_src1, r_dest_src1, value);
156    default:
157      LOG(FATAL) << "Bad case in OpRegImm " << op;
158  }
159  return NewLIR2(opcode, r_dest_src1, value);
160}
161
162LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
163    X86OpCode opcode = kX86Nop;
164    bool src2_must_be_cx = false;
165    switch (op) {
166        // X86 unary opcodes
167      case kOpMvn:
168        OpRegCopy(r_dest_src1, r_src2);
169        return OpReg(kOpNot, r_dest_src1);
170      case kOpNeg:
171        OpRegCopy(r_dest_src1, r_src2);
172        return OpReg(kOpNeg, r_dest_src1);
173      case kOpRev:
174        OpRegCopy(r_dest_src1, r_src2);
175        return OpReg(kOpRev, r_dest_src1);
176      case kOpRevsh:
177        OpRegCopy(r_dest_src1, r_src2);
178        OpReg(kOpRev, r_dest_src1);
179        return OpRegImm(kOpAsr, r_dest_src1, 16);
180        // X86 binary opcodes
181      case kOpSub: opcode = kX86Sub32RR; break;
182      case kOpSbc: opcode = kX86Sbb32RR; break;
183      case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break;
184      case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break;
185      case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break;
186      case kOpMov: opcode = kX86Mov32RR; break;
187      case kOpCmp: opcode = kX86Cmp32RR; break;
188      case kOpAdd: opcode = kX86Add32RR; break;
189      case kOpAdc: opcode = kX86Adc32RR; break;
190      case kOpAnd: opcode = kX86And32RR; break;
191      case kOpOr:  opcode = kX86Or32RR; break;
192      case kOpXor: opcode = kX86Xor32RR; break;
193      case kOp2Byte:
194        // Use shifts instead of a byte operand if the source can't be byte accessed.
195        if (r_src2 >= 4) {
196          NewLIR2(kX86Mov32RR, r_dest_src1, r_src2);
197          NewLIR2(kX86Sal32RI, r_dest_src1, 24);
198          return NewLIR2(kX86Sar32RI, r_dest_src1, 24);
199        } else {
200          opcode = kX86Movsx8RR;
201        }
202        break;
203      case kOp2Short: opcode = kX86Movsx16RR; break;
204      case kOp2Char: opcode = kX86Movzx16RR; break;
205      case kOpMul: opcode = kX86Imul32RR; break;
206      default:
207        LOG(FATAL) << "Bad case in OpRegReg " << op;
208        break;
209    }
210    CHECK(!src2_must_be_cx || r_src2 == rCX);
211    return NewLIR2(opcode, r_dest_src1, r_src2);
212}
213
214LIR* X86Mir2Lir::OpMovRegMem(int r_dest, int r_base, int offset, MoveType move_type) {
215  DCHECK(!(X86_FPREG(r_base)));
216
217  X86OpCode opcode = kX86Nop;
218  switch (move_type) {
219    case kMov8GP:
220      CHECK(!X86_FPREG(r_dest));
221      opcode = kX86Mov8RM;
222      break;
223    case kMov16GP:
224      CHECK(!X86_FPREG(r_dest));
225      opcode = kX86Mov16RM;
226      break;
227    case kMov32GP:
228      CHECK(!X86_FPREG(r_dest));
229      opcode = kX86Mov32RM;
230      break;
231    case kMov32FP:
232      CHECK(X86_FPREG(r_dest));
233      opcode = kX86MovssRM;
234      break;
235    case kMov64FP:
236      CHECK(X86_FPREG(r_dest));
237      opcode = kX86MovsdRM;
238      break;
239    case kMovU128FP:
240      CHECK(X86_FPREG(r_dest));
241      opcode = kX86MovupsRM;
242      break;
243    case kMovA128FP:
244      CHECK(X86_FPREG(r_dest));
245      opcode = kX86MovapsRM;
246      break;
247    case kMovLo128FP:
248      CHECK(X86_FPREG(r_dest));
249      opcode = kX86MovlpsRM;
250      break;
251    case kMovHi128FP:
252      CHECK(X86_FPREG(r_dest));
253      opcode = kX86MovhpsRM;
254      break;
255    case kMov64GP:
256    case kMovLo64FP:
257    case kMovHi64FP:
258    default:
259      LOG(FATAL) << "Bad case in OpMovRegMem";
260      break;
261  }
262
263  return NewLIR3(opcode, r_dest, r_base, offset);
264}
265
266LIR* X86Mir2Lir::OpMovMemReg(int r_base, int offset, int r_src, MoveType move_type) {
267  DCHECK(!(X86_FPREG(r_base)));
268
269  X86OpCode opcode = kX86Nop;
270  switch (move_type) {
271    case kMov8GP:
272      CHECK(!X86_FPREG(r_src));
273      opcode = kX86Mov8MR;
274      break;
275    case kMov16GP:
276      CHECK(!X86_FPREG(r_src));
277      opcode = kX86Mov16MR;
278      break;
279    case kMov32GP:
280      CHECK(!X86_FPREG(r_src));
281      opcode = kX86Mov32MR;
282      break;
283    case kMov32FP:
284      CHECK(X86_FPREG(r_src));
285      opcode = kX86MovssMR;
286      break;
287    case kMov64FP:
288      CHECK(X86_FPREG(r_src));
289      opcode = kX86MovsdMR;
290      break;
291    case kMovU128FP:
292      CHECK(X86_FPREG(r_src));
293      opcode = kX86MovupsMR;
294      break;
295    case kMovA128FP:
296      CHECK(X86_FPREG(r_src));
297      opcode = kX86MovapsMR;
298      break;
299    case kMovLo128FP:
300      CHECK(X86_FPREG(r_src));
301      opcode = kX86MovlpsMR;
302      break;
303    case kMovHi128FP:
304      CHECK(X86_FPREG(r_src));
305      opcode = kX86MovhpsMR;
306      break;
307    case kMov64GP:
308    case kMovLo64FP:
309    case kMovHi64FP:
310    default:
311      LOG(FATAL) << "Bad case in OpMovMemReg";
312      break;
313  }
314
315  return NewLIR3(opcode, r_base, offset, r_src);
316}
317
318LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, int r_dest, int r_src) {
319  // The only conditional reg to reg operation supported is Cmov
320  DCHECK_EQ(op, kOpCmov);
321  return NewLIR3(kX86Cmov32RRC, r_dest, r_src, X86ConditionEncoding(cc));
322}
323
324LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
325              int offset) {
326  X86OpCode opcode = kX86Nop;
327  switch (op) {
328      // X86 binary opcodes
329    case kOpSub: opcode = kX86Sub32RM; break;
330    case kOpMov: opcode = kX86Mov32RM; break;
331    case kOpCmp: opcode = kX86Cmp32RM; break;
332    case kOpAdd: opcode = kX86Add32RM; break;
333    case kOpAnd: opcode = kX86And32RM; break;
334    case kOpOr:  opcode = kX86Or32RM; break;
335    case kOpXor: opcode = kX86Xor32RM; break;
336    case kOp2Byte: opcode = kX86Movsx8RM; break;
337    case kOp2Short: opcode = kX86Movsx16RM; break;
338    case kOp2Char: opcode = kX86Movzx16RM; break;
339    case kOpMul:
340    default:
341      LOG(FATAL) << "Bad case in OpRegMem " << op;
342      break;
343  }
344  LIR *l = NewLIR3(opcode, r_dest, rBase, offset);
345  if (rBase == rX86_SP) {
346    AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */);
347  }
348  return l;
349}
350
351LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) {
352  DCHECK_NE(rl_dest.location, kLocPhysReg);
353  int displacement = SRegOffset(rl_dest.s_reg_low);
354  X86OpCode opcode = kX86Nop;
355  switch (op) {
356    case kOpSub: opcode = kX86Sub32MR; break;
357    case kOpMov: opcode = kX86Mov32MR; break;
358    case kOpCmp: opcode = kX86Cmp32MR; break;
359    case kOpAdd: opcode = kX86Add32MR; break;
360    case kOpAnd: opcode = kX86And32MR; break;
361    case kOpOr:  opcode = kX86Or32MR; break;
362    case kOpXor: opcode = kX86Xor32MR; break;
363    case kOpLsl: opcode = kX86Sal32MC; break;
364    case kOpLsr: opcode = kX86Shr32MC; break;
365    case kOpAsr: opcode = kX86Sar32MC; break;
366    default:
367      LOG(FATAL) << "Bad case in OpMemReg " << op;
368      break;
369  }
370  LIR *l = NewLIR3(opcode, rX86_SP, displacement, r_value);
371  AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */);
372  return l;
373}
374
375LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, RegLocation rl_value) {
376  DCHECK_NE(rl_value.location, kLocPhysReg);
377  int displacement = SRegOffset(rl_value.s_reg_low);
378  X86OpCode opcode = kX86Nop;
379  switch (op) {
380    case kOpSub: opcode = kX86Sub32RM; break;
381    case kOpMov: opcode = kX86Mov32RM; break;
382    case kOpCmp: opcode = kX86Cmp32RM; break;
383    case kOpAdd: opcode = kX86Add32RM; break;
384    case kOpAnd: opcode = kX86And32RM; break;
385    case kOpOr:  opcode = kX86Or32RM; break;
386    case kOpXor: opcode = kX86Xor32RM; break;
387    case kOpMul: opcode = kX86Imul32RM; break;
388    default:
389      LOG(FATAL) << "Bad case in OpRegMem " << op;
390      break;
391  }
392  LIR *l = NewLIR3(opcode, r_dest, rX86_SP, displacement);
393  AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */);
394  return l;
395}
396
397LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
398                 int r_src2) {
399  if (r_dest != r_src1 && r_dest != r_src2) {
400    if (op == kOpAdd) {  // lea special case, except can't encode rbp as base
401      if (r_src1 == r_src2) {
402        OpRegCopy(r_dest, r_src1);
403        return OpRegImm(kOpLsl, r_dest, 1);
404      } else if (r_src1 != rBP) {
405        return NewLIR5(kX86Lea32RA, r_dest, r_src1 /* base */,
406                       r_src2 /* index */, 0 /* scale */, 0 /* disp */);
407      } else {
408        return NewLIR5(kX86Lea32RA, r_dest, r_src2 /* base */,
409                       r_src1 /* index */, 0 /* scale */, 0 /* disp */);
410      }
411    } else {
412      OpRegCopy(r_dest, r_src1);
413      return OpRegReg(op, r_dest, r_src2);
414    }
415  } else if (r_dest == r_src1) {
416    return OpRegReg(op, r_dest, r_src2);
417  } else {  // r_dest == r_src2
418    switch (op) {
419      case kOpSub:  // non-commutative
420        OpReg(kOpNeg, r_dest);
421        op = kOpAdd;
422        break;
423      case kOpSbc:
424      case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: {
425        int t_reg = AllocTemp();
426        OpRegCopy(t_reg, r_src1);
427        OpRegReg(op, t_reg, r_src2);
428        LIR* res = OpRegCopy(r_dest, t_reg);
429        FreeTemp(t_reg);
430        return res;
431      }
432      case kOpAdd:  // commutative
433      case kOpOr:
434      case kOpAdc:
435      case kOpAnd:
436      case kOpXor:
437        break;
438      default:
439        LOG(FATAL) << "Bad case in OpRegRegReg " << op;
440    }
441    return OpRegReg(op, r_dest, r_src1);
442  }
443}
444
445LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
446                 int value) {
447  if (op == kOpMul) {
448    X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
449    return NewLIR3(opcode, r_dest, r_src, value);
450  } else if (op == kOpAnd) {
451    if (value == 0xFF && r_src < 4) {
452      return NewLIR2(kX86Movzx8RR, r_dest, r_src);
453    } else if (value == 0xFFFF) {
454      return NewLIR2(kX86Movzx16RR, r_dest, r_src);
455    }
456  }
457  if (r_dest != r_src) {
458    if (false && op == kOpLsl && value >= 0 && value <= 3) {  // lea shift special case
459      // TODO: fix bug in LEA encoding when disp == 0
460      return NewLIR5(kX86Lea32RA, r_dest,  r5sib_no_base /* base */,
461                     r_src /* index */, value /* scale */, 0 /* disp */);
462    } else if (op == kOpAdd) {  // lea add special case
463      return NewLIR5(kX86Lea32RA, r_dest, r_src /* base */,
464                     r4sib_no_index /* index */, 0 /* scale */, value /* disp */);
465    }
466    OpRegCopy(r_dest, r_src);
467  }
468  return OpRegImm(op, r_dest, value);
469}
470
471LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset thread_offset) {
472  X86OpCode opcode = kX86Bkpt;
473  switch (op) {
474    case kOpBlx: opcode = kX86CallT;  break;
475    default:
476      LOG(FATAL) << "Bad opcode: " << op;
477      break;
478  }
479  return NewLIR1(opcode, thread_offset.Int32Value());
480}
481
482LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) {
483  X86OpCode opcode = kX86Bkpt;
484  switch (op) {
485    case kOpBlx: opcode = kX86CallM;  break;
486    default:
487      LOG(FATAL) << "Bad opcode: " << op;
488      break;
489  }
490  return NewLIR2(opcode, rBase, disp);
491}
492
493LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
494    int32_t val_lo = Low32Bits(value);
495    int32_t val_hi = High32Bits(value);
496    LIR *res;
497    if (X86_FPREG(r_dest_lo)) {
498      DCHECK(X86_FPREG(r_dest_hi));  // ignore r_dest_hi
499      DCHECK_EQ(r_dest_lo, r_dest_hi);
500      if (value == 0) {
501        return NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo);
502      } else if (base_of_code_ != nullptr) {
503        // We will load the value from the literal area.
504        LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi);
505        if (data_target == NULL) {
506          data_target = AddWideData(&literal_list_, val_lo, val_hi);
507        }
508
509        // Address the start of the method
510        RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
511        rl_method = LoadValue(rl_method, kCoreReg);
512
513        // Load the proper value from the literal area.
514        // We don't know the proper offset for the value, so pick one that will force
515        // 4 byte offset.  We will fix this up in the assembler later to have the right
516        // value.
517        res = LoadBaseDisp(rl_method.reg.GetReg(), 256 /* bogus */, r_dest_lo, kDouble, INVALID_SREG);
518        res->target = data_target;
519        res->flags.fixup = kFixupLoad;
520        SetMemRefType(res, true, kLiteral);
521        store_method_addr_used_ = true;
522      } else {
523        if (val_lo == 0) {
524          res = NewLIR2(kX86XorpsRR, r_dest_lo, r_dest_lo);
525        } else {
526          res = LoadConstantNoClobber(r_dest_lo, val_lo);
527        }
528        if (val_hi != 0) {
529          r_dest_hi = AllocTempDouble();
530          LoadConstantNoClobber(r_dest_hi, val_hi);
531          NewLIR2(kX86PunpckldqRR, r_dest_lo, r_dest_hi);
532          FreeTemp(r_dest_hi);
533        }
534      }
535    } else {
536      res = LoadConstantNoClobber(r_dest_lo, val_lo);
537      LoadConstantNoClobber(r_dest_hi, val_hi);
538    }
539    return res;
540}
541
542LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale,
543                                     int displacement, int r_dest, int r_dest_hi, OpSize size,
544                                     int s_reg) {
545  LIR *load = NULL;
546  LIR *load2 = NULL;
547  bool is_array = r_index != INVALID_REG;
548  bool pair = false;
549  bool is64bit = false;
550  X86OpCode opcode = kX86Nop;
551  switch (size) {
552    case kLong:
553    case kDouble:
554      is64bit = true;
555      if (X86_FPREG(r_dest)) {
556        opcode = is_array ? kX86MovsdRA : kX86MovsdRM;
557      } else {
558        pair = true;
559        opcode = is_array ? kX86Mov32RA  : kX86Mov32RM;
560      }
561      // TODO: double store is to unaligned address
562      DCHECK_EQ((displacement & 0x3), 0);
563      break;
564    case kWord:
565    case kSingle:
566      opcode = is_array ? kX86Mov32RA : kX86Mov32RM;
567      if (X86_FPREG(r_dest)) {
568        opcode = is_array ? kX86MovssRA : kX86MovssRM;
569        DCHECK(X86_SINGLEREG(r_dest));
570      }
571      DCHECK_EQ((displacement & 0x3), 0);
572      break;
573    case kUnsignedHalf:
574      opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM;
575      DCHECK_EQ((displacement & 0x1), 0);
576      break;
577    case kSignedHalf:
578      opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM;
579      DCHECK_EQ((displacement & 0x1), 0);
580      break;
581    case kUnsignedByte:
582      opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM;
583      break;
584    case kSignedByte:
585      opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM;
586      break;
587    default:
588      LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody";
589  }
590
591  if (!is_array) {
592    if (!pair) {
593      load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
594    } else {
595      if (rBase == r_dest) {
596        load2 = NewLIR3(opcode, r_dest_hi, rBase,
597                        displacement + HIWORD_OFFSET);
598        load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
599      } else {
600        load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
601        load2 = NewLIR3(opcode, r_dest_hi, rBase,
602                        displacement + HIWORD_OFFSET);
603      }
604    }
605    if (rBase == rX86_SP) {
606      AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
607                              true /* is_load */, is64bit);
608      if (pair) {
609        AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
610                                true /* is_load */, is64bit);
611      }
612    }
613  } else {
614    if (!pair) {
615      load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
616                     displacement + LOWORD_OFFSET);
617    } else {
618      if (rBase == r_dest) {
619        if (r_dest_hi == r_index) {
620          // We can't use either register for the first load.
621          int temp = AllocTemp();
622          load2 = NewLIR5(opcode, temp, rBase, r_index, scale,
623                          displacement + HIWORD_OFFSET);
624          load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
625                         displacement + LOWORD_OFFSET);
626          OpRegCopy(r_dest_hi, temp);
627          FreeTemp(temp);
628        } else {
629          load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
630                          displacement + HIWORD_OFFSET);
631          load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
632                         displacement + LOWORD_OFFSET);
633        }
634      } else {
635        if (r_dest == r_index) {
636          // We can't use either register for the first load.
637          int temp = AllocTemp();
638          load = NewLIR5(opcode, temp, rBase, r_index, scale,
639                         displacement + LOWORD_OFFSET);
640          load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
641                          displacement + HIWORD_OFFSET);
642          OpRegCopy(r_dest, temp);
643          FreeTemp(temp);
644        } else {
645          load = NewLIR5(opcode, r_dest, rBase, r_index, scale,
646                         displacement + LOWORD_OFFSET);
647          load2 = NewLIR5(opcode, r_dest_hi, rBase, r_index, scale,
648                          displacement + HIWORD_OFFSET);
649        }
650      }
651    }
652  }
653
654  return load;
655}
656
657/* Load value from base + scaled index. */
658LIR* X86Mir2Lir::LoadBaseIndexed(int rBase,
659                     int r_index, int r_dest, int scale, OpSize size) {
660  return LoadBaseIndexedDisp(rBase, r_index, scale, 0,
661                             r_dest, INVALID_REG, size, INVALID_SREG);
662}
663
664LIR* X86Mir2Lir::LoadBaseDisp(int rBase, int displacement,
665                  int r_dest, OpSize size, int s_reg) {
666  return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
667                             r_dest, INVALID_REG, size, s_reg);
668}
669
670LIR* X86Mir2Lir::LoadBaseDispWide(int rBase, int displacement,
671                      int r_dest_lo, int r_dest_hi, int s_reg) {
672  return LoadBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
673                             r_dest_lo, r_dest_hi, kLong, s_reg);
674}
675
676LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale,
677                                      int displacement, int r_src, int r_src_hi, OpSize size,
678                                      int s_reg) {
679  LIR *store = NULL;
680  LIR *store2 = NULL;
681  bool is_array = r_index != INVALID_REG;
682  bool pair = false;
683  bool is64bit = false;
684  X86OpCode opcode = kX86Nop;
685  switch (size) {
686    case kLong:
687    case kDouble:
688      is64bit = true;
689      if (X86_FPREG(r_src)) {
690        opcode = is_array ? kX86MovsdAR : kX86MovsdMR;
691      } else {
692        pair = true;
693        opcode = is_array ? kX86Mov32AR  : kX86Mov32MR;
694      }
695      // TODO: double store is to unaligned address
696      DCHECK_EQ((displacement & 0x3), 0);
697      break;
698    case kWord:
699    case kSingle:
700      opcode = is_array ? kX86Mov32AR : kX86Mov32MR;
701      if (X86_FPREG(r_src)) {
702        opcode = is_array ? kX86MovssAR : kX86MovssMR;
703        DCHECK(X86_SINGLEREG(r_src));
704      }
705      DCHECK_EQ((displacement & 0x3), 0);
706      break;
707    case kUnsignedHalf:
708    case kSignedHalf:
709      opcode = is_array ? kX86Mov16AR : kX86Mov16MR;
710      DCHECK_EQ((displacement & 0x1), 0);
711      break;
712    case kUnsignedByte:
713    case kSignedByte:
714      opcode = is_array ? kX86Mov8AR : kX86Mov8MR;
715      break;
716    default:
717      LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody";
718  }
719
720  if (!is_array) {
721    if (!pair) {
722      store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
723    } else {
724      store = NewLIR3(opcode, rBase, displacement + LOWORD_OFFSET, r_src);
725      store2 = NewLIR3(opcode, rBase, displacement + HIWORD_OFFSET, r_src_hi);
726    }
727    if (rBase == rX86_SP) {
728      AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
729                              false /* is_load */, is64bit);
730      if (pair) {
731        AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
732                                false /* is_load */, is64bit);
733      }
734    }
735  } else {
736    if (!pair) {
737      store = NewLIR5(opcode, rBase, r_index, scale,
738                      displacement + LOWORD_OFFSET, r_src);
739    } else {
740      store = NewLIR5(opcode, rBase, r_index, scale,
741                      displacement + LOWORD_OFFSET, r_src);
742      store2 = NewLIR5(opcode, rBase, r_index, scale,
743                       displacement + HIWORD_OFFSET, r_src_hi);
744    }
745  }
746
747  return store;
748}
749
750/* store value base base + scaled index. */
751LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
752                      int scale, OpSize size) {
753  return StoreBaseIndexedDisp(rBase, r_index, scale, 0,
754                              r_src, INVALID_REG, size, INVALID_SREG);
755}
756
757LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement,
758                               int r_src, OpSize size) {
759    return StoreBaseIndexedDisp(rBase, INVALID_REG, 0,
760                                displacement, r_src, INVALID_REG, size,
761                                INVALID_SREG);
762}
763
764LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement,
765                                   int r_src_lo, int r_src_hi) {
766  return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
767                              r_src_lo, r_src_hi, kLong, INVALID_SREG);
768}
769
770/*
771 * Copy a long value in Core registers to an XMM register
772 *
773 */
774void X86Mir2Lir::OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg) {
775  NewLIR2(kX86MovdxrRR, fp_reg, low_reg);
776  int tmp_reg = AllocTempDouble();
777  NewLIR2(kX86MovdxrRR, tmp_reg, high_reg);
778  NewLIR2(kX86PunpckldqRR, fp_reg, tmp_reg);
779  FreeTemp(tmp_reg);
780}
781
782LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg,
783                                   int offset, int check_value, LIR* target) {
784    NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg, offset,
785            check_value);
786    LIR* branch = OpCondBranch(cond, target);
787    return branch;
788}
789
790void X86Mir2Lir::AnalyzeMIR() {
791  // Assume we don't need a pointer to the base of the code.
792  cu_->NewTimingSplit("X86 MIR Analysis");
793  store_method_addr_ = false;
794
795  // Walk the MIR looking for interesting items.
796  PreOrderDfsIterator iter(mir_graph_);
797  BasicBlock* curr_bb = iter.Next();
798  while (curr_bb != NULL) {
799    AnalyzeBB(curr_bb);
800    curr_bb = iter.Next();
801  }
802
803  // Did we need a pointer to the method code?
804  if (store_method_addr_) {
805    base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, false);
806  } else {
807    base_of_code_ = nullptr;
808  }
809}
810
811void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) {
812  if (bb->block_type == kDead) {
813    // Ignore dead blocks
814    return;
815  }
816
817  for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
818    int opcode = mir->dalvikInsn.opcode;
819    if (opcode >= kMirOpFirst) {
820      AnalyzeExtendedMIR(opcode, bb, mir);
821    } else {
822      AnalyzeMIR(opcode, bb, mir);
823    }
824  }
825}
826
827
828void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) {
829  switch (opcode) {
830    // Instructions referencing doubles.
831    case kMirOpFusedCmplDouble:
832    case kMirOpFusedCmpgDouble:
833      AnalyzeFPInstruction(opcode, bb, mir);
834      break;
835    default:
836      // Ignore the rest.
837      break;
838  }
839}
840
841void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) {
842  // Looking for
843  // - Do we need a pointer to the code (used for packed switches and double lits)?
844
845  switch (opcode) {
846    // Instructions referencing doubles.
847    case Instruction::CMPL_DOUBLE:
848    case Instruction::CMPG_DOUBLE:
849    case Instruction::NEG_DOUBLE:
850    case Instruction::ADD_DOUBLE:
851    case Instruction::SUB_DOUBLE:
852    case Instruction::MUL_DOUBLE:
853    case Instruction::DIV_DOUBLE:
854    case Instruction::REM_DOUBLE:
855    case Instruction::ADD_DOUBLE_2ADDR:
856    case Instruction::SUB_DOUBLE_2ADDR:
857    case Instruction::MUL_DOUBLE_2ADDR:
858    case Instruction::DIV_DOUBLE_2ADDR:
859    case Instruction::REM_DOUBLE_2ADDR:
860      AnalyzeFPInstruction(opcode, bb, mir);
861      break;
862
863    // Packed switches and array fills need a pointer to the base of the method.
864    case Instruction::FILL_ARRAY_DATA:
865    case Instruction::PACKED_SWITCH:
866      store_method_addr_ = true;
867      break;
868    default:
869      // Other instructions are not interesting yet.
870      break;
871  }
872}
873
874void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) {
875  // Look at all the uses, and see if they are double constants.
876  uint64_t attrs = mir_graph_->oat_data_flow_attributes_[opcode];
877  int next_sreg = 0;
878  if (attrs & DF_UA) {
879    if (attrs & DF_A_WIDE) {
880      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
881      next_sreg += 2;
882    } else {
883      next_sreg++;
884    }
885  }
886  if (attrs & DF_UB) {
887    if (attrs & DF_B_WIDE) {
888      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
889      next_sreg += 2;
890    } else {
891      next_sreg++;
892    }
893  }
894  if (attrs & DF_UC) {
895    if (attrs & DF_C_WIDE) {
896      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
897    }
898  }
899}
900
901void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) {
902  // If this is a double literal, we will want it in the literal pool.
903  if (use.is_const) {
904    store_method_addr_ = true;
905  }
906}
907
908}  // namespace art
909