utility_x86.cc revision 35ba7f3a78d38885ec54e61ed060d2771eeceea7 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "codegen_x86.h"
18#include "dex/quick/mir_to_lir-inl.h"
19#include "dex/dataflow_iterator-inl.h"
20#include "x86_lir.h"
21
22namespace art {
23
24/* This file contains codegen for the X86 ISA */
25
26LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) {
27  int opcode;
28  /* must be both DOUBLE or both not DOUBLE */
29  DCHECK(r_dest.IsFloat() || r_src.IsFloat());
30  DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble());
31  if (r_dest.IsDouble()) {
32    opcode = kX86MovsdRR;
33  } else {
34    if (r_dest.IsSingle()) {
35      if (r_src.IsSingle()) {
36        opcode = kX86MovssRR;
37      } else {  // Fpr <- Gpr
38        opcode = kX86MovdxrRR;
39      }
40    } else {  // Gpr <- Fpr
41      DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits();
42      opcode = kX86MovdrxRR;
43    }
44  }
45  DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL);
46  LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg());
47  if (r_dest == r_src) {
48    res->flags.is_nop = true;
49  }
50  return res;
51}
52
53bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) {
54  return true;
55}
56
57bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) {
58  return false;
59}
60
61bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) {
62  return true;
63}
64
65bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) {
66  return value == 0;
67}
68
69/*
70 * Load a immediate using a shortcut if possible; otherwise
71 * grab from the per-translation literal pool.  If target is
72 * a high register, build constant into a low register and copy.
73 *
74 * No additional register clobbering operation performed. Use this version when
75 * 1) r_dest is freshly returned from AllocTemp or
76 * 2) The codegen is under fixed register usage
77 */
78LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) {
79  RegStorage r_dest_save = r_dest;
80  if (r_dest.IsFloat()) {
81    if (value == 0) {
82      return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg());
83    }
84    r_dest = AllocTemp();
85  }
86
87  LIR *res;
88  if (value == 0) {
89    res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg());
90  } else {
91    // Note, there is no byte immediate form of a 32 bit immediate move.
92    if (r_dest.Is64Bit()) {
93      res = NewLIR2(kX86Mov64RI, r_dest.GetReg(), value);
94    } else {
95      res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value);
96    }
97  }
98
99  if (r_dest_save.IsFloat()) {
100    NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg());
101    FreeTemp(r_dest);
102  }
103
104  return res;
105}
106
107LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
108  LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/);
109  res->target = target;
110  return res;
111}
112
113LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
114  LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */,
115                        X86ConditionEncoding(cc));
116  branch->target = target;
117  return branch;
118}
119
120LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) {
121  X86OpCode opcode = kX86Bkpt;
122  switch (op) {
123    case kOpNeg: opcode = kX86Neg32R; break;
124    case kOpNot: opcode = kX86Not32R; break;
125    case kOpRev: opcode = kX86Bswap32R; break;
126    case kOpBlx: opcode = kX86CallR; break;
127    default:
128      LOG(FATAL) << "Bad case in OpReg " << op;
129  }
130  return NewLIR1(opcode, r_dest_src.GetReg());
131}
132
133LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) {
134  X86OpCode opcode = kX86Bkpt;
135  bool byte_imm = IS_SIMM8(value);
136  DCHECK(!r_dest_src1.IsFloat());
137  if (r_dest_src1.Is64Bit()) {
138    switch (op) {
139      case kOpAdd: opcode = byte_imm ? kX86Add64RI8 : kX86Add64RI; break;
140      case kOpSub: opcode = byte_imm ? kX86Sub64RI8 : kX86Sub64RI; break;
141      default:
142        LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op;
143    }
144  } else {
145    switch (op) {
146      case kOpLsl: opcode = kX86Sal32RI; break;
147      case kOpLsr: opcode = kX86Shr32RI; break;
148      case kOpAsr: opcode = kX86Sar32RI; break;
149      case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break;
150      case kOpOr:  opcode = byte_imm ? kX86Or32RI8  : kX86Or32RI;  break;
151      case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break;
152      // case kOpSbb: opcode = kX86Sbb32RI; break;
153      case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break;
154      case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break;
155      case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break;
156      case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break;
157      case kOpMov:
158        /*
159         * Moving the constant zero into register can be specialized as an xor of the register.
160         * However, that sets eflags while the move does not. For that reason here, always do
161         * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead.
162         */
163        opcode = kX86Mov32RI;
164        break;
165      case kOpMul:
166        opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI;
167        return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value);
168      case kOp2Byte:
169        opcode = kX86Mov32RI;
170        value = static_cast<int8_t>(value);
171        break;
172      case kOp2Short:
173        opcode = kX86Mov32RI;
174        value = static_cast<int16_t>(value);
175        break;
176      case kOp2Char:
177        opcode = kX86Mov32RI;
178        value = static_cast<uint16_t>(value);
179        break;
180      case kOpNeg:
181        opcode = kX86Mov32RI;
182        value = -value;
183        break;
184      default:
185        LOG(FATAL) << "Bad case in OpRegImm " << op;
186    }
187  }
188  return NewLIR2(opcode, r_dest_src1.GetReg(), value);
189}
190
191LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) {
192    X86OpCode opcode = kX86Nop;
193    bool src2_must_be_cx = false;
194    switch (op) {
195        // X86 unary opcodes
196      case kOpMvn:
197        OpRegCopy(r_dest_src1, r_src2);
198        return OpReg(kOpNot, r_dest_src1);
199      case kOpNeg:
200        OpRegCopy(r_dest_src1, r_src2);
201        return OpReg(kOpNeg, r_dest_src1);
202      case kOpRev:
203        OpRegCopy(r_dest_src1, r_src2);
204        return OpReg(kOpRev, r_dest_src1);
205      case kOpRevsh:
206        OpRegCopy(r_dest_src1, r_src2);
207        OpReg(kOpRev, r_dest_src1);
208        return OpRegImm(kOpAsr, r_dest_src1, 16);
209        // X86 binary opcodes
210      case kOpSub: opcode = kX86Sub32RR; break;
211      case kOpSbc: opcode = kX86Sbb32RR; break;
212      case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break;
213      case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break;
214      case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break;
215      case kOpMov: opcode = kX86Mov32RR; break;
216      case kOpCmp: opcode = kX86Cmp32RR; break;
217      case kOpAdd: opcode = kX86Add32RR; break;
218      case kOpAdc: opcode = kX86Adc32RR; break;
219      case kOpAnd: opcode = kX86And32RR; break;
220      case kOpOr:  opcode = kX86Or32RR; break;
221      case kOpXor: opcode = kX86Xor32RR; break;
222      case kOp2Byte:
223        // TODO: there are several instances of this check.  A utility function perhaps?
224        // TODO: Similar to Arm's reg < 8 check.  Perhaps add attribute checks to RegStorage?
225        // Use shifts instead of a byte operand if the source can't be byte accessed.
226        if (r_src2.GetRegNum() >= rs_rX86_SP.GetRegNum()) {
227          NewLIR2(kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg());
228          NewLIR2(kX86Sal32RI, r_dest_src1.GetReg(), 24);
229          return NewLIR2(kX86Sar32RI, r_dest_src1.GetReg(), 24);
230        } else {
231          opcode = kX86Movsx8RR;
232        }
233        break;
234      case kOp2Short: opcode = kX86Movsx16RR; break;
235      case kOp2Char: opcode = kX86Movzx16RR; break;
236      case kOpMul: opcode = kX86Imul32RR; break;
237      default:
238        LOG(FATAL) << "Bad case in OpRegReg " << op;
239        break;
240    }
241    CHECK(!src2_must_be_cx || r_src2.GetReg() == rs_rCX.GetReg());
242    return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg());
243}
244
245LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
246  DCHECK(!r_base.IsFloat());
247  X86OpCode opcode = kX86Nop;
248  int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg();
249  switch (move_type) {
250    case kMov8GP:
251      CHECK(!r_dest.IsFloat());
252      opcode = kX86Mov8RM;
253      break;
254    case kMov16GP:
255      CHECK(!r_dest.IsFloat());
256      opcode = kX86Mov16RM;
257      break;
258    case kMov32GP:
259      CHECK(!r_dest.IsFloat());
260      opcode = kX86Mov32RM;
261      break;
262    case kMov32FP:
263      CHECK(r_dest.IsFloat());
264      opcode = kX86MovssRM;
265      break;
266    case kMov64FP:
267      CHECK(r_dest.IsFloat());
268      opcode = kX86MovsdRM;
269      break;
270    case kMovU128FP:
271      CHECK(r_dest.IsFloat());
272      opcode = kX86MovupsRM;
273      break;
274    case kMovA128FP:
275      CHECK(r_dest.IsFloat());
276      opcode = kX86MovapsRM;
277      break;
278    case kMovLo128FP:
279      CHECK(r_dest.IsFloat());
280      opcode = kX86MovlpsRM;
281      break;
282    case kMovHi128FP:
283      CHECK(r_dest.IsFloat());
284      opcode = kX86MovhpsRM;
285      break;
286    case kMov64GP:
287    case kMovLo64FP:
288    case kMovHi64FP:
289    default:
290      LOG(FATAL) << "Bad case in OpMovRegMem";
291      break;
292  }
293
294  return NewLIR3(opcode, dest, r_base.GetReg(), offset);
295}
296
297LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
298  DCHECK(!r_base.IsFloat());
299  int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg();
300
301  X86OpCode opcode = kX86Nop;
302  switch (move_type) {
303    case kMov8GP:
304      CHECK(!r_src.IsFloat());
305      opcode = kX86Mov8MR;
306      break;
307    case kMov16GP:
308      CHECK(!r_src.IsFloat());
309      opcode = kX86Mov16MR;
310      break;
311    case kMov32GP:
312      CHECK(!r_src.IsFloat());
313      opcode = kX86Mov32MR;
314      break;
315    case kMov32FP:
316      CHECK(r_src.IsFloat());
317      opcode = kX86MovssMR;
318      break;
319    case kMov64FP:
320      CHECK(r_src.IsFloat());
321      opcode = kX86MovsdMR;
322      break;
323    case kMovU128FP:
324      CHECK(r_src.IsFloat());
325      opcode = kX86MovupsMR;
326      break;
327    case kMovA128FP:
328      CHECK(r_src.IsFloat());
329      opcode = kX86MovapsMR;
330      break;
331    case kMovLo128FP:
332      CHECK(r_src.IsFloat());
333      opcode = kX86MovlpsMR;
334      break;
335    case kMovHi128FP:
336      CHECK(r_src.IsFloat());
337      opcode = kX86MovhpsMR;
338      break;
339    case kMov64GP:
340    case kMovLo64FP:
341    case kMovHi64FP:
342    default:
343      LOG(FATAL) << "Bad case in OpMovMemReg";
344      break;
345  }
346
347  return NewLIR3(opcode, r_base.GetReg(), offset, src);
348}
349
350LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) {
351  // The only conditional reg to reg operation supported is Cmov
352  DCHECK_EQ(op, kOpCmov);
353  return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc));
354}
355
356LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) {
357  X86OpCode opcode = kX86Nop;
358  switch (op) {
359      // X86 binary opcodes
360    case kOpSub: opcode = kX86Sub32RM; break;
361    case kOpMov: opcode = kX86Mov32RM; break;
362    case kOpCmp: opcode = kX86Cmp32RM; break;
363    case kOpAdd: opcode = kX86Add32RM; break;
364    case kOpAnd: opcode = kX86And32RM; break;
365    case kOpOr:  opcode = kX86Or32RM; break;
366    case kOpXor: opcode = kX86Xor32RM; break;
367    case kOp2Byte: opcode = kX86Movsx8RM; break;
368    case kOp2Short: opcode = kX86Movsx16RM; break;
369    case kOp2Char: opcode = kX86Movzx16RM; break;
370    case kOpMul:
371    default:
372      LOG(FATAL) << "Bad case in OpRegMem " << op;
373      break;
374  }
375  LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset);
376  if (r_base == rs_rX86_SP) {
377    AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */);
378  }
379  return l;
380}
381
382LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) {
383  DCHECK_NE(rl_dest.location, kLocPhysReg);
384  int displacement = SRegOffset(rl_dest.s_reg_low);
385  X86OpCode opcode = kX86Nop;
386  switch (op) {
387    case kOpSub: opcode = kX86Sub32MR; break;
388    case kOpMov: opcode = kX86Mov32MR; break;
389    case kOpCmp: opcode = kX86Cmp32MR; break;
390    case kOpAdd: opcode = kX86Add32MR; break;
391    case kOpAnd: opcode = kX86And32MR; break;
392    case kOpOr:  opcode = kX86Or32MR; break;
393    case kOpXor: opcode = kX86Xor32MR; break;
394    case kOpLsl: opcode = kX86Sal32MC; break;
395    case kOpLsr: opcode = kX86Shr32MC; break;
396    case kOpAsr: opcode = kX86Sar32MC; break;
397    default:
398      LOG(FATAL) << "Bad case in OpMemReg " << op;
399      break;
400  }
401  LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value);
402  AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */);
403  AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */);
404  return l;
405}
406
407LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) {
408  DCHECK_NE(rl_value.location, kLocPhysReg);
409  int displacement = SRegOffset(rl_value.s_reg_low);
410  X86OpCode opcode = kX86Nop;
411  switch (op) {
412    case kOpSub: opcode = kX86Sub32RM; break;
413    case kOpMov: opcode = kX86Mov32RM; break;
414    case kOpCmp: opcode = kX86Cmp32RM; break;
415    case kOpAdd: opcode = kX86Add32RM; break;
416    case kOpAnd: opcode = kX86And32RM; break;
417    case kOpOr:  opcode = kX86Or32RM; break;
418    case kOpXor: opcode = kX86Xor32RM; break;
419    case kOpMul: opcode = kX86Imul32RM; break;
420    default:
421      LOG(FATAL) << "Bad case in OpRegMem " << op;
422      break;
423  }
424  LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement);
425  AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */);
426  return l;
427}
428
429LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1,
430                             RegStorage r_src2) {
431  if (r_dest != r_src1 && r_dest != r_src2) {
432    if (op == kOpAdd) {  // lea special case, except can't encode rbp as base
433      if (r_src1 == r_src2) {
434        OpRegCopy(r_dest, r_src1);
435        return OpRegImm(kOpLsl, r_dest, 1);
436      } else if (r_src1 != rs_rBP) {
437        return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src1.GetReg() /* base */,
438                       r_src2.GetReg() /* index */, 0 /* scale */, 0 /* disp */);
439      } else {
440        return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src2.GetReg() /* base */,
441                       r_src1.GetReg() /* index */, 0 /* scale */, 0 /* disp */);
442      }
443    } else {
444      OpRegCopy(r_dest, r_src1);
445      return OpRegReg(op, r_dest, r_src2);
446    }
447  } else if (r_dest == r_src1) {
448    return OpRegReg(op, r_dest, r_src2);
449  } else {  // r_dest == r_src2
450    switch (op) {
451      case kOpSub:  // non-commutative
452        OpReg(kOpNeg, r_dest);
453        op = kOpAdd;
454        break;
455      case kOpSbc:
456      case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: {
457        RegStorage t_reg = AllocTemp();
458        OpRegCopy(t_reg, r_src1);
459        OpRegReg(op, t_reg, r_src2);
460        LIR* res = OpRegCopyNoInsert(r_dest, t_reg);
461        AppendLIR(res);
462        FreeTemp(t_reg);
463        return res;
464      }
465      case kOpAdd:  // commutative
466      case kOpOr:
467      case kOpAdc:
468      case kOpAnd:
469      case kOpXor:
470        break;
471      default:
472        LOG(FATAL) << "Bad case in OpRegRegReg " << op;
473    }
474    return OpRegReg(op, r_dest, r_src1);
475  }
476}
477
478LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) {
479  if (op == kOpMul) {
480    X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
481    return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value);
482  } else if (op == kOpAnd) {
483    if (value == 0xFF && r_src.Low4()) {
484      return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg());
485    } else if (value == 0xFFFF) {
486      return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg());
487    }
488  }
489  if (r_dest != r_src) {
490    if (false && op == kOpLsl && value >= 0 && value <= 3) {  // lea shift special case
491      // TODO: fix bug in LEA encoding when disp == 0
492      return NewLIR5(kX86Lea32RA, r_dest.GetReg(),  r5sib_no_base /* base */,
493                     r_src.GetReg() /* index */, value /* scale */, 0 /* disp */);
494    } else if (op == kOpAdd) {  // lea add special case
495      return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src.GetReg() /* base */,
496                     rs_rX86_SP.GetReg()/*r4sib_no_index*/ /* index */, 0 /* scale */, value /* disp */);
497    }
498    OpRegCopy(r_dest, r_src);
499  }
500  return OpRegImm(op, r_dest, value);
501}
502
503LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) {
504  DCHECK_EQ(kX86, cu_->instruction_set);
505  X86OpCode opcode = kX86Bkpt;
506  switch (op) {
507    case kOpBlx: opcode = kX86CallT;  break;
508    case kOpBx: opcode = kX86JmpT;  break;
509    default:
510      LOG(FATAL) << "Bad opcode: " << op;
511      break;
512  }
513  return NewLIR1(opcode, thread_offset.Int32Value());
514}
515
516LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) {
517  DCHECK_EQ(kX86_64, cu_->instruction_set);
518  X86OpCode opcode = kX86Bkpt;
519  switch (op) {
520    case kOpBlx: opcode = kX86CallT;  break;
521    case kOpBx: opcode = kX86JmpT;  break;
522    default:
523      LOG(FATAL) << "Bad opcode: " << op;
524      break;
525  }
526  return NewLIR1(opcode, thread_offset.Int32Value());
527}
528
529LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) {
530  X86OpCode opcode = kX86Bkpt;
531  switch (op) {
532    case kOpBlx: opcode = kX86CallM;  break;
533    default:
534      LOG(FATAL) << "Bad opcode: " << op;
535      break;
536  }
537  return NewLIR2(opcode, r_base.GetReg(), disp);
538}
539
540LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) {
541    int32_t val_lo = Low32Bits(value);
542    int32_t val_hi = High32Bits(value);
543    int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg();
544    LIR *res;
545    bool is_fp = r_dest.IsFloat();
546    // TODO: clean this up once we fully recognize 64-bit storage containers.
547    if (is_fp) {
548      if (value == 0) {
549        return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val);
550      } else if (base_of_code_ != nullptr) {
551        // We will load the value from the literal area.
552        LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi);
553        if (data_target == NULL) {
554          data_target = AddWideData(&literal_list_, val_lo, val_hi);
555        }
556
557        // Address the start of the method
558        RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low);
559        rl_method = LoadValue(rl_method, kCoreReg);
560
561        // Load the proper value from the literal area.
562        // We don't know the proper offset for the value, so pick one that will force
563        // 4 byte offset.  We will fix this up in the assembler later to have the right
564        // value.
565        res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::FloatSolo64(low_reg_val),
566                           kDouble);
567        res->target = data_target;
568        res->flags.fixup = kFixupLoad;
569        SetMemRefType(res, true, kLiteral);
570        store_method_addr_used_ = true;
571      } else {
572        if (val_lo == 0) {
573          res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val);
574        } else {
575          res = LoadConstantNoClobber(RegStorage::Solo32(low_reg_val), val_lo);
576        }
577        if (val_hi != 0) {
578          RegStorage r_dest_hi = AllocTempDouble();
579          LoadConstantNoClobber(r_dest_hi, val_hi);
580          NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetReg());
581          FreeTemp(r_dest_hi);
582        }
583      }
584    } else {
585      res = LoadConstantNoClobber(r_dest.GetLow(), val_lo);
586      LoadConstantNoClobber(r_dest.GetHigh(), val_hi);
587    }
588    return res;
589}
590
591LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
592                                     int displacement, RegStorage r_dest, OpSize size) {
593  LIR *load = NULL;
594  LIR *load2 = NULL;
595  bool is_array = r_index.Valid();
596  bool pair = r_dest.IsPair();
597  bool is64bit = ((size == k64) || (size == kDouble));
598  X86OpCode opcode = kX86Nop;
599  switch (size) {
600    case k64:
601    case kDouble:
602      if (r_dest.IsFloat()) {
603        opcode = is_array ? kX86MovsdRA : kX86MovsdRM;
604      } else {
605        opcode = is_array ? kX86Mov32RA  : kX86Mov32RM;
606      }
607      // TODO: double store is to unaligned address
608      DCHECK_EQ((displacement & 0x3), 0);
609      break;
610    case kWord:
611      if (Gen64Bit()) {
612        opcode = is_array ? kX86Mov64RA  : kX86Mov64RM;
613        CHECK_EQ(is_array, false);
614        CHECK_EQ(r_dest.IsFloat(), false);
615        break;
616      }  // else fall-through to k32 case
617    case k32:
618    case kSingle:
619    case kReference:  // TODO: update for reference decompression on 64-bit targets.
620      opcode = is_array ? kX86Mov32RA : kX86Mov32RM;
621      if (r_dest.IsFloat()) {
622        opcode = is_array ? kX86MovssRA : kX86MovssRM;
623        DCHECK(r_dest.IsFloat());
624      }
625      DCHECK_EQ((displacement & 0x3), 0);
626      break;
627    case kUnsignedHalf:
628      opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM;
629      DCHECK_EQ((displacement & 0x1), 0);
630      break;
631    case kSignedHalf:
632      opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM;
633      DCHECK_EQ((displacement & 0x1), 0);
634      break;
635    case kUnsignedByte:
636      opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM;
637      break;
638    case kSignedByte:
639      opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM;
640      break;
641    default:
642      LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody";
643  }
644
645  if (!is_array) {
646    if (!pair) {
647      load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
648    } else {
649      DCHECK(!r_dest.IsFloat());  // Make sure we're not still using a pair here.
650      if (r_base == r_dest.GetLow()) {
651        load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(),
652                        displacement + HIWORD_OFFSET);
653        load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
654      } else {
655        load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET);
656        load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(),
657                        displacement + HIWORD_OFFSET);
658      }
659    }
660    if (r_base == rs_rX86_SP) {
661      AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
662                              true /* is_load */, is64bit);
663      if (pair) {
664        AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2,
665                                true /* is_load */, is64bit);
666      }
667    }
668  } else {
669    if (!pair) {
670      load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
671                     displacement + LOWORD_OFFSET);
672    } else {
673      DCHECK(!r_dest.IsFloat());  // Make sure we're not still using a pair here.
674      if (r_base == r_dest.GetLow()) {
675        if (r_dest.GetHigh() == r_index) {
676          // We can't use either register for the first load.
677          RegStorage temp = AllocTemp();
678          load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
679                          displacement + HIWORD_OFFSET);
680          load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
681                         displacement + LOWORD_OFFSET);
682          OpRegCopy(r_dest.GetHigh(), temp);
683          FreeTemp(temp);
684        } else {
685          load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
686                          displacement + HIWORD_OFFSET);
687          load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
688                         displacement + LOWORD_OFFSET);
689        }
690      } else {
691        if (r_dest.GetLow() == r_index) {
692          // We can't use either register for the first load.
693          RegStorage temp = AllocTemp();
694          load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale,
695                         displacement + LOWORD_OFFSET);
696          load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
697                          displacement + HIWORD_OFFSET);
698          OpRegCopy(r_dest.GetLow(), temp);
699          FreeTemp(temp);
700        } else {
701          load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale,
702                         displacement + LOWORD_OFFSET);
703          load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale,
704                          displacement + HIWORD_OFFSET);
705        }
706      }
707    }
708  }
709
710  return load;
711}
712
713/* Load value from base + scaled index. */
714LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
715                                 int scale, OpSize size) {
716  return LoadBaseIndexedDisp(r_base, r_index, scale, 0, r_dest, size);
717}
718
719LIR* X86Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest,
720                                      OpSize size) {
721  // LoadBaseDisp() will emit correct insn for atomic load on x86
722  // assuming r_dest is correctly prepared using RegClassForFieldLoadStore().
723  return LoadBaseDisp(r_base, displacement, r_dest, size);
724}
725
726LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
727                              OpSize size) {
728  return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_dest,
729                             size);
730}
731
732LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale,
733                                      int displacement, RegStorage r_src, OpSize size) {
734  LIR *store = NULL;
735  LIR *store2 = NULL;
736  bool is_array = r_index.Valid();
737  bool pair = r_src.IsPair();
738  bool is64bit = (size == k64) || (size == kDouble);
739  X86OpCode opcode = kX86Nop;
740  switch (size) {
741    case k64:
742    case kDouble:
743      if (r_src.IsFloat()) {
744        opcode = is_array ? kX86MovsdAR : kX86MovsdMR;
745      } else {
746        if (Gen64Bit()) {
747          opcode = is_array ? kX86Mov64AR  : kX86Mov64MR;
748        } else {
749          // TODO(64): pair = true;
750          opcode = is_array ? kX86Mov32AR  : kX86Mov32MR;
751        }
752      }
753      // TODO: double store is to unaligned address
754      DCHECK_EQ((displacement & 0x3), 0);
755      break;
756    case kWord:
757      if (Gen64Bit()) {
758        opcode = is_array ? kX86Mov64AR  : kX86Mov64MR;
759        CHECK_EQ(is_array, false);
760        CHECK_EQ(r_src.IsFloat(), false);
761        break;
762      }  // else fall-through to k32 case
763    case k32:
764    case kSingle:
765    case kReference:
766      opcode = is_array ? kX86Mov32AR : kX86Mov32MR;
767      if (r_src.IsFloat()) {
768        opcode = is_array ? kX86MovssAR : kX86MovssMR;
769        DCHECK(r_src.IsSingle());
770      }
771      DCHECK_EQ((displacement & 0x3), 0);
772      break;
773    case kUnsignedHalf:
774    case kSignedHalf:
775      opcode = is_array ? kX86Mov16AR : kX86Mov16MR;
776      DCHECK_EQ((displacement & 0x1), 0);
777      break;
778    case kUnsignedByte:
779    case kSignedByte:
780      opcode = is_array ? kX86Mov8AR : kX86Mov8MR;
781      break;
782    default:
783      LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody";
784  }
785
786  if (!is_array) {
787    if (!pair) {
788      store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg());
789    } else {
790      DCHECK(!r_src.IsFloat());  // Make sure we're not still using a pair here.
791      store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetLowReg());
792      store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src.GetHighReg());
793    }
794    if (r_base == rs_rX86_SP) {
795      AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
796                              false /* is_load */, is64bit);
797      if (pair) {
798        AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2,
799                                false /* is_load */, is64bit);
800      }
801    }
802  } else {
803    if (!pair) {
804      store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
805                      displacement + LOWORD_OFFSET, r_src.GetReg());
806    } else {
807      DCHECK(!r_src.IsFloat());  // Make sure we're not still using a pair here.
808      store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
809                      displacement + LOWORD_OFFSET, r_src.GetLowReg());
810      store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale,
811                       displacement + HIWORD_OFFSET, r_src.GetHighReg());
812    }
813  }
814  return store;
815}
816
817/* store value base base + scaled index. */
818LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src,
819                      int scale, OpSize size) {
820  return StoreBaseIndexedDisp(r_base, r_index, scale, 0, r_src, size);
821}
822
823LIR* X86Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement,
824                                       RegStorage r_src, OpSize size) {
825  // StoreBaseDisp() will emit correct insn for atomic store on x86
826  // assuming r_dest is correctly prepared using RegClassForFieldLoadStore().
827  return StoreBaseDisp(r_base, displacement, r_src, size);
828}
829
830LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement,
831                               RegStorage r_src, OpSize size) {
832  return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, size);
833}
834
835LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
836                                   int offset, int check_value, LIR* target) {
837    NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset,
838            check_value);
839    LIR* branch = OpCondBranch(cond, target);
840    return branch;
841}
842
843void X86Mir2Lir::AnalyzeMIR() {
844  // Assume we don't need a pointer to the base of the code.
845  cu_->NewTimingSplit("X86 MIR Analysis");
846  store_method_addr_ = false;
847
848  // Walk the MIR looking for interesting items.
849  PreOrderDfsIterator iter(mir_graph_);
850  BasicBlock* curr_bb = iter.Next();
851  while (curr_bb != NULL) {
852    AnalyzeBB(curr_bb);
853    curr_bb = iter.Next();
854  }
855
856  // Did we need a pointer to the method code?
857  if (store_method_addr_) {
858    base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, false);
859  } else {
860    base_of_code_ = nullptr;
861  }
862}
863
864void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) {
865  if (bb->block_type == kDead) {
866    // Ignore dead blocks
867    return;
868  }
869
870  for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
871    int opcode = mir->dalvikInsn.opcode;
872    if (MIRGraph::IsPseudoMirOp(opcode)) {
873      AnalyzeExtendedMIR(opcode, bb, mir);
874    } else {
875      AnalyzeMIR(opcode, bb, mir);
876    }
877  }
878}
879
880
881void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) {
882  switch (opcode) {
883    // Instructions referencing doubles.
884    case kMirOpFusedCmplDouble:
885    case kMirOpFusedCmpgDouble:
886      AnalyzeFPInstruction(opcode, bb, mir);
887      break;
888    case kMirOpConstVector:
889      store_method_addr_ = true;
890      break;
891    default:
892      // Ignore the rest.
893      break;
894  }
895}
896
897void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) {
898  // Looking for
899  // - Do we need a pointer to the code (used for packed switches and double lits)?
900
901  switch (opcode) {
902    // Instructions referencing doubles.
903    case Instruction::CMPL_DOUBLE:
904    case Instruction::CMPG_DOUBLE:
905    case Instruction::NEG_DOUBLE:
906    case Instruction::ADD_DOUBLE:
907    case Instruction::SUB_DOUBLE:
908    case Instruction::MUL_DOUBLE:
909    case Instruction::DIV_DOUBLE:
910    case Instruction::REM_DOUBLE:
911    case Instruction::ADD_DOUBLE_2ADDR:
912    case Instruction::SUB_DOUBLE_2ADDR:
913    case Instruction::MUL_DOUBLE_2ADDR:
914    case Instruction::DIV_DOUBLE_2ADDR:
915    case Instruction::REM_DOUBLE_2ADDR:
916      AnalyzeFPInstruction(opcode, bb, mir);
917      break;
918
919    // Packed switches and array fills need a pointer to the base of the method.
920    case Instruction::FILL_ARRAY_DATA:
921    case Instruction::PACKED_SWITCH:
922      store_method_addr_ = true;
923      break;
924    default:
925      // Other instructions are not interesting yet.
926      break;
927  }
928}
929
930void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) {
931  // Look at all the uses, and see if they are double constants.
932  uint64_t attrs = MIRGraph::GetDataFlowAttributes(static_cast<Instruction::Code>(opcode));
933  int next_sreg = 0;
934  if (attrs & DF_UA) {
935    if (attrs & DF_A_WIDE) {
936      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
937      next_sreg += 2;
938    } else {
939      next_sreg++;
940    }
941  }
942  if (attrs & DF_UB) {
943    if (attrs & DF_B_WIDE) {
944      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
945      next_sreg += 2;
946    } else {
947      next_sreg++;
948    }
949  }
950  if (attrs & DF_UC) {
951    if (attrs & DF_C_WIDE) {
952      AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg));
953    }
954  }
955}
956
957void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) {
958  // If this is a double literal, we will want it in the literal pool.
959  if (use.is_const) {
960    store_method_addr_ = true;
961  }
962}
963
964RegLocation X86Mir2Lir::UpdateLocTyped(RegLocation loc, int reg_class) {
965  loc = UpdateLoc(loc);
966  if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) {
967    if (GetRegInfo(loc.reg)->IsTemp()) {
968      Clobber(loc.reg);
969      FreeTemp(loc.reg);
970      loc.reg = RegStorage::InvalidReg();
971      loc.location = kLocDalvikFrame;
972    }
973  }
974  return loc;
975}
976
977RegLocation X86Mir2Lir::UpdateLocWideTyped(RegLocation loc, int reg_class) {
978  loc = UpdateLocWide(loc);
979  if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) {
980    if (GetRegInfo(loc.reg)->IsTemp()) {
981      Clobber(loc.reg);
982      FreeTemp(loc.reg);
983      loc.reg = RegStorage::InvalidReg();
984      loc.location = kLocDalvikFrame;
985    }
986  }
987  return loc;
988}
989
990}  // namespace art
991