utility_x86.cc revision 4c115b85cc48f4dfc8fc2b0484ddfeb29f02d658
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "dex/dataflow_iterator-inl.h" 20#include "x86_lir.h" 21 22namespace art { 23 24/* This file contains codegen for the X86 ISA */ 25 26LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { 27 int opcode; 28 /* must be both DOUBLE or both not DOUBLE */ 29 DCHECK(r_dest.IsFloat() || r_src.IsFloat()); 30 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble()); 31 if (r_dest.IsDouble()) { 32 opcode = kX86MovsdRR; 33 } else { 34 if (r_dest.IsSingle()) { 35 if (r_src.IsSingle()) { 36 opcode = kX86MovssRR; 37 } else { // Fpr <- Gpr 38 opcode = kX86MovdxrRR; 39 } 40 } else { // Gpr <- Fpr 41 DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits(); 42 opcode = kX86MovdrxRR; 43 } 44 } 45 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); 46 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 47 if (r_dest == r_src) { 48 res->flags.is_nop = true; 49 } 50 return res; 51} 52 53bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { 54 return true; 55} 56 57bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { 58 return false; 59} 60 61bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { 62 return true; 63} 64 65bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { 66 return value == 0; 67} 68 69/* 70 * Load a immediate using a shortcut if possible; otherwise 71 * grab from the per-translation literal pool. If target is 72 * a high register, build constant into a low register and copy. 73 * 74 * No additional register clobbering operation performed. Use this version when 75 * 1) r_dest is freshly returned from AllocTemp or 76 * 2) The codegen is under fixed register usage 77 */ 78LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { 79 RegStorage r_dest_save = r_dest; 80 if (r_dest.IsFloat()) { 81 if (value == 0) { 82 return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg()); 83 } 84 r_dest = AllocTemp(); 85 } 86 87 LIR *res; 88 if (value == 0) { 89 res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg()); 90 } else { 91 // Note, there is no byte immediate form of a 32 bit immediate move. 92 // 64-bit immediate is not supported by LIR structure 93 res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value); 94 } 95 96 if (r_dest_save.IsFloat()) { 97 NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg()); 98 FreeTemp(r_dest); 99 } 100 101 return res; 102} 103 104LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { 105 LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/); 106 res->target = target; 107 return res; 108} 109 110LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 111 LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, 112 X86ConditionEncoding(cc)); 113 branch->target = target; 114 return branch; 115} 116 117LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { 118 X86OpCode opcode = kX86Bkpt; 119 switch (op) { 120 case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; 121 case kOpNot: opcode = r_dest_src.Is64Bit() ? kX86Not64R : kX86Not32R; break; 122 case kOpRev: opcode = kX86Bswap32R; break; 123 case kOpBlx: opcode = kX86CallR; break; 124 default: 125 LOG(FATAL) << "Bad case in OpReg " << op; 126 } 127 return NewLIR1(opcode, r_dest_src.GetReg()); 128} 129 130LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { 131 X86OpCode opcode = kX86Bkpt; 132 bool byte_imm = IS_SIMM8(value); 133 DCHECK(!r_dest_src1.IsFloat()); 134 if (r_dest_src1.Is64Bit()) { 135 switch (op) { 136 case kOpAdd: opcode = byte_imm ? kX86Add64RI8 : kX86Add64RI; break; 137 case kOpSub: opcode = byte_imm ? kX86Sub64RI8 : kX86Sub64RI; break; 138 case kOpLsl: opcode = kX86Sal64RI; break; 139 case kOpLsr: opcode = kX86Shr64RI; break; 140 case kOpAsr: opcode = kX86Sar64RI; break; 141 case kOpCmp: opcode = byte_imm ? kX86Cmp64RI8 : kX86Cmp64RI; break; 142 default: 143 LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op; 144 } 145 } else { 146 switch (op) { 147 case kOpLsl: opcode = kX86Sal32RI; break; 148 case kOpLsr: opcode = kX86Shr32RI; break; 149 case kOpAsr: opcode = kX86Sar32RI; break; 150 case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; 151 case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; 152 case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; 153 // case kOpSbb: opcode = kX86Sbb32RI; break; 154 case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; 155 case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; 156 case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; 157 case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; 158 case kOpMov: 159 /* 160 * Moving the constant zero into register can be specialized as an xor of the register. 161 * However, that sets eflags while the move does not. For that reason here, always do 162 * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead. 163 */ 164 opcode = kX86Mov32RI; 165 break; 166 case kOpMul: 167 opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; 168 return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value); 169 case kOp2Byte: 170 opcode = kX86Mov32RI; 171 value = static_cast<int8_t>(value); 172 break; 173 case kOp2Short: 174 opcode = kX86Mov32RI; 175 value = static_cast<int16_t>(value); 176 break; 177 case kOp2Char: 178 opcode = kX86Mov32RI; 179 value = static_cast<uint16_t>(value); 180 break; 181 case kOpNeg: 182 opcode = kX86Mov32RI; 183 value = -value; 184 break; 185 default: 186 LOG(FATAL) << "Bad case in OpRegImm " << op; 187 } 188 } 189 return NewLIR2(opcode, r_dest_src1.GetReg(), value); 190} 191 192LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { 193 bool is64Bit = r_dest_src1.Is64Bit(); 194 X86OpCode opcode = kX86Nop; 195 bool src2_must_be_cx = false; 196 switch (op) { 197 // X86 unary opcodes 198 case kOpMvn: 199 OpRegCopy(r_dest_src1, r_src2); 200 return OpReg(kOpNot, r_dest_src1); 201 case kOpNeg: 202 OpRegCopy(r_dest_src1, r_src2); 203 return OpReg(kOpNeg, r_dest_src1); 204 case kOpRev: 205 OpRegCopy(r_dest_src1, r_src2); 206 return OpReg(kOpRev, r_dest_src1); 207 case kOpRevsh: 208 OpRegCopy(r_dest_src1, r_src2); 209 OpReg(kOpRev, r_dest_src1); 210 return OpRegImm(kOpAsr, r_dest_src1, 16); 211 // X86 binary opcodes 212 case kOpSub: opcode = is64Bit ? kX86Sub64RR : kX86Sub32RR; break; 213 case kOpSbc: opcode = is64Bit ? kX86Sbb64RR : kX86Sbb32RR; break; 214 case kOpLsl: opcode = is64Bit ? kX86Sal64RC : kX86Sal32RC; src2_must_be_cx = true; break; 215 case kOpLsr: opcode = is64Bit ? kX86Shr64RC : kX86Shr32RC; src2_must_be_cx = true; break; 216 case kOpAsr: opcode = is64Bit ? kX86Sar64RC : kX86Sar32RC; src2_must_be_cx = true; break; 217 case kOpMov: opcode = is64Bit ? kX86Mov64RR : kX86Mov32RR; break; 218 case kOpCmp: opcode = is64Bit ? kX86Cmp64RR : kX86Cmp32RR; break; 219 case kOpAdd: opcode = is64Bit ? kX86Add64RR : kX86Add32RR; break; 220 case kOpAdc: opcode = is64Bit ? kX86Adc64RR : kX86Adc32RR; break; 221 case kOpAnd: opcode = is64Bit ? kX86And64RR : kX86And32RR; break; 222 case kOpOr: opcode = is64Bit ? kX86Or64RR : kX86Or32RR; break; 223 case kOpXor: opcode = is64Bit ? kX86Xor64RR : kX86Xor32RR; break; 224 case kOp2Byte: 225 // TODO: there are several instances of this check. A utility function perhaps? 226 // TODO: Similar to Arm's reg < 8 check. Perhaps add attribute checks to RegStorage? 227 // Use shifts instead of a byte operand if the source can't be byte accessed. 228 if (r_src2.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 229 NewLIR2(is64Bit ? kX86Mov64RR : kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg()); 230 NewLIR2(is64Bit ? kX86Sal64RI : kX86Sal32RI, r_dest_src1.GetReg(), is64Bit ? 56 : 24); 231 return NewLIR2(is64Bit ? kX86Sar64RI : kX86Sar32RI, r_dest_src1.GetReg(), 232 is64Bit ? 56 : 24); 233 } else { 234 opcode = is64Bit ? kX86Bkpt : kX86Movsx8RR; 235 } 236 break; 237 case kOp2Short: opcode = is64Bit ? kX86Bkpt : kX86Movsx16RR; break; 238 case kOp2Char: opcode = is64Bit ? kX86Bkpt : kX86Movzx16RR; break; 239 case kOpMul: opcode = is64Bit ? kX86Bkpt : kX86Imul32RR; break; 240 default: 241 LOG(FATAL) << "Bad case in OpRegReg " << op; 242 break; 243 } 244 CHECK(!src2_must_be_cx || r_src2.GetReg() == rs_rCX.GetReg()); 245 return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg()); 246} 247 248LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 249 DCHECK(!r_base.IsFloat()); 250 X86OpCode opcode = kX86Nop; 251 int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 252 switch (move_type) { 253 case kMov8GP: 254 CHECK(!r_dest.IsFloat()); 255 opcode = kX86Mov8RM; 256 break; 257 case kMov16GP: 258 CHECK(!r_dest.IsFloat()); 259 opcode = kX86Mov16RM; 260 break; 261 case kMov32GP: 262 CHECK(!r_dest.IsFloat()); 263 opcode = kX86Mov32RM; 264 break; 265 case kMov32FP: 266 CHECK(r_dest.IsFloat()); 267 opcode = kX86MovssRM; 268 break; 269 case kMov64FP: 270 CHECK(r_dest.IsFloat()); 271 opcode = kX86MovsdRM; 272 break; 273 case kMovU128FP: 274 CHECK(r_dest.IsFloat()); 275 opcode = kX86MovupsRM; 276 break; 277 case kMovA128FP: 278 CHECK(r_dest.IsFloat()); 279 opcode = kX86MovapsRM; 280 break; 281 case kMovLo128FP: 282 CHECK(r_dest.IsFloat()); 283 opcode = kX86MovlpsRM; 284 break; 285 case kMovHi128FP: 286 CHECK(r_dest.IsFloat()); 287 opcode = kX86MovhpsRM; 288 break; 289 case kMov64GP: 290 case kMovLo64FP: 291 case kMovHi64FP: 292 default: 293 LOG(FATAL) << "Bad case in OpMovRegMem"; 294 break; 295 } 296 297 return NewLIR3(opcode, dest, r_base.GetReg(), offset); 298} 299 300LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 301 DCHECK(!r_base.IsFloat()); 302 int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg(); 303 304 X86OpCode opcode = kX86Nop; 305 switch (move_type) { 306 case kMov8GP: 307 CHECK(!r_src.IsFloat()); 308 opcode = kX86Mov8MR; 309 break; 310 case kMov16GP: 311 CHECK(!r_src.IsFloat()); 312 opcode = kX86Mov16MR; 313 break; 314 case kMov32GP: 315 CHECK(!r_src.IsFloat()); 316 opcode = kX86Mov32MR; 317 break; 318 case kMov32FP: 319 CHECK(r_src.IsFloat()); 320 opcode = kX86MovssMR; 321 break; 322 case kMov64FP: 323 CHECK(r_src.IsFloat()); 324 opcode = kX86MovsdMR; 325 break; 326 case kMovU128FP: 327 CHECK(r_src.IsFloat()); 328 opcode = kX86MovupsMR; 329 break; 330 case kMovA128FP: 331 CHECK(r_src.IsFloat()); 332 opcode = kX86MovapsMR; 333 break; 334 case kMovLo128FP: 335 CHECK(r_src.IsFloat()); 336 opcode = kX86MovlpsMR; 337 break; 338 case kMovHi128FP: 339 CHECK(r_src.IsFloat()); 340 opcode = kX86MovhpsMR; 341 break; 342 case kMov64GP: 343 case kMovLo64FP: 344 case kMovHi64FP: 345 default: 346 LOG(FATAL) << "Bad case in OpMovMemReg"; 347 break; 348 } 349 350 return NewLIR3(opcode, r_base.GetReg(), offset, src); 351} 352 353LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { 354 // The only conditional reg to reg operation supported is Cmov 355 DCHECK_EQ(op, kOpCmov); 356 return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc)); 357} 358 359LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { 360 bool is64Bit = r_dest.Is64Bit(); 361 X86OpCode opcode = kX86Nop; 362 switch (op) { 363 // X86 binary opcodes 364 case kOpSub: opcode = is64Bit ? kX86Sub64RM : kX86Sub32RM; break; 365 case kOpMov: opcode = is64Bit ? kX86Mov64RM : kX86Mov32RM; break; 366 case kOpCmp: opcode = is64Bit ? kX86Cmp64RM : kX86Cmp32RM; break; 367 case kOpAdd: opcode = is64Bit ? kX86Add64RM : kX86Add32RM; break; 368 case kOpAnd: opcode = is64Bit ? kX86And64RM : kX86And32RM; break; 369 case kOpOr: opcode = is64Bit ? kX86Or64RM : kX86Or32RM; break; 370 case kOpXor: opcode = is64Bit ? kX86Xor64RM : kX86Xor32RM; break; 371 case kOp2Byte: opcode = kX86Movsx8RM; break; 372 case kOp2Short: opcode = kX86Movsx16RM; break; 373 case kOp2Char: opcode = kX86Movzx16RM; break; 374 case kOpMul: 375 default: 376 LOG(FATAL) << "Bad case in OpRegMem " << op; 377 break; 378 } 379 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset); 380 if (mem_ref_type_ == ResourceMask::kDalvikReg) { 381 DCHECK(r_base == rs_rX86_SP); 382 AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); 383 } 384 return l; 385} 386 387LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { 388 DCHECK_NE(rl_dest.location, kLocPhysReg); 389 int displacement = SRegOffset(rl_dest.s_reg_low); 390 bool is64Bit = rl_dest.wide != 0; 391 X86OpCode opcode = kX86Nop; 392 switch (op) { 393 case kOpSub: opcode = is64Bit ? kX86Sub64MR : kX86Sub32MR; break; 394 case kOpMov: opcode = is64Bit ? kX86Mov64MR : kX86Mov32MR; break; 395 case kOpCmp: opcode = is64Bit ? kX86Cmp64MR : kX86Cmp32MR; break; 396 case kOpAdd: opcode = is64Bit ? kX86Add64MR : kX86Add32MR; break; 397 case kOpAnd: opcode = is64Bit ? kX86And64MR : kX86And32MR; break; 398 case kOpOr: opcode = is64Bit ? kX86Or64MR : kX86Or32MR; break; 399 case kOpXor: opcode = is64Bit ? kX86Xor64MR : kX86Xor32MR; break; 400 case kOpLsl: opcode = is64Bit ? kX86Sal64MC : kX86Sal32MC; break; 401 case kOpLsr: opcode = is64Bit ? kX86Shr64MC : kX86Shr32MC; break; 402 case kOpAsr: opcode = is64Bit ? kX86Sar64MC : kX86Sar32MC; break; 403 default: 404 LOG(FATAL) << "Bad case in OpMemReg " << op; 405 break; 406 } 407 LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value); 408 if (mem_ref_type_ == ResourceMask::kDalvikReg) { 409 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 410 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); 411 } 412 return l; 413} 414 415LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) { 416 DCHECK_NE(rl_value.location, kLocPhysReg); 417 bool is64Bit = r_dest.Is64Bit(); 418 int displacement = SRegOffset(rl_value.s_reg_low); 419 X86OpCode opcode = kX86Nop; 420 switch (op) { 421 case kOpSub: opcode = is64Bit ? kX86Sub64RM : kX86Sub32RM; break; 422 case kOpMov: opcode = is64Bit ? kX86Mov64RM : kX86Mov32RM; break; 423 case kOpCmp: opcode = is64Bit ? kX86Cmp64RM : kX86Cmp32RM; break; 424 case kOpAdd: opcode = is64Bit ? kX86Add64RM : kX86Add32RM; break; 425 case kOpAnd: opcode = is64Bit ? kX86And64RM : kX86And32RM; break; 426 case kOpOr: opcode = is64Bit ? kX86Or64RM : kX86Or32RM; break; 427 case kOpXor: opcode = is64Bit ? kX86Xor64RM : kX86Xor32RM; break; 428 case kOpMul: opcode = is64Bit ? kX86Bkpt : kX86Imul32RM; break; 429 default: 430 LOG(FATAL) << "Bad case in OpRegMem " << op; 431 break; 432 } 433 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement); 434 if (mem_ref_type_ == ResourceMask::kDalvikReg) { 435 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); 436 } 437 return l; 438} 439 440LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 441 RegStorage r_src2) { 442 bool is64Bit = r_dest.Is64Bit(); 443 if (r_dest != r_src1 && r_dest != r_src2) { 444 if (op == kOpAdd) { // lea special case, except can't encode rbp as base 445 if (r_src1 == r_src2) { 446 OpRegCopy(r_dest, r_src1); 447 return OpRegImm(kOpLsl, r_dest, 1); 448 } else if (r_src1 != rs_rBP) { 449 return NewLIR5(is64Bit ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), 450 r_src1.GetReg() /* base */, r_src2.GetReg() /* index */, 451 0 /* scale */, 0 /* disp */); 452 } else { 453 return NewLIR5(is64Bit ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), 454 r_src2.GetReg() /* base */, r_src1.GetReg() /* index */, 455 0 /* scale */, 0 /* disp */); 456 } 457 } else { 458 OpRegCopy(r_dest, r_src1); 459 return OpRegReg(op, r_dest, r_src2); 460 } 461 } else if (r_dest == r_src1) { 462 return OpRegReg(op, r_dest, r_src2); 463 } else { // r_dest == r_src2 464 switch (op) { 465 case kOpSub: // non-commutative 466 OpReg(kOpNeg, r_dest); 467 op = kOpAdd; 468 break; 469 case kOpSbc: 470 case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { 471 RegStorage t_reg = AllocTemp(); 472 OpRegCopy(t_reg, r_src1); 473 OpRegReg(op, t_reg, r_src2); 474 LIR* res = OpRegCopyNoInsert(r_dest, t_reg); 475 AppendLIR(res); 476 FreeTemp(t_reg); 477 return res; 478 } 479 case kOpAdd: // commutative 480 case kOpOr: 481 case kOpAdc: 482 case kOpAnd: 483 case kOpXor: 484 break; 485 default: 486 LOG(FATAL) << "Bad case in OpRegRegReg " << op; 487 } 488 return OpRegReg(op, r_dest, r_src1); 489 } 490} 491 492LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) { 493 if (op == kOpMul && !Gen64Bit()) { 494 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; 495 return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value); 496 } else if (op == kOpAnd && !Gen64Bit()) { 497 if (value == 0xFF && r_src.Low4()) { 498 return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg()); 499 } else if (value == 0xFFFF) { 500 return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg()); 501 } 502 } 503 if (r_dest != r_src) { 504 if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case 505 // TODO: fix bug in LEA encoding when disp == 0 506 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */, 507 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); 508 } else if (op == kOpAdd) { // lea add special case 509 return NewLIR5(r_dest.Is64Bit() ? kX86Lea64RA : kX86Lea32RA, r_dest.GetReg(), 510 r_src.GetReg() /* base */, rs_rX86_SP.GetReg()/*r4sib_no_index*/ /* index */, 511 0 /* scale */, value /* disp */); 512 } 513 OpRegCopy(r_dest, r_src); 514 } 515 return OpRegImm(op, r_dest, value); 516} 517 518LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { 519 DCHECK_EQ(kX86, cu_->instruction_set); 520 X86OpCode opcode = kX86Bkpt; 521 switch (op) { 522 case kOpBlx: opcode = kX86CallT; break; 523 case kOpBx: opcode = kX86JmpT; break; 524 default: 525 LOG(FATAL) << "Bad opcode: " << op; 526 break; 527 } 528 return NewLIR1(opcode, thread_offset.Int32Value()); 529} 530 531LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) { 532 DCHECK_EQ(kX86_64, cu_->instruction_set); 533 X86OpCode opcode = kX86Bkpt; 534 switch (op) { 535 case kOpBlx: opcode = kX86CallT; break; 536 case kOpBx: opcode = kX86JmpT; break; 537 default: 538 LOG(FATAL) << "Bad opcode: " << op; 539 break; 540 } 541 return NewLIR1(opcode, thread_offset.Int32Value()); 542} 543 544LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { 545 X86OpCode opcode = kX86Bkpt; 546 switch (op) { 547 case kOpBlx: opcode = kX86CallM; break; 548 default: 549 LOG(FATAL) << "Bad opcode: " << op; 550 break; 551 } 552 return NewLIR2(opcode, r_base.GetReg(), disp); 553} 554 555LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { 556 int32_t val_lo = Low32Bits(value); 557 int32_t val_hi = High32Bits(value); 558 int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 559 LIR *res; 560 bool is_fp = r_dest.IsFloat(); 561 // TODO: clean this up once we fully recognize 64-bit storage containers. 562 if (is_fp) { 563 if (value == 0) { 564 return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 565 } else if (base_of_code_ != nullptr) { 566 // We will load the value from the literal area. 567 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 568 if (data_target == NULL) { 569 data_target = AddWideData(&literal_list_, val_lo, val_hi); 570 } 571 572 // Address the start of the method 573 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 574 if (rl_method.wide) { 575 rl_method = LoadValueWide(rl_method, kCoreReg); 576 } else { 577 rl_method = LoadValue(rl_method, kCoreReg); 578 } 579 580 // Load the proper value from the literal area. 581 // We don't know the proper offset for the value, so pick one that will force 582 // 4 byte offset. We will fix this up in the assembler later to have the right 583 // value. 584 ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); 585 res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::FloatSolo64(low_reg_val), 586 kDouble); 587 res->target = data_target; 588 res->flags.fixup = kFixupLoad; 589 store_method_addr_used_ = true; 590 } else { 591 if (val_lo == 0) { 592 res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 593 } else { 594 res = LoadConstantNoClobber(RegStorage::FloatSolo32(low_reg_val), val_lo); 595 } 596 if (val_hi != 0) { 597 RegStorage r_dest_hi = AllocTempDouble(); 598 LoadConstantNoClobber(r_dest_hi, val_hi); 599 NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetReg()); 600 FreeTemp(r_dest_hi); 601 } 602 } 603 } else { 604 if (r_dest.IsPair()) { 605 res = LoadConstantNoClobber(r_dest.GetLow(), val_lo); 606 LoadConstantNoClobber(r_dest.GetHigh(), val_hi); 607 } else { 608 // TODO(64) make int64_t value parameter of LoadConstantNoClobber 609 if (val_lo < 0) { 610 val_hi += 1; 611 } 612 res = LoadConstantNoClobber(RegStorage::Solo32(r_dest.GetReg()), val_hi); 613 NewLIR2(kX86Sal64RI, r_dest.GetReg(), 32); 614 if (val_lo != 0) { 615 NewLIR2(kX86Add64RI, r_dest.GetReg(), val_lo); 616 } 617 } 618 } 619 return res; 620} 621 622LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 623 int displacement, RegStorage r_dest, OpSize size) { 624 LIR *load = NULL; 625 LIR *load2 = NULL; 626 bool is_array = r_index.Valid(); 627 bool pair = r_dest.IsPair(); 628 bool is64bit = ((size == k64) || (size == kDouble)); 629 X86OpCode opcode = kX86Nop; 630 switch (size) { 631 case k64: 632 case kDouble: 633 if (r_dest.IsFloat()) { 634 opcode = is_array ? kX86MovsdRA : kX86MovsdRM; 635 } else if (!pair) { 636 opcode = is_array ? kX86Mov64RA : kX86Mov64RM; 637 } else { 638 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 639 } 640 // TODO: double store is to unaligned address 641 DCHECK_EQ((displacement & 0x3), 0); 642 break; 643 case kWord: 644 if (Gen64Bit()) { 645 opcode = is_array ? kX86Mov64RA : kX86Mov64RM; 646 CHECK_EQ(is_array, false); 647 CHECK_EQ(r_dest.IsFloat(), false); 648 break; 649 } // else fall-through to k32 case 650 case k32: 651 case kSingle: 652 case kReference: // TODO: update for reference decompression on 64-bit targets. 653 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 654 if (r_dest.IsFloat()) { 655 opcode = is_array ? kX86MovssRA : kX86MovssRM; 656 DCHECK(r_dest.IsFloat()); 657 } 658 DCHECK_EQ((displacement & 0x3), 0); 659 break; 660 case kUnsignedHalf: 661 opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; 662 DCHECK_EQ((displacement & 0x1), 0); 663 break; 664 case kSignedHalf: 665 opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; 666 DCHECK_EQ((displacement & 0x1), 0); 667 break; 668 case kUnsignedByte: 669 opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; 670 break; 671 case kSignedByte: 672 opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; 673 break; 674 default: 675 LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; 676 } 677 678 if (!is_array) { 679 if (!pair) { 680 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 681 } else { 682 DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. 683 if (r_base == r_dest.GetLow()) { 684 load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), 685 displacement + HIWORD_OFFSET); 686 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 687 } else { 688 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 689 load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), 690 displacement + HIWORD_OFFSET); 691 } 692 } 693 if (mem_ref_type_ == ResourceMask::kDalvikReg) { 694 DCHECK(r_base == rs_rX86_SP); 695 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 696 true /* is_load */, is64bit); 697 if (pair) { 698 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, 699 true /* is_load */, is64bit); 700 } 701 } 702 } else { 703 if (!pair) { 704 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 705 displacement + LOWORD_OFFSET); 706 } else { 707 DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. 708 if (r_base == r_dest.GetLow()) { 709 if (r_dest.GetHigh() == r_index) { 710 // We can't use either register for the first load. 711 RegStorage temp = AllocTemp(); 712 load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 713 displacement + HIWORD_OFFSET); 714 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 715 displacement + LOWORD_OFFSET); 716 OpRegCopy(r_dest.GetHigh(), temp); 717 FreeTemp(temp); 718 } else { 719 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 720 displacement + HIWORD_OFFSET); 721 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 722 displacement + LOWORD_OFFSET); 723 } 724 } else { 725 if (r_dest.GetLow() == r_index) { 726 // We can't use either register for the first load. 727 RegStorage temp = AllocTemp(); 728 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 729 displacement + LOWORD_OFFSET); 730 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 731 displacement + HIWORD_OFFSET); 732 OpRegCopy(r_dest.GetLow(), temp); 733 FreeTemp(temp); 734 } else { 735 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 736 displacement + LOWORD_OFFSET); 737 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 738 displacement + HIWORD_OFFSET); 739 } 740 } 741 } 742 } 743 744 return load; 745} 746 747/* Load value from base + scaled index. */ 748LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 749 int scale, OpSize size) { 750 return LoadBaseIndexedDisp(r_base, r_index, scale, 0, r_dest, size); 751} 752 753LIR* X86Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 754 OpSize size) { 755 // LoadBaseDisp() will emit correct insn for atomic load on x86 756 // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). 757 return LoadBaseDisp(r_base, displacement, r_dest, size); 758} 759 760LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 761 OpSize size) { 762 return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_dest, 763 size); 764} 765 766LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 767 int displacement, RegStorage r_src, OpSize size) { 768 LIR *store = NULL; 769 LIR *store2 = NULL; 770 bool is_array = r_index.Valid(); 771 bool pair = r_src.IsPair(); 772 bool is64bit = (size == k64) || (size == kDouble); 773 X86OpCode opcode = kX86Nop; 774 switch (size) { 775 case k64: 776 case kDouble: 777 if (r_src.IsFloat()) { 778 opcode = is_array ? kX86MovsdAR : kX86MovsdMR; 779 } else if (!pair) { 780 opcode = is_array ? kX86Mov64AR : kX86Mov64MR; 781 } else { 782 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 783 } 784 // TODO: double store is to unaligned address 785 DCHECK_EQ((displacement & 0x3), 0); 786 break; 787 case kWord: 788 if (Gen64Bit()) { 789 opcode = is_array ? kX86Mov64AR : kX86Mov64MR; 790 CHECK_EQ(is_array, false); 791 CHECK_EQ(r_src.IsFloat(), false); 792 break; 793 } // else fall-through to k32 case 794 case k32: 795 case kSingle: 796 case kReference: 797 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 798 if (r_src.IsFloat()) { 799 opcode = is_array ? kX86MovssAR : kX86MovssMR; 800 DCHECK(r_src.IsSingle()); 801 } 802 DCHECK_EQ((displacement & 0x3), 0); 803 break; 804 case kUnsignedHalf: 805 case kSignedHalf: 806 opcode = is_array ? kX86Mov16AR : kX86Mov16MR; 807 DCHECK_EQ((displacement & 0x1), 0); 808 break; 809 case kUnsignedByte: 810 case kSignedByte: 811 opcode = is_array ? kX86Mov8AR : kX86Mov8MR; 812 break; 813 default: 814 LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody"; 815 } 816 817 if (!is_array) { 818 if (!pair) { 819 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); 820 } else { 821 DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. 822 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetLowReg()); 823 store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src.GetHighReg()); 824 } 825 if (mem_ref_type_ == ResourceMask::kDalvikReg) { 826 DCHECK(r_base == rs_rX86_SP); 827 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 828 false /* is_load */, is64bit); 829 if (pair) { 830 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, 831 false /* is_load */, is64bit); 832 } 833 } 834 } else { 835 if (!pair) { 836 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 837 displacement + LOWORD_OFFSET, r_src.GetReg()); 838 } else { 839 DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. 840 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 841 displacement + LOWORD_OFFSET, r_src.GetLowReg()); 842 store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 843 displacement + HIWORD_OFFSET, r_src.GetHighReg()); 844 } 845 } 846 return store; 847} 848 849/* store value base base + scaled index. */ 850LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 851 int scale, OpSize size) { 852 return StoreBaseIndexedDisp(r_base, r_index, scale, 0, r_src, size); 853} 854 855LIR* X86Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement, 856 RegStorage r_src, OpSize size) { 857 // StoreBaseDisp() will emit correct insn for atomic store on x86 858 // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). 859 return StoreBaseDisp(r_base, displacement, r_src, size); 860} 861 862LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, 863 RegStorage r_src, OpSize size) { 864 return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, size); 865} 866 867LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 868 int offset, int check_value, LIR* target) { 869 NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset, 870 check_value); 871 LIR* branch = OpCondBranch(cond, target); 872 return branch; 873} 874 875void X86Mir2Lir::AnalyzeMIR() { 876 // Assume we don't need a pointer to the base of the code. 877 cu_->NewTimingSplit("X86 MIR Analysis"); 878 store_method_addr_ = false; 879 880 // Walk the MIR looking for interesting items. 881 PreOrderDfsIterator iter(mir_graph_); 882 BasicBlock* curr_bb = iter.Next(); 883 while (curr_bb != NULL) { 884 AnalyzeBB(curr_bb); 885 curr_bb = iter.Next(); 886 } 887 888 // Did we need a pointer to the method code? 889 if (store_method_addr_) { 890 base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, Gen64Bit() == true); 891 } else { 892 base_of_code_ = nullptr; 893 } 894} 895 896void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) { 897 if (bb->block_type == kDead) { 898 // Ignore dead blocks 899 return; 900 } 901 902 for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 903 int opcode = mir->dalvikInsn.opcode; 904 if (MIRGraph::IsPseudoMirOp(opcode)) { 905 AnalyzeExtendedMIR(opcode, bb, mir); 906 } else { 907 AnalyzeMIR(opcode, bb, mir); 908 } 909 } 910} 911 912 913void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { 914 switch (opcode) { 915 // Instructions referencing doubles. 916 case kMirOpFusedCmplDouble: 917 case kMirOpFusedCmpgDouble: 918 AnalyzeFPInstruction(opcode, bb, mir); 919 break; 920 case kMirOpConstVector: 921 store_method_addr_ = true; 922 break; 923 default: 924 // Ignore the rest. 925 break; 926 } 927} 928 929void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { 930 // Looking for 931 // - Do we need a pointer to the code (used for packed switches and double lits)? 932 933 switch (opcode) { 934 // Instructions referencing doubles. 935 case Instruction::CMPL_DOUBLE: 936 case Instruction::CMPG_DOUBLE: 937 case Instruction::NEG_DOUBLE: 938 case Instruction::ADD_DOUBLE: 939 case Instruction::SUB_DOUBLE: 940 case Instruction::MUL_DOUBLE: 941 case Instruction::DIV_DOUBLE: 942 case Instruction::REM_DOUBLE: 943 case Instruction::ADD_DOUBLE_2ADDR: 944 case Instruction::SUB_DOUBLE_2ADDR: 945 case Instruction::MUL_DOUBLE_2ADDR: 946 case Instruction::DIV_DOUBLE_2ADDR: 947 case Instruction::REM_DOUBLE_2ADDR: 948 AnalyzeFPInstruction(opcode, bb, mir); 949 break; 950 951 // Packed switches and array fills need a pointer to the base of the method. 952 case Instruction::FILL_ARRAY_DATA: 953 case Instruction::PACKED_SWITCH: 954 store_method_addr_ = true; 955 break; 956 default: 957 // Other instructions are not interesting yet. 958 break; 959 } 960} 961 962void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) { 963 // Look at all the uses, and see if they are double constants. 964 uint64_t attrs = MIRGraph::GetDataFlowAttributes(static_cast<Instruction::Code>(opcode)); 965 int next_sreg = 0; 966 if (attrs & DF_UA) { 967 if (attrs & DF_A_WIDE) { 968 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 969 next_sreg += 2; 970 } else { 971 next_sreg++; 972 } 973 } 974 if (attrs & DF_UB) { 975 if (attrs & DF_B_WIDE) { 976 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 977 next_sreg += 2; 978 } else { 979 next_sreg++; 980 } 981 } 982 if (attrs & DF_UC) { 983 if (attrs & DF_C_WIDE) { 984 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 985 } 986 } 987} 988 989void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) { 990 // If this is a double literal, we will want it in the literal pool. 991 if (use.is_const) { 992 store_method_addr_ = true; 993 } 994} 995 996RegLocation X86Mir2Lir::UpdateLocTyped(RegLocation loc, int reg_class) { 997 loc = UpdateLoc(loc); 998 if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { 999 if (GetRegInfo(loc.reg)->IsTemp()) { 1000 Clobber(loc.reg); 1001 FreeTemp(loc.reg); 1002 loc.reg = RegStorage::InvalidReg(); 1003 loc.location = kLocDalvikFrame; 1004 } 1005 } 1006 DCHECK(CheckCorePoolSanity()); 1007 return loc; 1008} 1009 1010RegLocation X86Mir2Lir::UpdateLocWideTyped(RegLocation loc, int reg_class) { 1011 loc = UpdateLocWide(loc); 1012 if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { 1013 if (GetRegInfo(loc.reg)->IsTemp()) { 1014 Clobber(loc.reg); 1015 FreeTemp(loc.reg); 1016 loc.reg = RegStorage::InvalidReg(); 1017 loc.location = kLocDalvikFrame; 1018 } 1019 } 1020 DCHECK(CheckCorePoolSanity()); 1021 return loc; 1022} 1023} // namespace art 1024