utility_x86.cc revision d65c51a556e6649db4e18bd083c8fec37607a442
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "dex/dataflow_iterator-inl.h" 20#include "x86_lir.h" 21 22namespace art { 23 24/* This file contains codegen for the X86 ISA */ 25 26LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { 27 int opcode; 28 /* must be both DOUBLE or both not DOUBLE */ 29 DCHECK(r_dest.IsFloat() || r_src.IsFloat()); 30 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble()); 31 if (r_dest.IsDouble()) { 32 opcode = kX86MovsdRR; 33 } else { 34 if (r_dest.IsSingle()) { 35 if (r_src.IsSingle()) { 36 opcode = kX86MovssRR; 37 } else { // Fpr <- Gpr 38 opcode = kX86MovdxrRR; 39 } 40 } else { // Gpr <- Fpr 41 DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits(); 42 opcode = kX86MovdrxRR; 43 } 44 } 45 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); 46 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 47 if (r_dest == r_src) { 48 res->flags.is_nop = true; 49 } 50 return res; 51} 52 53bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { 54 return true; 55} 56 57bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { 58 return false; 59} 60 61bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { 62 return true; 63} 64 65bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { 66 return value == 0; 67} 68 69/* 70 * Load a immediate using a shortcut if possible; otherwise 71 * grab from the per-translation literal pool. If target is 72 * a high register, build constant into a low register and copy. 73 * 74 * No additional register clobbering operation performed. Use this version when 75 * 1) r_dest is freshly returned from AllocTemp or 76 * 2) The codegen is under fixed register usage 77 */ 78LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { 79 RegStorage r_dest_save = r_dest; 80 if (r_dest.IsFloat()) { 81 if (value == 0) { 82 return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg()); 83 } 84 r_dest = AllocTemp(); 85 } 86 87 LIR *res; 88 if (value == 0) { 89 res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg()); 90 } else { 91 // Note, there is no byte immediate form of a 32 bit immediate move. 92 res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value); 93 } 94 95 if (r_dest_save.IsFloat()) { 96 NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg()); 97 FreeTemp(r_dest); 98 } 99 100 return res; 101} 102 103LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { 104 LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/); 105 res->target = target; 106 return res; 107} 108 109LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 110 LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, 111 X86ConditionEncoding(cc)); 112 branch->target = target; 113 return branch; 114} 115 116LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { 117 X86OpCode opcode = kX86Bkpt; 118 switch (op) { 119 case kOpNeg: opcode = kX86Neg32R; break; 120 case kOpNot: opcode = kX86Not32R; break; 121 case kOpRev: opcode = kX86Bswap32R; break; 122 case kOpBlx: opcode = kX86CallR; break; 123 default: 124 LOG(FATAL) << "Bad case in OpReg " << op; 125 } 126 return NewLIR1(opcode, r_dest_src.GetReg()); 127} 128 129LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { 130 X86OpCode opcode = kX86Bkpt; 131 bool byte_imm = IS_SIMM8(value); 132 DCHECK(!r_dest_src1.IsFloat()); 133 if (r_dest_src1.Is64Bit()) { 134 switch (op) { 135 case kOpAdd: opcode = byte_imm ? kX86Add64RI8 : kX86Add64RI; break; 136 case kOpSub: opcode = byte_imm ? kX86Sub64RI8 : kX86Sub64RI; break; 137 default: 138 LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op; 139 } 140 } else { 141 switch (op) { 142 case kOpLsl: opcode = kX86Sal32RI; break; 143 case kOpLsr: opcode = kX86Shr32RI; break; 144 case kOpAsr: opcode = kX86Sar32RI; break; 145 case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; 146 case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; 147 case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; 148 // case kOpSbb: opcode = kX86Sbb32RI; break; 149 case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; 150 case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; 151 case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; 152 case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; 153 case kOpMov: 154 /* 155 * Moving the constant zero into register can be specialized as an xor of the register. 156 * However, that sets eflags while the move does not. For that reason here, always do 157 * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead. 158 */ 159 opcode = kX86Mov32RI; 160 break; 161 case kOpMul: 162 opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; 163 return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value); 164 default: 165 LOG(FATAL) << "Bad case in OpRegImm " << op; 166 } 167 } 168 CHECK(!r_dest_src1.Is64Bit() || X86Mir2Lir::EncodingMap[opcode].kind == kReg64Imm) << "OpRegImm(" << op << ")"; 169 return NewLIR2(opcode, r_dest_src1.GetReg(), value); 170} 171 172LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { 173 X86OpCode opcode = kX86Nop; 174 bool src2_must_be_cx = false; 175 switch (op) { 176 // X86 unary opcodes 177 case kOpMvn: 178 OpRegCopy(r_dest_src1, r_src2); 179 return OpReg(kOpNot, r_dest_src1); 180 case kOpNeg: 181 OpRegCopy(r_dest_src1, r_src2); 182 return OpReg(kOpNeg, r_dest_src1); 183 case kOpRev: 184 OpRegCopy(r_dest_src1, r_src2); 185 return OpReg(kOpRev, r_dest_src1); 186 case kOpRevsh: 187 OpRegCopy(r_dest_src1, r_src2); 188 OpReg(kOpRev, r_dest_src1); 189 return OpRegImm(kOpAsr, r_dest_src1, 16); 190 // X86 binary opcodes 191 case kOpSub: opcode = kX86Sub32RR; break; 192 case kOpSbc: opcode = kX86Sbb32RR; break; 193 case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break; 194 case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break; 195 case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break; 196 case kOpMov: opcode = kX86Mov32RR; break; 197 case kOpCmp: opcode = kX86Cmp32RR; break; 198 case kOpAdd: opcode = kX86Add32RR; break; 199 case kOpAdc: opcode = kX86Adc32RR; break; 200 case kOpAnd: opcode = kX86And32RR; break; 201 case kOpOr: opcode = kX86Or32RR; break; 202 case kOpXor: opcode = kX86Xor32RR; break; 203 case kOp2Byte: 204 // TODO: there are several instances of this check. A utility function perhaps? 205 // TODO: Similar to Arm's reg < 8 check. Perhaps add attribute checks to RegStorage? 206 // Use shifts instead of a byte operand if the source can't be byte accessed. 207 if (r_src2.GetRegNum() >= rs_rX86_SP.GetRegNum()) { 208 NewLIR2(kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg()); 209 NewLIR2(kX86Sal32RI, r_dest_src1.GetReg(), 24); 210 return NewLIR2(kX86Sar32RI, r_dest_src1.GetReg(), 24); 211 } else { 212 opcode = kX86Movsx8RR; 213 } 214 break; 215 case kOp2Short: opcode = kX86Movsx16RR; break; 216 case kOp2Char: opcode = kX86Movzx16RR; break; 217 case kOpMul: opcode = kX86Imul32RR; break; 218 default: 219 LOG(FATAL) << "Bad case in OpRegReg " << op; 220 break; 221 } 222 CHECK(!src2_must_be_cx || r_src2.GetReg() == rs_rCX.GetReg()); 223 return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg()); 224} 225 226LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 227 DCHECK(!r_base.IsFloat()); 228 X86OpCode opcode = kX86Nop; 229 int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 230 switch (move_type) { 231 case kMov8GP: 232 CHECK(!r_dest.IsFloat()); 233 opcode = kX86Mov8RM; 234 break; 235 case kMov16GP: 236 CHECK(!r_dest.IsFloat()); 237 opcode = kX86Mov16RM; 238 break; 239 case kMov32GP: 240 CHECK(!r_dest.IsFloat()); 241 opcode = kX86Mov32RM; 242 break; 243 case kMov32FP: 244 CHECK(r_dest.IsFloat()); 245 opcode = kX86MovssRM; 246 break; 247 case kMov64FP: 248 CHECK(r_dest.IsFloat()); 249 opcode = kX86MovsdRM; 250 break; 251 case kMovU128FP: 252 CHECK(r_dest.IsFloat()); 253 opcode = kX86MovupsRM; 254 break; 255 case kMovA128FP: 256 CHECK(r_dest.IsFloat()); 257 opcode = kX86MovapsRM; 258 break; 259 case kMovLo128FP: 260 CHECK(r_dest.IsFloat()); 261 opcode = kX86MovlpsRM; 262 break; 263 case kMovHi128FP: 264 CHECK(r_dest.IsFloat()); 265 opcode = kX86MovhpsRM; 266 break; 267 case kMov64GP: 268 case kMovLo64FP: 269 case kMovHi64FP: 270 default: 271 LOG(FATAL) << "Bad case in OpMovRegMem"; 272 break; 273 } 274 275 return NewLIR3(opcode, dest, r_base.GetReg(), offset); 276} 277 278LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 279 DCHECK(!r_base.IsFloat()); 280 int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg(); 281 282 X86OpCode opcode = kX86Nop; 283 switch (move_type) { 284 case kMov8GP: 285 CHECK(!r_src.IsFloat()); 286 opcode = kX86Mov8MR; 287 break; 288 case kMov16GP: 289 CHECK(!r_src.IsFloat()); 290 opcode = kX86Mov16MR; 291 break; 292 case kMov32GP: 293 CHECK(!r_src.IsFloat()); 294 opcode = kX86Mov32MR; 295 break; 296 case kMov32FP: 297 CHECK(r_src.IsFloat()); 298 opcode = kX86MovssMR; 299 break; 300 case kMov64FP: 301 CHECK(r_src.IsFloat()); 302 opcode = kX86MovsdMR; 303 break; 304 case kMovU128FP: 305 CHECK(r_src.IsFloat()); 306 opcode = kX86MovupsMR; 307 break; 308 case kMovA128FP: 309 CHECK(r_src.IsFloat()); 310 opcode = kX86MovapsMR; 311 break; 312 case kMovLo128FP: 313 CHECK(r_src.IsFloat()); 314 opcode = kX86MovlpsMR; 315 break; 316 case kMovHi128FP: 317 CHECK(r_src.IsFloat()); 318 opcode = kX86MovhpsMR; 319 break; 320 case kMov64GP: 321 case kMovLo64FP: 322 case kMovHi64FP: 323 default: 324 LOG(FATAL) << "Bad case in OpMovMemReg"; 325 break; 326 } 327 328 return NewLIR3(opcode, r_base.GetReg(), offset, src); 329} 330 331LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { 332 // The only conditional reg to reg operation supported is Cmov 333 DCHECK_EQ(op, kOpCmov); 334 return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc)); 335} 336 337LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { 338 X86OpCode opcode = kX86Nop; 339 switch (op) { 340 // X86 binary opcodes 341 case kOpSub: opcode = kX86Sub32RM; break; 342 case kOpMov: opcode = kX86Mov32RM; break; 343 case kOpCmp: opcode = kX86Cmp32RM; break; 344 case kOpAdd: opcode = kX86Add32RM; break; 345 case kOpAnd: opcode = kX86And32RM; break; 346 case kOpOr: opcode = kX86Or32RM; break; 347 case kOpXor: opcode = kX86Xor32RM; break; 348 case kOp2Byte: opcode = kX86Movsx8RM; break; 349 case kOp2Short: opcode = kX86Movsx16RM; break; 350 case kOp2Char: opcode = kX86Movzx16RM; break; 351 case kOpMul: 352 default: 353 LOG(FATAL) << "Bad case in OpRegMem " << op; 354 break; 355 } 356 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset); 357 if (r_base == rs_rX86_SP) { 358 AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); 359 } 360 return l; 361} 362 363LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { 364 DCHECK_NE(rl_dest.location, kLocPhysReg); 365 int displacement = SRegOffset(rl_dest.s_reg_low); 366 X86OpCode opcode = kX86Nop; 367 switch (op) { 368 case kOpSub: opcode = kX86Sub32MR; break; 369 case kOpMov: opcode = kX86Mov32MR; break; 370 case kOpCmp: opcode = kX86Cmp32MR; break; 371 case kOpAdd: opcode = kX86Add32MR; break; 372 case kOpAnd: opcode = kX86And32MR; break; 373 case kOpOr: opcode = kX86Or32MR; break; 374 case kOpXor: opcode = kX86Xor32MR; break; 375 case kOpLsl: opcode = kX86Sal32MC; break; 376 case kOpLsr: opcode = kX86Shr32MC; break; 377 case kOpAsr: opcode = kX86Sar32MC; break; 378 default: 379 LOG(FATAL) << "Bad case in OpMemReg " << op; 380 break; 381 } 382 LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value); 383 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); 384 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */); 385 return l; 386} 387 388LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) { 389 DCHECK_NE(rl_value.location, kLocPhysReg); 390 int displacement = SRegOffset(rl_value.s_reg_low); 391 X86OpCode opcode = kX86Nop; 392 switch (op) { 393 case kOpSub: opcode = kX86Sub32RM; break; 394 case kOpMov: opcode = kX86Mov32RM; break; 395 case kOpCmp: opcode = kX86Cmp32RM; break; 396 case kOpAdd: opcode = kX86Add32RM; break; 397 case kOpAnd: opcode = kX86And32RM; break; 398 case kOpOr: opcode = kX86Or32RM; break; 399 case kOpXor: opcode = kX86Xor32RM; break; 400 case kOpMul: opcode = kX86Imul32RM; break; 401 default: 402 LOG(FATAL) << "Bad case in OpRegMem " << op; 403 break; 404 } 405 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement); 406 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); 407 return l; 408} 409 410LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 411 RegStorage r_src2) { 412 if (r_dest != r_src1 && r_dest != r_src2) { 413 if (op == kOpAdd) { // lea special case, except can't encode rbp as base 414 if (r_src1 == r_src2) { 415 OpRegCopy(r_dest, r_src1); 416 return OpRegImm(kOpLsl, r_dest, 1); 417 } else if (r_src1 != rs_rBP) { 418 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src1.GetReg() /* base */, 419 r_src2.GetReg() /* index */, 0 /* scale */, 0 /* disp */); 420 } else { 421 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src2.GetReg() /* base */, 422 r_src1.GetReg() /* index */, 0 /* scale */, 0 /* disp */); 423 } 424 } else { 425 OpRegCopy(r_dest, r_src1); 426 return OpRegReg(op, r_dest, r_src2); 427 } 428 } else if (r_dest == r_src1) { 429 return OpRegReg(op, r_dest, r_src2); 430 } else { // r_dest == r_src2 431 switch (op) { 432 case kOpSub: // non-commutative 433 OpReg(kOpNeg, r_dest); 434 op = kOpAdd; 435 break; 436 case kOpSbc: 437 case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { 438 RegStorage t_reg = AllocTemp(); 439 OpRegCopy(t_reg, r_src1); 440 OpRegReg(op, t_reg, r_src2); 441 LIR* res = OpRegCopyNoInsert(r_dest, t_reg); 442 AppendLIR(res); 443 FreeTemp(t_reg); 444 return res; 445 } 446 case kOpAdd: // commutative 447 case kOpOr: 448 case kOpAdc: 449 case kOpAnd: 450 case kOpXor: 451 break; 452 default: 453 LOG(FATAL) << "Bad case in OpRegRegReg " << op; 454 } 455 return OpRegReg(op, r_dest, r_src1); 456 } 457} 458 459LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) { 460 if (op == kOpMul) { 461 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; 462 return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value); 463 } else if (op == kOpAnd) { 464 if (value == 0xFF && r_src.Low4()) { 465 return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg()); 466 } else if (value == 0xFFFF) { 467 return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg()); 468 } 469 } 470 if (r_dest != r_src) { 471 if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case 472 // TODO: fix bug in LEA encoding when disp == 0 473 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */, 474 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); 475 } else if (op == kOpAdd) { // lea add special case 476 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src.GetReg() /* base */, 477 rs_rX86_SP.GetReg()/*r4sib_no_index*/ /* index */, 0 /* scale */, value /* disp */); 478 } 479 OpRegCopy(r_dest, r_src); 480 } 481 return OpRegImm(op, r_dest, value); 482} 483 484LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { 485 DCHECK_EQ(kX86, cu_->instruction_set); 486 X86OpCode opcode = kX86Bkpt; 487 switch (op) { 488 case kOpBlx: opcode = kX86CallT; break; 489 case kOpBx: opcode = kX86JmpT; break; 490 default: 491 LOG(FATAL) << "Bad opcode: " << op; 492 break; 493 } 494 return NewLIR1(opcode, thread_offset.Int32Value()); 495} 496 497LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) { 498 DCHECK_EQ(kX86_64, cu_->instruction_set); 499 X86OpCode opcode = kX86Bkpt; 500 switch (op) { 501 case kOpBlx: opcode = kX86CallT; break; 502 case kOpBx: opcode = kX86JmpT; break; 503 default: 504 LOG(FATAL) << "Bad opcode: " << op; 505 break; 506 } 507 return NewLIR1(opcode, thread_offset.Int32Value()); 508} 509 510LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { 511 X86OpCode opcode = kX86Bkpt; 512 switch (op) { 513 case kOpBlx: opcode = kX86CallM; break; 514 default: 515 LOG(FATAL) << "Bad opcode: " << op; 516 break; 517 } 518 return NewLIR2(opcode, r_base.GetReg(), disp); 519} 520 521LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { 522 int32_t val_lo = Low32Bits(value); 523 int32_t val_hi = High32Bits(value); 524 int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 525 LIR *res; 526 bool is_fp = RegStorage::IsFloat(low_reg_val); 527 // TODO: clean this up once we fully recognize 64-bit storage containers. 528 if (is_fp) { 529 if (value == 0) { 530 return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 531 } else if (base_of_code_ != nullptr) { 532 // We will load the value from the literal area. 533 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 534 if (data_target == NULL) { 535 data_target = AddWideData(&literal_list_, val_lo, val_hi); 536 } 537 538 // Address the start of the method 539 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 540 rl_method = LoadValue(rl_method, kCoreReg); 541 542 // Load the proper value from the literal area. 543 // We don't know the proper offset for the value, so pick one that will force 544 // 4 byte offset. We will fix this up in the assembler later to have the right 545 // value. 546 res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::Solo64(low_reg_val), 547 kDouble); 548 res->target = data_target; 549 res->flags.fixup = kFixupLoad; 550 SetMemRefType(res, true, kLiteral); 551 store_method_addr_used_ = true; 552 } else { 553 if (val_lo == 0) { 554 res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 555 } else { 556 res = LoadConstantNoClobber(RegStorage::Solo32(low_reg_val), val_lo); 557 } 558 if (val_hi != 0) { 559 RegStorage r_dest_hi = AllocTempDouble(); 560 LoadConstantNoClobber(r_dest_hi, val_hi); 561 NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetReg()); 562 FreeTemp(r_dest_hi); 563 } 564 } 565 } else { 566 res = LoadConstantNoClobber(r_dest.GetLow(), val_lo); 567 LoadConstantNoClobber(r_dest.GetHigh(), val_hi); 568 } 569 return res; 570} 571 572LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 573 int displacement, RegStorage r_dest, OpSize size) { 574 LIR *load = NULL; 575 LIR *load2 = NULL; 576 bool is_array = r_index.Valid(); 577 bool pair = r_dest.IsPair(); 578 bool is64bit = ((size == k64) || (size == kDouble)); 579 X86OpCode opcode = kX86Nop; 580 switch (size) { 581 case k64: 582 case kDouble: 583 if (r_dest.IsFloat()) { 584 opcode = is_array ? kX86MovsdRA : kX86MovsdRM; 585 } else { 586 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 587 } 588 // TODO: double store is to unaligned address 589 DCHECK_EQ((displacement & 0x3), 0); 590 break; 591 case kWord: 592 if (Gen64Bit()) { 593 opcode = is_array ? kX86Mov64RA : kX86Mov64RM; 594 CHECK_EQ(is_array, false); 595 CHECK_EQ(r_dest.IsFloat(), false); 596 break; 597 } // else fall-through to k32 case 598 case k32: 599 case kSingle: 600 case kReference: // TODO: update for reference decompression on 64-bit targets. 601 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 602 if (r_dest.IsFloat()) { 603 opcode = is_array ? kX86MovssRA : kX86MovssRM; 604 DCHECK(r_dest.IsFloat()); 605 } 606 DCHECK_EQ((displacement & 0x3), 0); 607 break; 608 case kUnsignedHalf: 609 opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; 610 DCHECK_EQ((displacement & 0x1), 0); 611 break; 612 case kSignedHalf: 613 opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; 614 DCHECK_EQ((displacement & 0x1), 0); 615 break; 616 case kUnsignedByte: 617 opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; 618 break; 619 case kSignedByte: 620 opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; 621 break; 622 default: 623 LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; 624 } 625 626 if (!is_array) { 627 if (!pair) { 628 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 629 } else { 630 DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. 631 if (r_base == r_dest.GetLow()) { 632 load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), 633 displacement + HIWORD_OFFSET); 634 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 635 } else { 636 load = NewLIR3(opcode, r_dest.GetLowReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 637 load2 = NewLIR3(opcode, r_dest.GetHighReg(), r_base.GetReg(), 638 displacement + HIWORD_OFFSET); 639 } 640 } 641 if (r_base == rs_rX86_SP) { 642 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 643 true /* is_load */, is64bit); 644 if (pair) { 645 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, 646 true /* is_load */, is64bit); 647 } 648 } 649 } else { 650 if (!pair) { 651 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 652 displacement + LOWORD_OFFSET); 653 } else { 654 DCHECK(!r_dest.IsFloat()); // Make sure we're not still using a pair here. 655 if (r_base == r_dest.GetLow()) { 656 if (r_dest.GetHigh() == r_index) { 657 // We can't use either register for the first load. 658 RegStorage temp = AllocTemp(); 659 load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 660 displacement + HIWORD_OFFSET); 661 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 662 displacement + LOWORD_OFFSET); 663 OpRegCopy(r_dest.GetHigh(), temp); 664 FreeTemp(temp); 665 } else { 666 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 667 displacement + HIWORD_OFFSET); 668 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 669 displacement + LOWORD_OFFSET); 670 } 671 } else { 672 if (r_dest.GetLow() == r_index) { 673 // We can't use either register for the first load. 674 RegStorage temp = AllocTemp(); 675 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 676 displacement + LOWORD_OFFSET); 677 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 678 displacement + HIWORD_OFFSET); 679 OpRegCopy(r_dest.GetLow(), temp); 680 FreeTemp(temp); 681 } else { 682 load = NewLIR5(opcode, r_dest.GetLowReg(), r_base.GetReg(), r_index.GetReg(), scale, 683 displacement + LOWORD_OFFSET); 684 load2 = NewLIR5(opcode, r_dest.GetHighReg(), r_base.GetReg(), r_index.GetReg(), scale, 685 displacement + HIWORD_OFFSET); 686 } 687 } 688 } 689 } 690 691 return load; 692} 693 694/* Load value from base + scaled index. */ 695LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 696 int scale, OpSize size) { 697 return LoadBaseIndexedDisp(r_base, r_index, scale, 0, r_dest, size); 698} 699 700LIR* X86Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 701 OpSize size) { 702 // LoadBaseDisp() will emit correct insn for atomic load on x86 703 // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). 704 return LoadBaseDisp(r_base, displacement, r_dest, size); 705} 706 707LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 708 OpSize size) { 709 return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_dest, 710 size); 711} 712 713LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 714 int displacement, RegStorage r_src, OpSize size) { 715 LIR *store = NULL; 716 LIR *store2 = NULL; 717 bool is_array = r_index.Valid(); 718 bool pair = r_src.IsPair(); 719 bool is64bit = (size == k64) || (size == kDouble); 720 X86OpCode opcode = kX86Nop; 721 switch (size) { 722 case k64: 723 case kDouble: 724 if (r_src.IsFloat()) { 725 opcode = is_array ? kX86MovsdAR : kX86MovsdMR; 726 } else { 727 if (Gen64Bit()) { 728 opcode = is_array ? kX86Mov64AR : kX86Mov64MR; 729 } else { 730 // TODO(64): pair = true; 731 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 732 } 733 } 734 // TODO: double store is to unaligned address 735 DCHECK_EQ((displacement & 0x3), 0); 736 break; 737 case kWord: 738 if (Gen64Bit()) { 739 opcode = is_array ? kX86Mov64AR : kX86Mov64MR; 740 CHECK_EQ(is_array, false); 741 CHECK_EQ(r_src.IsFloat(), false); 742 break; 743 } // else fall-through to k32 case 744 case k32: 745 case kSingle: 746 case kReference: 747 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 748 if (r_src.IsFloat()) { 749 opcode = is_array ? kX86MovssAR : kX86MovssMR; 750 DCHECK(r_src.IsSingle()); 751 } 752 DCHECK_EQ((displacement & 0x3), 0); 753 break; 754 case kUnsignedHalf: 755 case kSignedHalf: 756 opcode = is_array ? kX86Mov16AR : kX86Mov16MR; 757 DCHECK_EQ((displacement & 0x1), 0); 758 break; 759 case kUnsignedByte: 760 case kSignedByte: 761 opcode = is_array ? kX86Mov8AR : kX86Mov8MR; 762 break; 763 default: 764 LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody"; 765 } 766 767 if (!is_array) { 768 if (!pair) { 769 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); 770 } else { 771 DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. 772 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetLowReg()); 773 store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src.GetHighReg()); 774 } 775 if (r_base == rs_rX86_SP) { 776 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 777 false /* is_load */, is64bit); 778 if (pair) { 779 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, 780 false /* is_load */, is64bit); 781 } 782 } 783 } else { 784 if (!pair) { 785 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 786 displacement + LOWORD_OFFSET, r_src.GetReg()); 787 } else { 788 DCHECK(!r_src.IsFloat()); // Make sure we're not still using a pair here. 789 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 790 displacement + LOWORD_OFFSET, r_src.GetLowReg()); 791 store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 792 displacement + HIWORD_OFFSET, r_src.GetHighReg()); 793 } 794 } 795 return store; 796} 797 798/* store value base base + scaled index. */ 799LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 800 int scale, OpSize size) { 801 return StoreBaseIndexedDisp(r_base, r_index, scale, 0, r_src, size); 802} 803 804LIR* X86Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement, 805 RegStorage r_src, OpSize size) { 806 // StoreBaseDisp() will emit correct insn for atomic store on x86 807 // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). 808 return StoreBaseDisp(r_base, displacement, r_src, size); 809} 810 811LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, 812 RegStorage r_src, OpSize size) { 813 return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, size); 814} 815 816LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 817 int offset, int check_value, LIR* target) { 818 NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset, 819 check_value); 820 LIR* branch = OpCondBranch(cond, target); 821 return branch; 822} 823 824void X86Mir2Lir::AnalyzeMIR() { 825 // Assume we don't need a pointer to the base of the code. 826 cu_->NewTimingSplit("X86 MIR Analysis"); 827 store_method_addr_ = false; 828 829 // Walk the MIR looking for interesting items. 830 PreOrderDfsIterator iter(mir_graph_); 831 BasicBlock* curr_bb = iter.Next(); 832 while (curr_bb != NULL) { 833 AnalyzeBB(curr_bb); 834 curr_bb = iter.Next(); 835 } 836 837 // Did we need a pointer to the method code? 838 if (store_method_addr_) { 839 base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, false); 840 } else { 841 base_of_code_ = nullptr; 842 } 843} 844 845void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) { 846 if (bb->block_type == kDead) { 847 // Ignore dead blocks 848 return; 849 } 850 851 for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 852 int opcode = mir->dalvikInsn.opcode; 853 if (opcode >= kMirOpFirst) { 854 AnalyzeExtendedMIR(opcode, bb, mir); 855 } else { 856 AnalyzeMIR(opcode, bb, mir); 857 } 858 } 859} 860 861 862void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { 863 switch (opcode) { 864 // Instructions referencing doubles. 865 case kMirOpFusedCmplDouble: 866 case kMirOpFusedCmpgDouble: 867 AnalyzeFPInstruction(opcode, bb, mir); 868 break; 869 case kMirOpConstVector: 870 store_method_addr_ = true; 871 break; 872 default: 873 // Ignore the rest. 874 break; 875 } 876} 877 878void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { 879 // Looking for 880 // - Do we need a pointer to the code (used for packed switches and double lits)? 881 882 switch (opcode) { 883 // Instructions referencing doubles. 884 case Instruction::CMPL_DOUBLE: 885 case Instruction::CMPG_DOUBLE: 886 case Instruction::NEG_DOUBLE: 887 case Instruction::ADD_DOUBLE: 888 case Instruction::SUB_DOUBLE: 889 case Instruction::MUL_DOUBLE: 890 case Instruction::DIV_DOUBLE: 891 case Instruction::REM_DOUBLE: 892 case Instruction::ADD_DOUBLE_2ADDR: 893 case Instruction::SUB_DOUBLE_2ADDR: 894 case Instruction::MUL_DOUBLE_2ADDR: 895 case Instruction::DIV_DOUBLE_2ADDR: 896 case Instruction::REM_DOUBLE_2ADDR: 897 AnalyzeFPInstruction(opcode, bb, mir); 898 break; 899 900 // Packed switches and array fills need a pointer to the base of the method. 901 case Instruction::FILL_ARRAY_DATA: 902 case Instruction::PACKED_SWITCH: 903 store_method_addr_ = true; 904 break; 905 default: 906 // Other instructions are not interesting yet. 907 break; 908 } 909} 910 911void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) { 912 // Look at all the uses, and see if they are double constants. 913 uint64_t attrs = MIRGraph::GetDataFlowAttributes(static_cast<Instruction::Code>(opcode)); 914 int next_sreg = 0; 915 if (attrs & DF_UA) { 916 if (attrs & DF_A_WIDE) { 917 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 918 next_sreg += 2; 919 } else { 920 next_sreg++; 921 } 922 } 923 if (attrs & DF_UB) { 924 if (attrs & DF_B_WIDE) { 925 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 926 next_sreg += 2; 927 } else { 928 next_sreg++; 929 } 930 } 931 if (attrs & DF_UC) { 932 if (attrs & DF_C_WIDE) { 933 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 934 } 935 } 936} 937 938void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) { 939 // If this is a double literal, we will want it in the literal pool. 940 if (use.is_const) { 941 store_method_addr_ = true; 942 } 943} 944 945RegLocation X86Mir2Lir::UpdateLocTyped(RegLocation loc, int reg_class) { 946 loc = UpdateLoc(loc); 947 if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { 948 if (GetRegInfo(loc.reg)->IsTemp()) { 949 Clobber(loc.reg); 950 FreeTemp(loc.reg); 951 loc.reg = RegStorage::InvalidReg(); 952 loc.location = kLocDalvikFrame; 953 } 954 } 955 return loc; 956} 957 958RegLocation X86Mir2Lir::UpdateLocWideTyped(RegLocation loc, int reg_class) { 959 loc = UpdateLocWide(loc); 960 if ((loc.location == kLocPhysReg) && (loc.fp != loc.reg.IsFloat())) { 961 if (GetRegInfo(loc.reg)->IsTemp()) { 962 Clobber(loc.reg); 963 FreeTemp(loc.reg); 964 loc.reg = RegStorage::InvalidReg(); 965 loc.location = kLocDalvikFrame; 966 } 967 } 968 return loc; 969} 970 971} // namespace art 972