utility_x86.cc revision dd7624d2b9e599d57762d12031b10b89defc9807
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "codegen_x86.h" 18#include "dex/quick/mir_to_lir-inl.h" 19#include "dex/dataflow_iterator-inl.h" 20#include "x86_lir.h" 21 22namespace art { 23 24/* This file contains codegen for the X86 ISA */ 25 26LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { 27 int opcode; 28 /* must be both DOUBLE or both not DOUBLE */ 29 DCHECK_EQ(X86_DOUBLEREG(r_dest.GetReg()), X86_DOUBLEREG(r_src.GetReg())); 30 if (X86_DOUBLEREG(r_dest.GetReg())) { 31 opcode = kX86MovsdRR; 32 } else { 33 if (X86_SINGLEREG(r_dest.GetReg())) { 34 if (X86_SINGLEREG(r_src.GetReg())) { 35 opcode = kX86MovssRR; 36 } else { // Fpr <- Gpr 37 opcode = kX86MovdxrRR; 38 } 39 } else { // Gpr <- Fpr 40 DCHECK(X86_SINGLEREG(r_src.GetReg())); 41 opcode = kX86MovdrxRR; 42 } 43 } 44 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); 45 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 46 if (r_dest == r_src) { 47 res->flags.is_nop = true; 48 } 49 return res; 50} 51 52bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { 53 return true; 54} 55 56bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { 57 return false; 58} 59 60bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { 61 return true; 62} 63 64bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { 65 return value == 0; 66} 67 68/* 69 * Load a immediate using a shortcut if possible; otherwise 70 * grab from the per-translation literal pool. If target is 71 * a high register, build constant into a low register and copy. 72 * 73 * No additional register clobbering operation performed. Use this version when 74 * 1) r_dest is freshly returned from AllocTemp or 75 * 2) The codegen is under fixed register usage 76 */ 77LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { 78 RegStorage r_dest_save = r_dest; 79 if (X86_FPREG(r_dest.GetReg())) { 80 if (value == 0) { 81 return NewLIR2(kX86XorpsRR, r_dest.GetReg(), r_dest.GetReg()); 82 } 83 DCHECK(X86_SINGLEREG(r_dest.GetReg())); 84 r_dest = AllocTemp(); 85 } 86 87 LIR *res; 88 if (value == 0) { 89 res = NewLIR2(kX86Xor32RR, r_dest.GetReg(), r_dest.GetReg()); 90 } else { 91 // Note, there is no byte immediate form of a 32 bit immediate move. 92 res = NewLIR2(kX86Mov32RI, r_dest.GetReg(), value); 93 } 94 95 if (X86_FPREG(r_dest_save.GetReg())) { 96 NewLIR2(kX86MovdxrRR, r_dest_save.GetReg(), r_dest.GetReg()); 97 FreeTemp(r_dest); 98 } 99 100 return res; 101} 102 103LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { 104 LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/); 105 res->target = target; 106 return res; 107} 108 109LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { 110 LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */, 111 X86ConditionEncoding(cc)); 112 branch->target = target; 113 return branch; 114} 115 116LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { 117 X86OpCode opcode = kX86Bkpt; 118 switch (op) { 119 case kOpNeg: opcode = kX86Neg32R; break; 120 case kOpNot: opcode = kX86Not32R; break; 121 case kOpRev: opcode = kX86Bswap32R; break; 122 case kOpBlx: opcode = kX86CallR; break; 123 default: 124 LOG(FATAL) << "Bad case in OpReg " << op; 125 } 126 return NewLIR1(opcode, r_dest_src.GetReg()); 127} 128 129LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { 130 X86OpCode opcode = kX86Bkpt; 131 bool byte_imm = IS_SIMM8(value); 132 DCHECK(!X86_FPREG(r_dest_src1.GetReg())); 133 switch (op) { 134 case kOpLsl: opcode = kX86Sal32RI; break; 135 case kOpLsr: opcode = kX86Shr32RI; break; 136 case kOpAsr: opcode = kX86Sar32RI; break; 137 case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break; 138 case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break; 139 case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break; 140 // case kOpSbb: opcode = kX86Sbb32RI; break; 141 case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break; 142 case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break; 143 case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break; 144 case kOpCmp: opcode = byte_imm ? kX86Cmp32RI8 : kX86Cmp32RI; break; 145 case kOpMov: 146 /* 147 * Moving the constant zero into register can be specialized as an xor of the register. 148 * However, that sets eflags while the move does not. For that reason here, always do 149 * the move and if caller is flexible, they should be calling LoadConstantNoClobber instead. 150 */ 151 opcode = kX86Mov32RI; 152 break; 153 case kOpMul: 154 opcode = byte_imm ? kX86Imul32RRI8 : kX86Imul32RRI; 155 return NewLIR3(opcode, r_dest_src1.GetReg(), r_dest_src1.GetReg(), value); 156 default: 157 LOG(FATAL) << "Bad case in OpRegImm " << op; 158 } 159 return NewLIR2(opcode, r_dest_src1.GetReg(), value); 160} 161 162LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { 163 X86OpCode opcode = kX86Nop; 164 bool src2_must_be_cx = false; 165 switch (op) { 166 // X86 unary opcodes 167 case kOpMvn: 168 OpRegCopy(r_dest_src1, r_src2); 169 return OpReg(kOpNot, r_dest_src1); 170 case kOpNeg: 171 OpRegCopy(r_dest_src1, r_src2); 172 return OpReg(kOpNeg, r_dest_src1); 173 case kOpRev: 174 OpRegCopy(r_dest_src1, r_src2); 175 return OpReg(kOpRev, r_dest_src1); 176 case kOpRevsh: 177 OpRegCopy(r_dest_src1, r_src2); 178 OpReg(kOpRev, r_dest_src1); 179 return OpRegImm(kOpAsr, r_dest_src1, 16); 180 // X86 binary opcodes 181 case kOpSub: opcode = kX86Sub32RR; break; 182 case kOpSbc: opcode = kX86Sbb32RR; break; 183 case kOpLsl: opcode = kX86Sal32RC; src2_must_be_cx = true; break; 184 case kOpLsr: opcode = kX86Shr32RC; src2_must_be_cx = true; break; 185 case kOpAsr: opcode = kX86Sar32RC; src2_must_be_cx = true; break; 186 case kOpMov: opcode = kX86Mov32RR; break; 187 case kOpCmp: opcode = kX86Cmp32RR; break; 188 case kOpAdd: opcode = kX86Add32RR; break; 189 case kOpAdc: opcode = kX86Adc32RR; break; 190 case kOpAnd: opcode = kX86And32RR; break; 191 case kOpOr: opcode = kX86Or32RR; break; 192 case kOpXor: opcode = kX86Xor32RR; break; 193 case kOp2Byte: 194 // Use shifts instead of a byte operand if the source can't be byte accessed. 195 if (r_src2.GetReg() >= 4) { 196 NewLIR2(kX86Mov32RR, r_dest_src1.GetReg(), r_src2.GetReg()); 197 NewLIR2(kX86Sal32RI, r_dest_src1.GetReg(), 24); 198 return NewLIR2(kX86Sar32RI, r_dest_src1.GetReg(), 24); 199 } else { 200 opcode = kX86Movsx8RR; 201 } 202 break; 203 case kOp2Short: opcode = kX86Movsx16RR; break; 204 case kOp2Char: opcode = kX86Movzx16RR; break; 205 case kOpMul: opcode = kX86Imul32RR; break; 206 default: 207 LOG(FATAL) << "Bad case in OpRegReg " << op; 208 break; 209 } 210 CHECK(!src2_must_be_cx || r_src2.GetReg() == rCX); 211 return NewLIR2(opcode, r_dest_src1.GetReg(), r_src2.GetReg()); 212} 213 214LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { 215 DCHECK(!(X86_FPREG(r_base.GetReg()))); 216 X86OpCode opcode = kX86Nop; 217 int dest = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 218 switch (move_type) { 219 case kMov8GP: 220 CHECK(!X86_FPREG(dest)); 221 opcode = kX86Mov8RM; 222 break; 223 case kMov16GP: 224 CHECK(!X86_FPREG(dest)); 225 opcode = kX86Mov16RM; 226 break; 227 case kMov32GP: 228 CHECK(!X86_FPREG(dest)); 229 opcode = kX86Mov32RM; 230 break; 231 case kMov32FP: 232 CHECK(X86_FPREG(dest)); 233 opcode = kX86MovssRM; 234 break; 235 case kMov64FP: 236 CHECK(X86_FPREG(dest)); 237 opcode = kX86MovsdRM; 238 break; 239 case kMovU128FP: 240 CHECK(X86_FPREG(dest)); 241 opcode = kX86MovupsRM; 242 break; 243 case kMovA128FP: 244 CHECK(X86_FPREG(dest)); 245 opcode = kX86MovapsRM; 246 break; 247 case kMovLo128FP: 248 CHECK(X86_FPREG(dest)); 249 opcode = kX86MovlpsRM; 250 break; 251 case kMovHi128FP: 252 CHECK(X86_FPREG(dest)); 253 opcode = kX86MovhpsRM; 254 break; 255 case kMov64GP: 256 case kMovLo64FP: 257 case kMovHi64FP: 258 default: 259 LOG(FATAL) << "Bad case in OpMovRegMem"; 260 break; 261 } 262 263 return NewLIR3(opcode, dest, r_base.GetReg(), offset); 264} 265 266LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 267 DCHECK(!(X86_FPREG(r_base.GetReg()))); 268 int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg(); 269 270 X86OpCode opcode = kX86Nop; 271 switch (move_type) { 272 case kMov8GP: 273 CHECK(!X86_FPREG(src)); 274 opcode = kX86Mov8MR; 275 break; 276 case kMov16GP: 277 CHECK(!X86_FPREG(src)); 278 opcode = kX86Mov16MR; 279 break; 280 case kMov32GP: 281 CHECK(!X86_FPREG(src)); 282 opcode = kX86Mov32MR; 283 break; 284 case kMov32FP: 285 CHECK(X86_FPREG(src)); 286 opcode = kX86MovssMR; 287 break; 288 case kMov64FP: 289 CHECK(X86_FPREG(src)); 290 opcode = kX86MovsdMR; 291 break; 292 case kMovU128FP: 293 CHECK(X86_FPREG(src)); 294 opcode = kX86MovupsMR; 295 break; 296 case kMovA128FP: 297 CHECK(X86_FPREG(src)); 298 opcode = kX86MovapsMR; 299 break; 300 case kMovLo128FP: 301 CHECK(X86_FPREG(src)); 302 opcode = kX86MovlpsMR; 303 break; 304 case kMovHi128FP: 305 CHECK(X86_FPREG(src)); 306 opcode = kX86MovhpsMR; 307 break; 308 case kMov64GP: 309 case kMovLo64FP: 310 case kMovHi64FP: 311 default: 312 LOG(FATAL) << "Bad case in OpMovMemReg"; 313 break; 314 } 315 316 return NewLIR3(opcode, r_base.GetReg(), offset, src); 317} 318 319LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { 320 // The only conditional reg to reg operation supported is Cmov 321 DCHECK_EQ(op, kOpCmov); 322 return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc)); 323} 324 325LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { 326 X86OpCode opcode = kX86Nop; 327 switch (op) { 328 // X86 binary opcodes 329 case kOpSub: opcode = kX86Sub32RM; break; 330 case kOpMov: opcode = kX86Mov32RM; break; 331 case kOpCmp: opcode = kX86Cmp32RM; break; 332 case kOpAdd: opcode = kX86Add32RM; break; 333 case kOpAnd: opcode = kX86And32RM; break; 334 case kOpOr: opcode = kX86Or32RM; break; 335 case kOpXor: opcode = kX86Xor32RM; break; 336 case kOp2Byte: opcode = kX86Movsx8RM; break; 337 case kOp2Short: opcode = kX86Movsx16RM; break; 338 case kOp2Char: opcode = kX86Movzx16RM; break; 339 case kOpMul: 340 default: 341 LOG(FATAL) << "Bad case in OpRegMem " << op; 342 break; 343 } 344 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset); 345 if (r_base == rs_rX86_SP) { 346 AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); 347 } 348 return l; 349} 350 351LIR* X86Mir2Lir::OpMemReg(OpKind op, RegLocation rl_dest, int r_value) { 352 DCHECK_NE(rl_dest.location, kLocPhysReg); 353 int displacement = SRegOffset(rl_dest.s_reg_low); 354 X86OpCode opcode = kX86Nop; 355 switch (op) { 356 case kOpSub: opcode = kX86Sub32MR; break; 357 case kOpMov: opcode = kX86Mov32MR; break; 358 case kOpCmp: opcode = kX86Cmp32MR; break; 359 case kOpAdd: opcode = kX86Add32MR; break; 360 case kOpAnd: opcode = kX86And32MR; break; 361 case kOpOr: opcode = kX86Or32MR; break; 362 case kOpXor: opcode = kX86Xor32MR; break; 363 case kOpLsl: opcode = kX86Sal32MC; break; 364 case kOpLsr: opcode = kX86Shr32MC; break; 365 case kOpAsr: opcode = kX86Sar32MC; break; 366 default: 367 LOG(FATAL) << "Bad case in OpMemReg " << op; 368 break; 369 } 370 LIR *l = NewLIR3(opcode, rX86_SP, displacement, r_value); 371 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); 372 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, false /* is_64bit */); 373 return l; 374} 375 376LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegLocation rl_value) { 377 DCHECK_NE(rl_value.location, kLocPhysReg); 378 int displacement = SRegOffset(rl_value.s_reg_low); 379 X86OpCode opcode = kX86Nop; 380 switch (op) { 381 case kOpSub: opcode = kX86Sub32RM; break; 382 case kOpMov: opcode = kX86Mov32RM; break; 383 case kOpCmp: opcode = kX86Cmp32RM; break; 384 case kOpAdd: opcode = kX86Add32RM; break; 385 case kOpAnd: opcode = kX86And32RM; break; 386 case kOpOr: opcode = kX86Or32RM; break; 387 case kOpXor: opcode = kX86Xor32RM; break; 388 case kOpMul: opcode = kX86Imul32RM; break; 389 default: 390 LOG(FATAL) << "Bad case in OpRegMem " << op; 391 break; 392 } 393 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rX86_SP, displacement); 394 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, false /* is_64bit */); 395 return l; 396} 397 398LIR* X86Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, 399 RegStorage r_src2) { 400 if (r_dest != r_src1 && r_dest != r_src2) { 401 if (op == kOpAdd) { // lea special case, except can't encode rbp as base 402 if (r_src1 == r_src2) { 403 OpRegCopy(r_dest, r_src1); 404 return OpRegImm(kOpLsl, r_dest, 1); 405 } else if (r_src1 != rs_rBP) { 406 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src1.GetReg() /* base */, 407 r_src2.GetReg() /* index */, 0 /* scale */, 0 /* disp */); 408 } else { 409 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src2.GetReg() /* base */, 410 r_src1.GetReg() /* index */, 0 /* scale */, 0 /* disp */); 411 } 412 } else { 413 OpRegCopy(r_dest, r_src1); 414 return OpRegReg(op, r_dest, r_src2); 415 } 416 } else if (r_dest == r_src1) { 417 return OpRegReg(op, r_dest, r_src2); 418 } else { // r_dest == r_src2 419 switch (op) { 420 case kOpSub: // non-commutative 421 OpReg(kOpNeg, r_dest); 422 op = kOpAdd; 423 break; 424 case kOpSbc: 425 case kOpLsl: case kOpLsr: case kOpAsr: case kOpRor: { 426 RegStorage t_reg = AllocTemp(); 427 OpRegCopy(t_reg, r_src1); 428 OpRegReg(op, t_reg, r_src2); 429 LIR* res = OpRegCopy(r_dest, t_reg); 430 FreeTemp(t_reg); 431 return res; 432 } 433 case kOpAdd: // commutative 434 case kOpOr: 435 case kOpAdc: 436 case kOpAnd: 437 case kOpXor: 438 break; 439 default: 440 LOG(FATAL) << "Bad case in OpRegRegReg " << op; 441 } 442 return OpRegReg(op, r_dest, r_src1); 443 } 444} 445 446LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int value) { 447 if (op == kOpMul) { 448 X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI; 449 return NewLIR3(opcode, r_dest.GetReg(), r_src.GetReg(), value); 450 } else if (op == kOpAnd) { 451 if (value == 0xFF && r_src.GetReg() < 4) { 452 return NewLIR2(kX86Movzx8RR, r_dest.GetReg(), r_src.GetReg()); 453 } else if (value == 0xFFFF) { 454 return NewLIR2(kX86Movzx16RR, r_dest.GetReg(), r_src.GetReg()); 455 } 456 } 457 if (r_dest != r_src) { 458 if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case 459 // TODO: fix bug in LEA encoding when disp == 0 460 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */, 461 r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); 462 } else if (op == kOpAdd) { // lea add special case 463 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r_src.GetReg() /* base */, 464 r4sib_no_index /* index */, 0 /* scale */, value /* disp */); 465 } 466 OpRegCopy(r_dest, r_src); 467 } 468 return OpRegImm(op, r_dest, value); 469} 470 471LIR* X86Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { 472 X86OpCode opcode = kX86Bkpt; 473 switch (op) { 474 case kOpBlx: opcode = kX86CallT; break; 475 case kOpBx: opcode = kX86JmpT; break; 476 default: 477 LOG(FATAL) << "Bad opcode: " << op; 478 break; 479 } 480 return NewLIR1(opcode, thread_offset.Int32Value()); 481} 482 483LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { 484 X86OpCode opcode = kX86Bkpt; 485 switch (op) { 486 case kOpBlx: opcode = kX86CallM; break; 487 default: 488 LOG(FATAL) << "Bad opcode: " << op; 489 break; 490 } 491 return NewLIR2(opcode, r_base.GetReg(), disp); 492} 493 494LIR* X86Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { 495 int32_t val_lo = Low32Bits(value); 496 int32_t val_hi = High32Bits(value); 497 int32_t low_reg_val = r_dest.IsPair() ? r_dest.GetLowReg() : r_dest.GetReg(); 498 LIR *res; 499 bool is_fp = X86_FPREG(low_reg_val); 500 // TODO: clean this up once we fully recognize 64-bit storage containers. 501 if (is_fp) { 502 if (value == 0) { 503 return NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 504 } else if (base_of_code_ != nullptr) { 505 // We will load the value from the literal area. 506 LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); 507 if (data_target == NULL) { 508 data_target = AddWideData(&literal_list_, val_lo, val_hi); 509 } 510 511 // Address the start of the method 512 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); 513 rl_method = LoadValue(rl_method, kCoreReg); 514 515 // Load the proper value from the literal area. 516 // We don't know the proper offset for the value, so pick one that will force 517 // 4 byte offset. We will fix this up in the assembler later to have the right 518 // value. 519 res = LoadBaseDisp(rl_method.reg, 256 /* bogus */, RegStorage::Solo64(low_reg_val), 520 kDouble, INVALID_SREG); 521 res->target = data_target; 522 res->flags.fixup = kFixupLoad; 523 SetMemRefType(res, true, kLiteral); 524 store_method_addr_used_ = true; 525 } else { 526 if (val_lo == 0) { 527 res = NewLIR2(kX86XorpsRR, low_reg_val, low_reg_val); 528 } else { 529 res = LoadConstantNoClobber(RegStorage::Solo32(low_reg_val), val_lo); 530 } 531 if (val_hi != 0) { 532 // FIXME: clean up when AllocTempDouble no longer returns a pair. 533 RegStorage r_dest_hi = AllocTempDouble(); 534 LoadConstantNoClobber(RegStorage::Solo32(r_dest_hi.GetLowReg()), val_hi); 535 NewLIR2(kX86PunpckldqRR, low_reg_val, r_dest_hi.GetLowReg()); 536 FreeTemp(r_dest_hi); 537 } 538 } 539 } else { 540 res = LoadConstantNoClobber(r_dest.GetLow(), val_lo); 541 LoadConstantNoClobber(r_dest.GetHigh(), val_hi); 542 } 543 return res; 544} 545 546// FIXME: don't split r_dest into two storage units. 547LIR* X86Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 548 int displacement, RegStorage r_dest, RegStorage r_dest_hi, 549 OpSize size, int s_reg) { 550 LIR *load = NULL; 551 LIR *load2 = NULL; 552 bool is_array = r_index.Valid(); 553 bool pair = false; 554 bool is64bit = false; 555 X86OpCode opcode = kX86Nop; 556 switch (size) { 557 case kLong: 558 case kDouble: 559 // TODO: use regstorage attributes here. 560 is64bit = true; 561 if (X86_FPREG(r_dest.GetReg())) { 562 opcode = is_array ? kX86MovsdRA : kX86MovsdRM; 563 } else { 564 pair = true; 565 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 566 } 567 // TODO: double store is to unaligned address 568 DCHECK_EQ((displacement & 0x3), 0); 569 break; 570 case kWord: 571 case kSingle: 572 opcode = is_array ? kX86Mov32RA : kX86Mov32RM; 573 if (X86_FPREG(r_dest.GetReg())) { 574 opcode = is_array ? kX86MovssRA : kX86MovssRM; 575 DCHECK(X86_SINGLEREG(r_dest.GetReg())); 576 } 577 DCHECK_EQ((displacement & 0x3), 0); 578 break; 579 case kUnsignedHalf: 580 opcode = is_array ? kX86Movzx16RA : kX86Movzx16RM; 581 DCHECK_EQ((displacement & 0x1), 0); 582 break; 583 case kSignedHalf: 584 opcode = is_array ? kX86Movsx16RA : kX86Movsx16RM; 585 DCHECK_EQ((displacement & 0x1), 0); 586 break; 587 case kUnsignedByte: 588 opcode = is_array ? kX86Movzx8RA : kX86Movzx8RM; 589 break; 590 case kSignedByte: 591 opcode = is_array ? kX86Movsx8RA : kX86Movsx8RM; 592 break; 593 default: 594 LOG(FATAL) << "Bad case in LoadBaseIndexedDispBody"; 595 } 596 597 if (!is_array) { 598 if (!pair) { 599 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 600 } else { 601 if (r_base == r_dest) { 602 load2 = NewLIR3(opcode, r_dest_hi.GetReg(), r_base.GetReg(), 603 displacement + HIWORD_OFFSET); 604 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 605 } else { 606 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), displacement + LOWORD_OFFSET); 607 load2 = NewLIR3(opcode, r_dest_hi.GetReg(), r_base.GetReg(), 608 displacement + HIWORD_OFFSET); 609 } 610 } 611 if (r_base == rs_rX86_SP) { 612 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 613 true /* is_load */, is64bit); 614 if (pair) { 615 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, 616 true /* is_load */, is64bit); 617 } 618 } 619 } else { 620 if (!pair) { 621 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 622 displacement + LOWORD_OFFSET); 623 } else { 624 if (r_base == r_dest) { 625 if (r_dest_hi == r_index) { 626 // We can't use either register for the first load. 627 RegStorage temp = AllocTemp(); 628 load2 = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 629 displacement + HIWORD_OFFSET); 630 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 631 displacement + LOWORD_OFFSET); 632 OpRegCopy(r_dest_hi, temp); 633 FreeTemp(temp); 634 } else { 635 load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 636 displacement + HIWORD_OFFSET); 637 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 638 displacement + LOWORD_OFFSET); 639 } 640 } else { 641 if (r_dest == r_index) { 642 // We can't use either register for the first load. 643 RegStorage temp = AllocTemp(); 644 load = NewLIR5(opcode, temp.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 645 displacement + LOWORD_OFFSET); 646 load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 647 displacement + HIWORD_OFFSET); 648 OpRegCopy(r_dest, temp); 649 FreeTemp(temp); 650 } else { 651 load = NewLIR5(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 652 displacement + LOWORD_OFFSET); 653 load2 = NewLIR5(opcode, r_dest_hi.GetReg(), r_base.GetReg(), r_index.GetReg(), scale, 654 displacement + HIWORD_OFFSET); 655 } 656 } 657 } 658 } 659 660 return load; 661} 662 663/* Load value from base + scaled index. */ 664LIR* X86Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, 665 int scale, OpSize size) { 666 return LoadBaseIndexedDisp(r_base, r_index, scale, 0, 667 r_dest, RegStorage::InvalidReg(), size, INVALID_SREG); 668} 669 670LIR* X86Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, 671 RegStorage r_dest, OpSize size, int s_reg) { 672 return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, 673 r_dest, RegStorage::InvalidReg(), size, s_reg); 674} 675 676LIR* X86Mir2Lir::LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, 677 int s_reg) { 678 return LoadBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, 679 r_dest.GetLow(), r_dest.GetHigh(), kLong, s_reg); 680} 681 682LIR* X86Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, 683 int displacement, RegStorage r_src, RegStorage r_src_hi, 684 OpSize size, int s_reg) { 685 LIR *store = NULL; 686 LIR *store2 = NULL; 687 bool is_array = r_index.Valid(); 688 // FIXME: use regstorage attributes in place of these. 689 bool pair = false; 690 bool is64bit = false; 691 X86OpCode opcode = kX86Nop; 692 switch (size) { 693 case kLong: 694 case kDouble: 695 is64bit = true; 696 if (X86_FPREG(r_src.GetReg())) { 697 opcode = is_array ? kX86MovsdAR : kX86MovsdMR; 698 } else { 699 pair = true; 700 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 701 } 702 // TODO: double store is to unaligned address 703 DCHECK_EQ((displacement & 0x3), 0); 704 break; 705 case kWord: 706 case kSingle: 707 opcode = is_array ? kX86Mov32AR : kX86Mov32MR; 708 if (X86_FPREG(r_src.GetReg())) { 709 opcode = is_array ? kX86MovssAR : kX86MovssMR; 710 DCHECK(X86_SINGLEREG(r_src.GetReg())); 711 } 712 DCHECK_EQ((displacement & 0x3), 0); 713 break; 714 case kUnsignedHalf: 715 case kSignedHalf: 716 opcode = is_array ? kX86Mov16AR : kX86Mov16MR; 717 DCHECK_EQ((displacement & 0x1), 0); 718 break; 719 case kUnsignedByte: 720 case kSignedByte: 721 opcode = is_array ? kX86Mov8AR : kX86Mov8MR; 722 break; 723 default: 724 LOG(FATAL) << "Bad case in StoreBaseIndexedDispBody"; 725 } 726 727 if (!is_array) { 728 if (!pair) { 729 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); 730 } else { 731 store = NewLIR3(opcode, r_base.GetReg(), displacement + LOWORD_OFFSET, r_src.GetReg()); 732 store2 = NewLIR3(opcode, r_base.GetReg(), displacement + HIWORD_OFFSET, r_src_hi.GetReg()); 733 } 734 if (r_base == rs_rX86_SP) { 735 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, 736 false /* is_load */, is64bit); 737 if (pair) { 738 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, 739 false /* is_load */, is64bit); 740 } 741 } 742 } else { 743 if (!pair) { 744 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 745 displacement + LOWORD_OFFSET, r_src.GetReg()); 746 } else { 747 store = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 748 displacement + LOWORD_OFFSET, r_src.GetReg()); 749 store2 = NewLIR5(opcode, r_base.GetReg(), r_index.GetReg(), scale, 750 displacement + HIWORD_OFFSET, r_src_hi.GetReg()); 751 } 752 } 753 754 return store; 755} 756 757/* store value base base + scaled index. */ 758LIR* X86Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 759 int scale, OpSize size) { 760 return StoreBaseIndexedDisp(r_base, r_index, scale, 0, 761 r_src, RegStorage::InvalidReg(), size, INVALID_SREG); 762} 763 764LIR* X86Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, 765 RegStorage r_src, OpSize size) { 766 return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, r_src, 767 RegStorage::InvalidReg(), size, INVALID_SREG); 768} 769 770LIR* X86Mir2Lir::StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src) { 771 return StoreBaseIndexedDisp(r_base, RegStorage::InvalidReg(), 0, displacement, 772 r_src.GetLow(), r_src.GetHigh(), kLong, INVALID_SREG); 773} 774 775/* 776 * Copy a long value in Core registers to an XMM register 777 * 778 */ 779void X86Mir2Lir::OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg) { 780 NewLIR2(kX86MovdxrRR, fp_reg, low_reg); 781 int tmp_reg = AllocTempDouble().GetLowReg(); 782 NewLIR2(kX86MovdxrRR, tmp_reg, high_reg); 783 NewLIR2(kX86PunpckldqRR, fp_reg, tmp_reg); 784 FreeTemp(tmp_reg); 785} 786 787LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 788 int offset, int check_value, LIR* target) { 789 NewLIR3(IS_SIMM8(check_value) ? kX86Cmp32MI8 : kX86Cmp32MI, base_reg.GetReg(), offset, 790 check_value); 791 LIR* branch = OpCondBranch(cond, target); 792 return branch; 793} 794 795void X86Mir2Lir::AnalyzeMIR() { 796 // Assume we don't need a pointer to the base of the code. 797 cu_->NewTimingSplit("X86 MIR Analysis"); 798 store_method_addr_ = false; 799 800 // Walk the MIR looking for interesting items. 801 PreOrderDfsIterator iter(mir_graph_); 802 BasicBlock* curr_bb = iter.Next(); 803 while (curr_bb != NULL) { 804 AnalyzeBB(curr_bb); 805 curr_bb = iter.Next(); 806 } 807 808 // Did we need a pointer to the method code? 809 if (store_method_addr_) { 810 base_of_code_ = mir_graph_->GetNewCompilerTemp(kCompilerTempVR, false); 811 } else { 812 base_of_code_ = nullptr; 813 } 814} 815 816void X86Mir2Lir::AnalyzeBB(BasicBlock * bb) { 817 if (bb->block_type == kDead) { 818 // Ignore dead blocks 819 return; 820 } 821 822 for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) { 823 int opcode = mir->dalvikInsn.opcode; 824 if (opcode >= kMirOpFirst) { 825 AnalyzeExtendedMIR(opcode, bb, mir); 826 } else { 827 AnalyzeMIR(opcode, bb, mir); 828 } 829 } 830} 831 832 833void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { 834 switch (opcode) { 835 // Instructions referencing doubles. 836 case kMirOpFusedCmplDouble: 837 case kMirOpFusedCmpgDouble: 838 AnalyzeFPInstruction(opcode, bb, mir); 839 break; 840 default: 841 // Ignore the rest. 842 break; 843 } 844} 845 846void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { 847 // Looking for 848 // - Do we need a pointer to the code (used for packed switches and double lits)? 849 850 switch (opcode) { 851 // Instructions referencing doubles. 852 case Instruction::CMPL_DOUBLE: 853 case Instruction::CMPG_DOUBLE: 854 case Instruction::NEG_DOUBLE: 855 case Instruction::ADD_DOUBLE: 856 case Instruction::SUB_DOUBLE: 857 case Instruction::MUL_DOUBLE: 858 case Instruction::DIV_DOUBLE: 859 case Instruction::REM_DOUBLE: 860 case Instruction::ADD_DOUBLE_2ADDR: 861 case Instruction::SUB_DOUBLE_2ADDR: 862 case Instruction::MUL_DOUBLE_2ADDR: 863 case Instruction::DIV_DOUBLE_2ADDR: 864 case Instruction::REM_DOUBLE_2ADDR: 865 AnalyzeFPInstruction(opcode, bb, mir); 866 break; 867 868 // Packed switches and array fills need a pointer to the base of the method. 869 case Instruction::FILL_ARRAY_DATA: 870 case Instruction::PACKED_SWITCH: 871 store_method_addr_ = true; 872 break; 873 default: 874 // Other instructions are not interesting yet. 875 break; 876 } 877} 878 879void X86Mir2Lir::AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) { 880 // Look at all the uses, and see if they are double constants. 881 uint64_t attrs = mir_graph_->oat_data_flow_attributes_[opcode]; 882 int next_sreg = 0; 883 if (attrs & DF_UA) { 884 if (attrs & DF_A_WIDE) { 885 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 886 next_sreg += 2; 887 } else { 888 next_sreg++; 889 } 890 } 891 if (attrs & DF_UB) { 892 if (attrs & DF_B_WIDE) { 893 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 894 next_sreg += 2; 895 } else { 896 next_sreg++; 897 } 898 } 899 if (attrs & DF_UC) { 900 if (attrs & DF_C_WIDE) { 901 AnalyzeDoubleUse(mir_graph_->GetSrcWide(mir, next_sreg)); 902 } 903 } 904} 905 906void X86Mir2Lir::AnalyzeDoubleUse(RegLocation use) { 907 // If this is a double literal, we will want it in the literal pool. 908 if (use.is_const) { 909 store_method_addr_ = true; 910 } 911} 912 913} // namespace art 914