15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Copyright (c) 2012 The Chromium Authors. All rights reserved. 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Use of this source code is governed by a BSD-style license that can be 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// found in the LICENSE file. 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "base/cpu.h" 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "build/build_config.h" 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "testing/gtest/include/gtest/gtest.h" 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Tests whether we can run extended instructions represented by the CPU 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// information. This test actually executes some extended instructions (such as 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// MMX, SSE, etc.) supported by the CPU and sees we can run them without 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// "undefined instruction" exceptions. That is, this test succeeds when this 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// test finishes without a crash. 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)TEST(CPU, RunExtendedInstructions) { 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#if defined(ARCH_CPU_X86_FAMILY) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Retrieve the CPU information. 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) base::CPU cpu; 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// TODO(jschuh): crbug.com/168866 Find a way to enable this on Win64. 212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#if defined(OS_WIN) && !defined(_M_X64) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ASSERT_TRUE(cpu.has_mmx()); 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an MMX instruction. 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm emms; 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse()) { 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE instruction. 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm xorps xmm0, xmm0; 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse2()) { 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 2 instruction. 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm psrldq xmm0, 0; 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse3()) { 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 3 instruction. 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm addsubpd xmm0, xmm0; 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_ssse3()) { 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute a Supplimental SSE 3 instruction. 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm psignb xmm0, xmm0; 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse41()) { 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 4.1 instruction. 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm pmuldq xmm0, xmm0; 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse42()) { 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 4.2 instruction. 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm crc32 eax, eax; 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#elif defined(OS_POSIX) && defined(__x86_64__) 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ASSERT_TRUE(cpu.has_mmx()); 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an MMX instruction. 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("emms\n" : : : "mm0"); 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse()) { 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE instruction. 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0"); 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse2()) { 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 2 instruction. 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0"); 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse3()) { 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 3 instruction. 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0"); 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_ssse3()) { 785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute a Supplimental SSE 3 instruction. 795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0"); 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse41()) { 835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 4.1 instruction. 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0"); 855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (cpu.has_sse42()) { 885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Execute an SSE 4.2 instruction. 895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax"); 905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 94