1# Copyright (c) 2014, Google Inc.
2#
3# Permission to use, copy, modify, and/or distribute this software for any
4# purpose with or without fee is hereby granted, provided that the above
5# copyright notice and this permission notice appear in all copies.
6#
7# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14
15# This file contains a pre-compiled version of chacha_vec.c for ARM. This is
16# needed to support switching on NEON code at runtime. If the whole of OpenSSL
17# were to be compiled with the needed flags to build chacha_vec.c, then it
18# wouldn't be possible to run on non-NEON systems.
19#
20# This file was generated by:
21#
22#     /opt/gcc-linaro-arm-linux-gnueabihf-4.7-2012.10-20121022_linux/bin/arm-linux-gnueabihf-gcc -O3 -mcpu=cortex-a8 -mfpu=neon -S chacha_vec.c -I ../../include -fpic -o chacha_vec_arm.S
23
24#if !defined(OPENSSL_NO_ASM)
25
26	.syntax unified
27	.cpu cortex-a8
28	.eabi_attribute 27, 3
29
30# EABI attribute 28 sets whether VFP register arguments were used to build this
31# file. If object files are inconsistent on this point, the linker will refuse
32# to link them. Thus we report whatever the compiler expects since we don't use
33# VFP arguments.
34
35#if defined(__ARM_PCS_VFP)
36	.eabi_attribute 28, 1
37#else
38	.eabi_attribute 28, 0
39#endif
40
41	.fpu neon
42	.eabi_attribute 20, 1
43	.eabi_attribute 21, 1
44	.eabi_attribute 23, 3
45	.eabi_attribute 24, 1
46	.eabi_attribute 25, 1
47	.eabi_attribute 26, 2
48	.eabi_attribute 30, 2
49	.eabi_attribute 34, 1
50	.eabi_attribute 18, 4
51	.thumb
52	.file	"chacha_vec.c"
53	.text
54	.align	2
55	.global	CRYPTO_chacha_20_neon
56	.hidden	CRYPTO_chacha_20_neon
57	.thumb
58	.thumb_func
59	.type	CRYPTO_chacha_20_neon, %function
60CRYPTO_chacha_20_neon:
61	@ args = 8, pretend = 0, frame = 304
62	@ frame_needed = 1, uses_anonymous_args = 0
63	@ link register save eliminated.
64	push	{r4, r5, r6, r7, r8, r9, sl, fp}
65	fstmfdd	sp!, {d8, d9, d10, d11, d12, d13, d14, d15}
66	sub	sp, sp, #304
67	add	r7, sp, #0
68	movw	ip, #43691
69	movt	ip, 43690
70	str	r2, [r7, #196]
71	sub	sp, sp, #96
72	ldr	r4, [r7, #196]
73	ldr	r6, [r7, #400]
74	ldr	r2, .L38+16
75	umull	r4, ip, ip, r4
76	ldr	r6, [r6, #0]
77	ldr	r8, [r7, #400]
78.LPIC24:
79	add	r2, pc
80	add	r4, sp, #15
81	str	r3, [r7, #244]
82	str	r6, [r7, #176]
83	bic	r4, r4, #15
84	str	r0, [r7, #188]
85	str	r4, [r7, #200]
86	lsrs	ip, ip, #7
87	str	r1, [r7, #184]
88	ldmia	r2, {r0, r1, r2, r3}
89	ldr	r4, [r8, #4]
90	ldr	r5, [r7, #244]
91	vld1.64	{d24-d25}, [r5:64]
92	vldr	d26, [r5, #16]
93	vldr	d27, [r5, #24]
94	ldr	r9, [r7, #200]
95	ldr	r8, [r7, #404]
96	ldr	r5, [r7, #176]
97	add	r6, r9, #64
98	str	r4, [r7, #300]
99	mov	r4, #0
100	str	r8, [r7, #288]
101	str	r5, [r7, #296]
102	str	r4, [r7, #292]
103	stmia	r6, {r0, r1, r2, r3}
104	vldr	d22, [r9, #64]
105	vldr	d23, [r9, #72]
106	vldr	d20, [r7, #288]
107	vldr	d21, [r7, #296]
108	str	ip, [r7, #192]
109	beq	.L20
110	lsl	r6, ip, #1
111	ldr	r1, [r9, #68]
112	add	r3, r6, ip
113	str	r6, [r7, #180]
114	ldr	r2, [r9, #72]
115	add	r8, r8, #2
116	ldr	r5, [r9, #76]
117	vldr	d18, .L38
118	vldr	d19, .L38+8
119	str	r4, [r7, #240]
120	ldr	r6, [r7, #184]
121	ldr	r4, [r7, #188]
122	str	r0, [r7, #224]
123	str	r1, [r7, #220]
124	str	r8, [r7, #208]
125	str	r2, [r7, #216]
126	str	r3, [r7, #204]
127	str	r5, [r7, #212]
128	str	r6, [r7, #252]
129	str	r4, [r7, #248]
130.L4:
131	ldr	r2, [r7, #244]
132	add	r9, r7, #216
133	ldr	r3, [r7, #244]
134	vadd.i32	q8, q10, q9
135	ldr	r6, [r7, #208]
136	vmov	q15, q13  @ v4si
137	ldr	r5, [r7, #240]
138	vmov	q3, q12  @ v4si
139	ldr	r4, [r7, #244]
140	vmov	q2, q11  @ v4si
141	adds	r5, r5, r6
142	ldr	r2, [r2, #8]
143	ldr	r6, [r7, #400]
144	vmov	q5, q10  @ v4si
145	ldr	r3, [r3, #12]
146	vmov	q1, q13  @ v4si
147	ldr	r0, [r7, #244]
148	vmov	q0, q12  @ v4si
149	ldr	r1, [r7, #244]
150	vmov	q4, q11  @ v4si
151	ldmia	r9, {r9, sl, fp}
152	str	r5, [r7, #228]
153	ldr	r5, [r4, #24]
154	ldr	r0, [r0, #0]
155	ldr	r1, [r1, #4]
156	str	r2, [r7, #264]
157	str	r3, [r7, #236]
158	ldr	r2, [r6, #4]
159	ldr	r3, [r4, #28]
160	str	r5, [r7, #280]
161	ldr	r5, [r6, #0]
162	movs	r6, #0
163	ldr	ip, [r7, #228]
164	ldr	r8, [r7, #212]
165	str	r0, [r7, #232]
166	str	r1, [r7, #268]
167	ldr	r0, [r4, #16]
168	ldr	r1, [r4, #20]
169	movs	r4, #10
170	str	r2, [r7, #24]
171	str	r3, [r7, #284]
172	str	r4, [r7, #256]
173	ldr	r2, [r7, #264]
174	str	r9, [r7, #276]
175	mov	r9, r6
176	ldr	r6, [r7, #280]
177	str	r8, [r7, #260]
178	mov	r8, sl
179	str	r1, [r7, #272]
180	mov	sl, ip
181	str	r6, [r7, #264]
182	mov	r6, r5
183	ldr	r3, [r7, #236]
184	mov	r5, r0
185	ldr	ip, [r7, #24]
186	ldr	r1, [r7, #268]
187	ldr	r0, [r7, #232]
188	b	.L39
189.L40:
190	.align	3
191.L38:
192	.word	1
193	.word	0
194	.word	0
195	.word	0
196	.word	.LANCHOR0-(.LPIC24+4)
197.L39:
198.L3:
199	vadd.i32	q4, q4, q0
200	add	r8, r8, r1
201	vadd.i32	q2, q2, q3
202	str	r8, [r7, #268]
203	veor	q5, q5, q4
204	ldr	r8, [r7, #276]
205	veor	q8, q8, q2
206	add	fp, fp, r0
207	str	fp, [r7, #280]
208	add	r8, r8, r2
209	vrev32.16	q5, q5
210	str	r8, [r7, #276]
211	vrev32.16	q8, q8
212	vadd.i32	q1, q1, q5
213	vadd.i32	q15, q15, q8
214	ldr	r8, [r7, #280]
215	veor	q0, q1, q0
216	ldr	r4, [r7, #260]
217	veor	q3, q15, q3
218	eor	sl, sl, r8
219	ldr	r8, [r7, #276]
220	add	fp, r4, r3
221	vshl.i32	q7, q0, #12
222	ldr	r4, [r7, #268]
223	vshl.i32	q6, q3, #12
224	eor	r6, r6, r8
225	eor	r9, r9, r4
226	ldr	r4, [r7, #272]
227	vsri.32	q7, q0, #20
228	ror	r8, r6, #16
229	ldr	r6, [r7, #264]
230	eor	ip, ip, fp
231	vsri.32	q6, q3, #20
232	ror	sl, sl, #16
233	ror	r9, r9, #16
234	add	r5, r5, sl
235	vadd.i32	q4, q4, q7
236	str	r5, [r7, #236]
237	vadd.i32	q2, q2, q6
238	add	r5, r4, r9
239	add	r4, r6, r8
240	ldr	r6, [r7, #284]
241	ror	ip, ip, #16
242	veor	q5, q4, q5
243	veor	q8, q2, q8
244	add	r6, r6, ip
245	str	r6, [r7, #264]
246	eors	r1, r1, r5
247	ldr	r6, [r7, #236]
248	vshl.i32	q3, q5, #8
249	vshl.i32	q14, q8, #8
250	eors	r2, r2, r4
251	eors	r0, r0, r6
252	ldr	r6, [r7, #264]
253	vsri.32	q3, q5, #24
254	ror	r1, r1, #20
255	eors	r3, r3, r6
256	ldr	r6, [r7, #280]
257	ror	r0, r0, #20
258	vsri.32	q14, q8, #24
259	adds	r6, r0, r6
260	str	r6, [r7, #284]
261	ldr	r6, [r7, #268]
262	vadd.i32	q1, q1, q3
263	vadd.i32	q15, q15, q14
264	ror	r2, r2, #20
265	adds	r6, r1, r6
266	str	r6, [r7, #260]
267	ldr	r6, [r7, #276]
268	veor	q6, q15, q6
269	veor	q7, q1, q7
270	ror	r3, r3, #20
271	adds	r6, r2, r6
272	str	r6, [r7, #280]
273	ldr	r6, [r7, #284]
274	vshl.i32	q0, q6, #7
275	vshl.i32	q5, q7, #7
276	add	fp, r3, fp
277	eor	sl, r6, sl
278	ldr	r6, [r7, #260]
279	eor	ip, fp, ip
280	vsri.32	q0, q6, #25
281	eor	r9, r6, r9
282	ldr	r6, [r7, #280]
283	ror	sl, sl, #24
284	vsri.32	q5, q7, #25
285	eor	r8, r6, r8
286	ldr	r6, [r7, #236]
287	ror	r9, r9, #24
288	ror	ip, ip, #24
289	add	r6, sl, r6
290	str	r6, [r7, #276]
291	ldr	r6, [r7, #264]
292	add	r5, r9, r5
293	str	r5, [r7, #272]
294	vext.32	q5, q5, q5, #1
295	add	r5, ip, r6
296	ldr	r6, [r7, #276]
297	vext.32	q0, q0, q0, #1
298	vadd.i32	q4, q4, q5
299	eors	r0, r0, r6
300	ldr	r6, [r7, #272]
301	vadd.i32	q2, q2, q0
302	vext.32	q3, q3, q3, #3
303	ror	r8, r8, #24
304	eors	r1, r1, r6
305	vext.32	q14, q14, q14, #3
306	add	r4, r8, r4
307	ldr	r6, [r7, #284]
308	veor	q3, q4, q3
309	veor	q14, q2, q14
310	eors	r2, r2, r4
311	ror	r1, r1, #25
312	vext.32	q1, q1, q1, #2
313	adds	r6, r1, r6
314	str	r6, [r7, #284]
315	vext.32	q15, q15, q15, #2
316	ldr	r6, [r7, #260]
317	eors	r3, r3, r5
318	ror	r2, r2, #25
319	vrev32.16	q8, q14
320	adds	r6, r2, r6
321	vrev32.16	q3, q3
322	str	r6, [r7, #268]
323	vadd.i32	q1, q1, q3
324	ldr	r6, [r7, #280]
325	vadd.i32	q15, q15, q8
326	ror	r3, r3, #25
327	veor	q5, q1, q5
328	adds	r6, r3, r6
329	veor	q0, q15, q0
330	str	r6, [r7, #264]
331	ldr	r6, [r7, #268]
332	ror	r0, r0, #25
333	add	fp, r0, fp
334	vshl.i32	q6, q5, #12
335	eor	sl, r6, sl
336	ldr	r6, [r7, #284]
337	vshl.i32	q14, q0, #12
338	eor	r8, fp, r8
339	eor	ip, r6, ip
340	ldr	r6, [r7, #264]
341	vsri.32	q6, q5, #20
342	ror	sl, sl, #16
343	eor	r9, r6, r9
344	ror	r6, r8, #16
345	vsri.32	q14, q0, #20
346	ldr	r8, [r7, #272]
347	ror	ip, ip, #16
348	add	r5, sl, r5
349	add	r8, r6, r8
350	add	r4, ip, r4
351	str	r4, [r7, #236]
352	eor	r0, r8, r0
353	str	r5, [r7, #280]
354	vadd.i32	q4, q4, q6
355	ldr	r5, [r7, #236]
356	vadd.i32	q2, q2, q14
357	ldr	r4, [r7, #276]
358	ror	r0, r0, #20
359	veor	q3, q4, q3
360	eors	r1, r1, r5
361	veor	q0, q2, q8
362	str	r8, [r7, #272]
363	str	r0, [r7, #24]
364	add	fp, r0, fp
365	ldr	r8, [r7, #280]
366	ror	r9, r9, #16
367	ldr	r0, [r7, #284]
368	add	r4, r9, r4
369	str	fp, [r7, #260]
370	ror	r1, r1, #20
371	add	fp, r1, r0
372	eor	r2, r8, r2
373	ldr	r0, [r7, #260]
374	eors	r3, r3, r4
375	vshl.i32	q5, q3, #8
376	str	r4, [r7, #232]
377	vshl.i32	q8, q0, #8
378	ldr	r4, [r7, #268]
379	ldr	r5, [r7, #264]
380	ror	r2, r2, #20
381	ror	r3, r3, #20
382	eors	r6, r6, r0
383	adds	r5, r3, r5
384	add	r8, r2, r4
385	vsri.32	q5, q3, #24
386	ldr	r4, [r7, #272]
387	eor	r9, r5, r9
388	eor	ip, fp, ip
389	vsri.32	q8, q0, #24
390	eor	sl, r8, sl
391	ror	r6, r6, #24
392	ldr	r0, [r7, #280]
393	str	r5, [r7, #276]
394	adds	r4, r6, r4
395	ldr	r5, [r7, #236]
396	vadd.i32	q1, q1, q5
397	str	r4, [r7, #272]
398	vadd.i32	q15, q15, q8
399	ldr	r4, [r7, #232]
400	ror	ip, ip, #24
401	ror	sl, sl, #24
402	ror	r9, r9, #24
403	add	r5, ip, r5
404	add	r0, sl, r0
405	str	r5, [r7, #264]
406	add	r5, r9, r4
407	str	r0, [r7, #284]
408	veor	q6, q1, q6
409	ldr	r4, [r7, #24]
410	veor	q14, q15, q14
411	ldr	r0, [r7, #272]
412	eors	r3, r3, r5
413	vshl.i32	q0, q6, #7
414	vext.32	q1, q1, q1, #2
415	eors	r0, r0, r4
416	ldr	r4, [r7, #284]
417	str	r0, [r7, #280]
418	vshl.i32	q3, q14, #7
419	eors	r2, r2, r4
420	ldr	r4, [r7, #280]
421	ldr	r0, [r7, #264]
422	vsri.32	q0, q6, #25
423	ror	r2, r2, #25
424	ror	r3, r3, #25
425	eors	r1, r1, r0
426	vsri.32	q3, q14, #25
427	ror	r0, r4, #25
428	ldr	r4, [r7, #256]
429	ror	r1, r1, #25
430	vext.32	q5, q5, q5, #1
431	subs	r4, r4, #1
432	str	r4, [r7, #256]
433	vext.32	q15, q15, q15, #2
434	vext.32	q8, q8, q8, #1
435	vext.32	q0, q0, q0, #3
436	vext.32	q3, q3, q3, #3
437	bne	.L3
438	ldr	r4, [r7, #264]
439	vadd.i32	q14, q10, q9
440	str	r2, [r7, #264]
441	vadd.i32	q10, q10, q5
442	ldr	r2, [r7, #252]
443	vld1.64	{d12-d13}, [r2:64]
444	ldr	r2, [r7, #220]
445	vadd.i32	q4, q11, q4
446	str	ip, [r7, #24]
447	mov	ip, sl
448	mov	sl, r8
449	ldr	r8, [r7, #260]
450	add	sl, sl, r2
451	ldr	r2, [r7, #212]
452	str	r4, [r7, #280]
453	vadd.i32	q0, q12, q0
454	ldr	r4, [r7, #224]
455	add	r8, r8, r2
456	ldr	r2, [r7, #240]
457	vadd.i32	q1, q13, q1
458	str	r0, [r7, #232]
459	add	fp, fp, r4
460	mov	r0, r5
461	ldr	r4, [r7, #216]
462	mov	r5, r6
463	mov	r6, r9
464	ldr	r9, [r7, #276]
465	adds	r2, r2, #3
466	str	r2, [r7, #240]
467	vadd.i32	q2, q11, q2
468	ldr	r2, [r7, #252]
469	add	r9, r9, r4
470	vadd.i32	q3, q12, q3
471	ldr	r4, [r7, #228]
472	vadd.i32	q15, q13, q15
473	str	r1, [r7, #268]
474	vadd.i32	q8, q14, q8
475	str	r3, [r7, #236]
476	veor	q4, q4, q6
477	ldr	r3, [r7, #284]
478	ldr	r1, [r7, #272]
479	add	ip, r4, ip
480	ldr	r4, [r7, #248]
481	vst1.64	{d8-d9}, [r4:64]
482	vldr	d8, [r2, #16]
483	vldr	d9, [r2, #24]
484	veor	q0, q0, q4
485	vstr	d0, [r4, #16]
486	vstr	d1, [r4, #24]
487	vldr	d0, [r2, #32]
488	vldr	d1, [r2, #40]
489	veor	q1, q1, q0
490	vstr	d2, [r4, #32]
491	vstr	d3, [r4, #40]
492	vldr	d2, [r2, #48]
493	vldr	d3, [r2, #56]
494	veor	q10, q10, q1
495	vstr	d20, [r4, #48]
496	vstr	d21, [r4, #56]
497	vldr	d8, [r2, #64]
498	vldr	d9, [r2, #72]
499	veor	q2, q2, q4
500	vstr	d4, [r4, #64]
501	vstr	d5, [r4, #72]
502	vldr	d10, [r2, #80]
503	vldr	d11, [r2, #88]
504	veor	q3, q3, q5
505	vstr	d6, [r4, #80]
506	vstr	d7, [r4, #88]
507	vldr	d12, [r2, #96]
508	vldr	d13, [r2, #104]
509	veor	q15, q15, q6
510	vstr	d30, [r4, #96]
511	vstr	d31, [r4, #104]
512	vldr	d20, [r2, #112]
513	vldr	d21, [r2, #120]
514	veor	q8, q8, q10
515	vstr	d16, [r4, #112]
516	vstr	d17, [r4, #120]
517	ldr	r4, [r2, #128]
518	ldr	r2, [r7, #248]
519	vadd.i32	q10, q14, q9
520	eor	r4, fp, r4
521	vadd.i32	q10, q10, q9
522	str	r4, [r2, #128]
523	ldr	r4, [r7, #252]
524	ldr	r2, [r4, #132]
525	eor	r2, sl, r2
526	ldr	sl, [r7, #248]
527	str	r2, [sl, #132]
528	ldr	r2, [r4, #136]
529	eor	r2, r9, r2
530	str	r2, [sl, #136]
531	ldr	r2, [r4, #140]
532	eor	r2, r8, r2
533	str	r2, [sl, #140]
534	ldr	r2, [r7, #244]
535	ldr	r4, [r4, #144]
536	ldr	r2, [r2, #0]
537	str	r4, [r7, #44]
538	ldr	r4, [r7, #232]
539	add	r8, r4, r2
540	ldr	r2, [r7, #44]
541	ldr	r4, [r7, #244]
542	eor	r8, r8, r2
543	ldr	r2, [r7, #252]
544	str	r8, [sl, #144]
545	ldr	r4, [r4, #4]
546	ldr	r2, [r2, #148]
547	str	r2, [r7, #40]
548	ldr	r2, [r7, #268]
549	add	r8, r2, r4
550	ldr	r4, [r7, #40]
551	ldr	r2, [r7, #244]
552	eor	r8, r8, r4
553	ldr	r4, [r7, #252]
554	str	r8, [sl, #148]
555	ldr	r2, [r2, #8]
556	ldr	r4, [r4, #152]
557	str	r4, [r7, #36]
558	ldr	r4, [r7, #264]
559	add	r8, r4, r2
560	ldr	r2, [r7, #36]
561	eor	r8, r8, r2
562	str	r8, [sl, #152]
563	ldr	r2, [r7, #252]
564	ldr	r4, [r7, #244]
565	ldr	r2, [r2, #156]
566	ldr	r4, [r4, #12]
567	str	r2, [r7, #32]
568	ldr	r2, [r7, #236]
569	add	r8, r2, r4
570	ldr	r4, [r7, #32]
571	ldr	r2, [r7, #252]
572	eor	r8, r8, r4
573	str	r8, [sl, #156]
574	ldr	r8, [r7, #244]
575	ldr	r2, [r2, #160]
576	ldr	r4, [r8, #16]
577	adds	r0, r0, r4
578	ldr	r4, [r7, #252]
579	eors	r0, r0, r2
580	str	r0, [sl, #160]
581	ldr	r0, [r8, #20]
582	ldr	r2, [r4, #164]
583	adds	r1, r1, r0
584	ldr	r0, [r7, #280]
585	eors	r1, r1, r2
586	str	r1, [sl, #164]
587	ldr	r2, [r8, #24]
588	ldr	r1, [r4, #168]
589	adds	r2, r0, r2
590	eors	r2, r2, r1
591	str	r2, [sl, #168]
592	ldr	r1, [r8, #28]
593	ldr	r2, [r4, #172]
594	adds	r3, r3, r1
595	eors	r3, r3, r2
596	str	r3, [sl, #172]
597	ldr	r3, [r4, #176]
598	eor	r3, ip, r3
599	str	r3, [sl, #176]
600	ldr	r3, [r4, #180]
601	ldr	r4, [r7, #400]
602	eors	r6, r6, r3
603	str	r6, [sl, #180]
604	ldr	r6, [r7, #252]
605	ldr	r2, [r4, #0]
606	ldr	r3, [r6, #184]
607	adds	r5, r5, r2
608	eors	r5, r5, r3
609	str	r5, [sl, #184]
610	ldr	r2, [r6, #188]
611	adds	r6, r6, #192
612	ldr	r3, [r4, #4]
613	str	r6, [r7, #252]
614	ldr	r0, [r7, #24]
615	ldr	r1, [r7, #240]
616	adds	r4, r0, r3
617	eors	r4, r4, r2
618	ldr	r2, [r7, #204]
619	str	r4, [sl, #188]
620	add	sl, sl, #192
621	cmp	r1, r2
622	str	sl, [r7, #248]
623	bne	.L4
624	ldr	r4, [r7, #192]
625	ldr	r3, [r7, #180]
626	ldr	r6, [r7, #188]
627	adds	r5, r3, r4
628	ldr	r8, [r7, #184]
629	lsls	r5, r5, #6
630	adds	r4, r6, r5
631	add	r5, r8, r5
632.L2:
633	ldr	r9, [r7, #196]
634	movw	r3, #43691
635	movt	r3, 43690
636	ldr	sl, [r7, #196]
637	umull	r9, r3, r3, r9
638	lsrs	r3, r3, #7
639	add	r3, r3, r3, lsl #1
640	sub	r3, sl, r3, lsl #6
641	lsrs	r6, r3, #6
642	beq	.L5
643	add	r1, r5, #16
644	add	r2, r4, #16
645	mov	r0, r6
646	vldr	d30, .L41
647	vldr	d31, .L41+8
648.L6:
649	vmov	q8, q10  @ v4si
650	movs	r3, #10
651	vmov	q1, q13  @ v4si
652	vmov	q14, q12  @ v4si
653	vmov	q3, q11  @ v4si
654.L7:
655	vadd.i32	q3, q3, q14
656	subs	r3, r3, #1
657	veor	q2, q8, q3
658	vrev32.16	q2, q2
659	vadd.i32	q8, q1, q2
660	veor	q9, q8, q14
661	vshl.i32	q14, q9, #12
662	vsri.32	q14, q9, #20
663	vadd.i32	q3, q3, q14
664	veor	q2, q3, q2
665	vshl.i32	q9, q2, #8
666	vsri.32	q9, q2, #24
667	vadd.i32	q8, q8, q9
668	vext.32	q9, q9, q9, #3
669	veor	q14, q8, q14
670	vext.32	q1, q8, q8, #2
671	vshl.i32	q8, q14, #7
672	vsri.32	q8, q14, #25
673	vext.32	q8, q8, q8, #1
674	vadd.i32	q3, q3, q8
675	veor	q2, q3, q9
676	vrev32.16	q2, q2
677	vadd.i32	q9, q1, q2
678	veor	q8, q9, q8
679	vshl.i32	q14, q8, #12
680	vsri.32	q14, q8, #20
681	vadd.i32	q3, q3, q14
682	veor	q2, q3, q2
683	vshl.i32	q8, q2, #8
684	vsri.32	q8, q2, #24
685	vadd.i32	q9, q9, q8
686	vext.32	q8, q8, q8, #1
687	veor	q14, q9, q14
688	vext.32	q1, q9, q9, #2
689	vshl.i32	q9, q14, #7
690	vsri.32	q9, q14, #25
691	vext.32	q14, q9, q9, #3
692	bne	.L7
693	vadd.i32	q8, q10, q8
694	subs	r0, r0, #1
695	vadd.i32	q3, q11, q3
696	vldr	d0, [r1, #-16]
697	vldr	d1, [r1, #-8]
698	vadd.i32	q14, q12, q14
699	vadd.i32	q1, q13, q1
700	veor	q3, q3, q0
701	vstr	d6, [r2, #-16]
702	vstr	d7, [r2, #-8]
703	vadd.i32	q10, q10, q15
704	vld1.64	{d8-d9}, [r1:64]
705	veor	q14, q14, q4
706	vst1.64	{d28-d29}, [r2:64]
707	vldr	d10, [r1, #16]
708	vldr	d11, [r1, #24]
709	veor	q1, q1, q5
710	vstr	d2, [r2, #16]
711	vstr	d3, [r2, #24]
712	vldr	d18, [r1, #32]
713	vldr	d19, [r1, #40]
714	add	r1, r1, #64
715	veor	q8, q8, q9
716	vstr	d16, [r2, #32]
717	vstr	d17, [r2, #40]
718	add	r2, r2, #64
719	bne	.L6
720	lsls	r6, r6, #6
721	adds	r4, r4, r6
722	adds	r5, r5, r6
723.L5:
724	ldr	r6, [r7, #196]
725	ands	ip, r6, #63
726	beq	.L1
727	vmov	q8, q10  @ v4si
728	movs	r3, #10
729	vmov	q14, q13  @ v4si
730	vmov	q9, q12  @ v4si
731	vmov	q15, q11  @ v4si
732.L10:
733	vadd.i32	q15, q15, q9
734	subs	r3, r3, #1
735	veor	q8, q8, q15
736	vrev32.16	q8, q8
737	vadd.i32	q3, q14, q8
738	veor	q9, q3, q9
739	vshl.i32	q14, q9, #12
740	vsri.32	q14, q9, #20
741	vadd.i32	q15, q15, q14
742	veor	q9, q15, q8
743	vshl.i32	q8, q9, #8
744	vsri.32	q8, q9, #24
745	vadd.i32	q9, q3, q8
746	vext.32	q8, q8, q8, #3
747	veor	q2, q9, q14
748	vext.32	q14, q9, q9, #2
749	vshl.i32	q9, q2, #7
750	vsri.32	q9, q2, #25
751	vext.32	q9, q9, q9, #1
752	vadd.i32	q15, q15, q9
753	veor	q3, q15, q8
754	vrev32.16	q3, q3
755	vadd.i32	q14, q14, q3
756	veor	q8, q14, q9
757	vshl.i32	q9, q8, #12
758	vsri.32	q9, q8, #20
759	vadd.i32	q15, q15, q9
760	veor	q3, q15, q3
761	vshl.i32	q8, q3, #8
762	vsri.32	q8, q3, #24
763	vadd.i32	q14, q14, q8
764	vext.32	q8, q8, q8, #1
765	veor	q3, q14, q9
766	vext.32	q14, q14, q14, #2
767	vshl.i32	q9, q3, #7
768	vsri.32	q9, q3, #25
769	vext.32	q9, q9, q9, #3
770	bne	.L10
771	cmp	ip, #15
772	vadd.i32	q11, q11, q15
773	bhi	.L37
774	ldr	r9, [r7, #200]
775	vst1.64	{d22-d23}, [r9:128]
776.L14:
777	ldr	sl, [r7, #196]
778	and	r3, sl, #48
779	cmp	ip, r3
780	bls	.L1
781	adds	r0, r5, r3
782	adds	r1, r4, r3
783	add	r2, r0, #16
784	add	r6, r1, #16
785	cmp	r1, r2
786	it	cc
787	cmpcc	r0, r6
788	rsb	r9, r3, ip
789	ite	cc
790	movcc	r2, #0
791	movcs	r2, #1
792	cmp	r9, #15
793	ite	ls
794	movls	r2, #0
795	andhi	r2, r2, #1
796	lsr	r8, r9, #4
797	eor	r2, r2, #1
798	cmp	r8, #0
799	it	eq
800	orreq	r2, r2, #1
801	lsl	sl, r8, #4
802	cbnz	r2, .L35
803	ldr	fp, [r7, #200]
804	add	r6, fp, r3
805.L17:
806	vld1.8	{q8}, [r0]!
807	adds	r2, r2, #1
808	cmp	r8, r2
809	vld1.8	{q9}, [r6]!
810	veor	q8, q9, q8
811	vst1.8	{q8}, [r1]!
812	bhi	.L17
813	cmp	r9, sl
814	add	r3, r3, sl
815	beq	.L1
816.L35:
817	ldr	r0, [r7, #200]
818.L25:
819	ldrb	r2, [r5, r3]	@ zero_extendqisi2
820	ldrb	r1, [r3, r0]	@ zero_extendqisi2
821	eors	r2, r2, r1
822	strb	r2, [r4, r3]
823	adds	r3, r3, #1
824	cmp	ip, r3
825	bhi	.L25
826.L1:
827	add	r7, r7, #304
828	mov	sp, r7
829	fldmfdd	sp!, {d8, d9, d10, d11, d12, d13, d14, d15}
830	pop	{r4, r5, r6, r7, r8, r9, sl, fp}
831	bx	lr
832.L37:
833	cmp	ip, #31
834	vld1.64	{d0-d1}, [r5:64]
835	vadd.i32	q9, q12, q9
836	veor	q11, q11, q0
837	vst1.64	{d22-d23}, [r4:64]
838	bls	.L12
839	cmp	ip, #47
840	vldr	d2, [r5, #16]
841	vldr	d3, [r5, #24]
842	vadd.i32	q13, q13, q14
843	veor	q9, q9, q1
844	vstr	d18, [r4, #16]
845	vstr	d19, [r4, #24]
846	bls	.L13
847	vadd.i32	q8, q8, q10
848	vldr	d0, [r5, #32]
849	vldr	d1, [r5, #40]
850	ldr	r6, [r7, #200]
851	vstr	d16, [r6, #48]
852	vstr	d17, [r6, #56]
853	veor	q8, q13, q0
854	vstr	d16, [r4, #32]
855	vstr	d17, [r4, #40]
856	b	.L14
857.L12:
858	ldr	r8, [r7, #200]
859	vstr	d18, [r8, #16]
860	vstr	d19, [r8, #24]
861	b	.L14
862.L20:
863	ldr	r5, [r7, #184]
864	ldr	r4, [r7, #188]
865	b	.L2
866.L13:
867	ldr	r6, [r7, #200]
868	vstr	d26, [r6, #32]
869	vstr	d27, [r6, #40]
870	b	.L14
871.L42:
872	.align	3
873.L41:
874	.word	1
875	.word	0
876	.word	0
877	.word	0
878	.size	CRYPTO_chacha_20_neon, .-CRYPTO_chacha_20_neon
879	.section	.rodata
880	.align	3
881.LANCHOR0 = . + 0
882.LC0:
883	.word	1634760805
884	.word	857760878
885	.word	2036477234
886	.word	1797285236
887	.ident	"GCC: (crosstool-NG linaro-1.13.1-4.7-2012.10-20121022 - Linaro GCC 2012.10) 4.7.3 20121001 (prerelease)"
888	.section	.note.GNU-stack,"",%progbits
889
890#endif  /* !OPENSSL_NO_ASM */
891