1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "pipe/p_context.h" 24#include "pipe/p_state.h" 25#include "util/u_inlines.h" 26#include "util/u_format.h" 27#include "translate/translate.h" 28 29#include "nv50_context.h" 30#include "nv50_resource.h" 31 32#include "nv50_3d.xml.h" 33 34void 35nv50_vertex_state_delete(struct pipe_context *pipe, 36 void *hwcso) 37{ 38 struct nv50_vertex_stateobj *so = hwcso; 39 40 if (so->translate) 41 so->translate->release(so->translate); 42 FREE(hwcso); 43} 44 45void * 46nv50_vertex_state_create(struct pipe_context *pipe, 47 unsigned num_elements, 48 const struct pipe_vertex_element *elements) 49{ 50 struct nv50_vertex_stateobj *so; 51 struct translate_key transkey; 52 unsigned i; 53 54 so = MALLOC(sizeof(*so) + 55 num_elements * sizeof(struct nv50_vertex_element)); 56 if (!so) 57 return NULL; 58 so->num_elements = num_elements; 59 so->instance_elts = 0; 60 so->instance_bufs = 0; 61 so->need_conversion = FALSE; 62 63 memset(so->vb_access_size, 0, sizeof(so->vb_access_size)); 64 65 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i) 66 so->min_instance_div[i] = 0xffffffff; 67 68 transkey.nr_elements = 0; 69 transkey.output_stride = 0; 70 71 for (i = 0; i < num_elements; ++i) { 72 const struct pipe_vertex_element *ve = &elements[i]; 73 const unsigned vbi = ve->vertex_buffer_index; 74 unsigned size; 75 enum pipe_format fmt = ve->src_format; 76 77 so->element[i].pipe = elements[i]; 78 so->element[i].state = nv50_format_table[fmt].vtx; 79 80 if (!so->element[i].state) { 81 switch (util_format_get_nr_components(fmt)) { 82 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break; 83 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break; 84 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break; 85 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break; 86 default: 87 assert(0); 88 return NULL; 89 } 90 so->element[i].state = nv50_format_table[fmt].vtx; 91 so->need_conversion = TRUE; 92 } 93 so->element[i].state |= i; 94 95 size = util_format_get_blocksize(fmt); 96 if (so->vb_access_size[vbi] < (ve->src_offset + size)) 97 so->vb_access_size[vbi] = ve->src_offset + size; 98 99 if (1) { 100 unsigned j = transkey.nr_elements++; 101 102 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL; 103 transkey.element[j].input_format = ve->src_format; 104 transkey.element[j].input_buffer = vbi; 105 transkey.element[j].input_offset = ve->src_offset; 106 transkey.element[j].instance_divisor = ve->instance_divisor; 107 108 transkey.element[j].output_format = fmt; 109 transkey.element[j].output_offset = transkey.output_stride; 110 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3; 111 112 if (unlikely(ve->instance_divisor)) { 113 so->instance_elts |= 1 << i; 114 so->instance_bufs |= 1 << vbi; 115 if (ve->instance_divisor < so->min_instance_div[vbi]) 116 so->min_instance_div[vbi] = ve->instance_divisor; 117 } 118 } 119 } 120 121 so->translate = translate_create(&transkey); 122 so->vertex_size = transkey.output_stride / 4; 123 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN / 124 MAX2(so->vertex_size, 1); 125 126 return so; 127} 128 129#define NV50_3D_VERTEX_ATTRIB_INACTIVE \ 130 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \ 131 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \ 132 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST 133 134static void 135nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, 136 struct pipe_vertex_element *ve, unsigned attr) 137{ 138 struct nouveau_pushbuf *push = nv50->base.pushbuf; 139 const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset; 140 float v[4]; 141 const unsigned nc = util_format_get_nr_components(ve->src_format); 142 143 assert(vb->user_buffer); 144 145 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1); 146 147 switch (nc) { 148 case 4: 149 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4); 150 PUSH_DATAf(push, v[0]); 151 PUSH_DATAf(push, v[1]); 152 PUSH_DATAf(push, v[2]); 153 PUSH_DATAf(push, v[3]); 154 break; 155 case 3: 156 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3); 157 PUSH_DATAf(push, v[0]); 158 PUSH_DATAf(push, v[1]); 159 PUSH_DATAf(push, v[2]); 160 break; 161 case 2: 162 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2); 163 PUSH_DATAf(push, v[0]); 164 PUSH_DATAf(push, v[1]); 165 break; 166 case 1: 167 if (attr == nv50->vertprog->vp.edgeflag) { 168 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); 169 PUSH_DATA (push, v[0] ? 1 : 0); 170 } 171 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1); 172 PUSH_DATAf(push, v[0]); 173 break; 174 default: 175 assert(0); 176 break; 177 } 178} 179 180static INLINE void 181nv50_user_vbuf_range(struct nv50_context *nv50, int vbi, 182 uint32_t *base, uint32_t *size) 183{ 184 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { 185 /* TODO: use min and max instance divisor to get a proper range */ 186 *base = 0; 187 *size = nv50->vtxbuf[vbi].buffer->width0; 188 } else { 189 /* NOTE: if there are user buffers, we *must* have index bounds */ 190 assert(nv50->vb_elt_limit != ~0); 191 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride; 192 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride + 193 nv50->vertex->vb_access_size[vbi]; 194 } 195} 196 197static void 198nv50_upload_user_buffers(struct nv50_context *nv50, 199 uint64_t addrs[], uint32_t limits[]) 200{ 201 unsigned b; 202 203 for (b = 0; b < nv50->num_vtxbufs; ++b) { 204 struct nouveau_bo *bo; 205 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b]; 206 uint32_t base, size; 207 208 if (!(nv50->vbo_user & (1 << b)) || !vb->stride) 209 continue; 210 nv50_user_vbuf_range(nv50, b, &base, &size); 211 212 limits[b] = base + size - 1; 213 addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size, 214 &bo); 215 if (addrs[b]) 216 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, NOUVEAU_BO_GART | 217 NOUVEAU_BO_RD, bo); 218 } 219 nv50->base.vbo_dirty = TRUE; 220} 221 222static void 223nv50_update_user_vbufs(struct nv50_context *nv50) 224{ 225 uint64_t address[PIPE_MAX_ATTRIBS]; 226 struct nouveau_pushbuf *push = nv50->base.pushbuf; 227 unsigned i; 228 uint32_t written = 0; 229 230 for (i = 0; i < nv50->vertex->num_elements; ++i) { 231 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe; 232 const unsigned b = ve->vertex_buffer_index; 233 struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b]; 234 uint32_t base, size; 235 236 if (!(nv50->vbo_user & (1 << b))) 237 continue; 238 239 if (!vb->stride) { 240 nv50_emit_vtxattr(nv50, vb, ve, i); 241 continue; 242 } 243 nv50_user_vbuf_range(nv50, b, &base, &size); 244 245 if (!(written & (1 << b))) { 246 struct nouveau_bo *bo; 247 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD; 248 written |= 1 << b; 249 address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, 250 base, size, &bo); 251 if (address[b]) 252 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo); 253 } 254 255 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 256 PUSH_DATAh(push, address[b] + base + size - 1); 257 PUSH_DATA (push, address[b] + base + size - 1); 258 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2); 259 PUSH_DATAh(push, address[b] + ve->src_offset); 260 PUSH_DATA (push, address[b] + ve->src_offset); 261 } 262 nv50->base.vbo_dirty = TRUE; 263} 264 265static INLINE void 266nv50_release_user_vbufs(struct nv50_context *nv50) 267{ 268 if (nv50->vbo_user) { 269 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_VERTEX_TMP); 270 nouveau_scratch_done(&nv50->base); 271 } 272} 273 274void 275nv50_vertex_arrays_validate(struct nv50_context *nv50) 276{ 277 uint64_t addrs[PIPE_MAX_ATTRIBS]; 278 uint32_t limits[PIPE_MAX_ATTRIBS]; 279 struct nouveau_pushbuf *push = nv50->base.pushbuf; 280 struct nv50_vertex_stateobj *vertex = nv50->vertex; 281 struct pipe_vertex_buffer *vb; 282 struct nv50_vertex_element *ve; 283 uint32_t mask; 284 uint32_t refd = 0; 285 unsigned i; 286 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts); 287 288 if (unlikely(vertex->need_conversion)) 289 nv50->vbo_fifo = ~0; 290 else 291 if (nv50->vbo_user & ~nv50->vbo_constant) 292 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0; 293 else 294 nv50->vbo_fifo = 0; 295 296 if (!nv50->vbo_fifo) { 297 /* if vertex buffer was written by GPU - flush VBO cache */ 298 for (i = 0; i < nv50->num_vtxbufs; ++i) { 299 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer); 300 if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 301 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 302 nv50->base.vbo_dirty = TRUE; 303 break; 304 } 305 } 306 } 307 308 /* update vertex format state */ 309 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n); 310 if (nv50->vbo_fifo) { 311 nv50->state.num_vtxelts = vertex->num_elements; 312 for (i = 0; i < vertex->num_elements; ++i) 313 PUSH_DATA (push, vertex->element[i].state); 314 for (; i < n; ++i) 315 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 316 for (i = 0; i < n; ++i) { 317 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 318 PUSH_DATA (push, 0); 319 } 320 return; 321 } 322 for (i = 0; i < vertex->num_elements; ++i) { 323 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 324 ve = &vertex->element[i]; 325 vb = &nv50->vtxbuf[b]; 326 327 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b))) 328 PUSH_DATA(push, ve->state); 329 else 330 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST); 331 } 332 for (; i < n; ++i) 333 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 334 335 /* update per-instance enables */ 336 mask = vertex->instance_elts ^ nv50->state.instance_elts; 337 while (mask) { 338 const int i = ffs(mask) - 1; 339 mask &= ~(1 << i); 340 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); 341 PUSH_DATA (push, (vertex->instance_elts >> i) & 1); 342 } 343 nv50->state.instance_elts = vertex->instance_elts; 344 345 if (nv50->vbo_user & ~nv50->vbo_constant) 346 nv50_upload_user_buffers(nv50, addrs, limits); 347 348 /* update buffers and set constant attributes */ 349 for (i = 0; i < vertex->num_elements; ++i) { 350 uint64_t address, limit; 351 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 352 ve = &vertex->element[i]; 353 vb = &nv50->vtxbuf[b]; 354 355 if (unlikely(nv50->vbo_constant & (1 << b))) { 356 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 357 PUSH_DATA (push, 0); 358 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i); 359 continue; 360 } else 361 if (nv50->vbo_user & (1 << b)) { 362 address = addrs[b] + ve->pipe.src_offset; 363 limit = addrs[b] + limits[b]; 364 } else { 365 struct nv04_resource *buf = nv04_resource(vb->buffer); 366 if (!(refd & (1 << b))) { 367 refd |= 1 << b; 368 BCTX_REFN(nv50->bufctx_3d, VERTEX, buf, RD); 369 } 370 address = buf->address + vb->buffer_offset + ve->pipe.src_offset; 371 limit = buf->address + buf->base.width0 - 1; 372 } 373 374 if (unlikely(ve->pipe.instance_divisor)) { 375 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4); 376 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 377 PUSH_DATAh(push, address); 378 PUSH_DATA (push, address); 379 PUSH_DATA (push, ve->pipe.instance_divisor); 380 } else { 381 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3); 382 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 383 PUSH_DATAh(push, address); 384 PUSH_DATA (push, address); 385 } 386 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 387 PUSH_DATAh(push, limit); 388 PUSH_DATA (push, limit); 389 } 390 for (; i < nv50->state.num_vtxelts; ++i) { 391 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 392 PUSH_DATA (push, 0); 393 } 394 nv50->state.num_vtxelts = vertex->num_elements; 395} 396 397#define NV50_PRIM_GL_CASE(n) \ 398 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n 399 400static INLINE unsigned 401nv50_prim_gl(unsigned prim) 402{ 403 switch (prim) { 404 NV50_PRIM_GL_CASE(POINTS); 405 NV50_PRIM_GL_CASE(LINES); 406 NV50_PRIM_GL_CASE(LINE_LOOP); 407 NV50_PRIM_GL_CASE(LINE_STRIP); 408 NV50_PRIM_GL_CASE(TRIANGLES); 409 NV50_PRIM_GL_CASE(TRIANGLE_STRIP); 410 NV50_PRIM_GL_CASE(TRIANGLE_FAN); 411 NV50_PRIM_GL_CASE(QUADS); 412 NV50_PRIM_GL_CASE(QUAD_STRIP); 413 NV50_PRIM_GL_CASE(POLYGON); 414 NV50_PRIM_GL_CASE(LINES_ADJACENCY); 415 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); 416 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY); 417 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); 418 default: 419 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; 420 break; 421 } 422} 423 424/* For pre-nva0 transform feedback. */ 425static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] = 426{ 427 [PIPE_PRIM_POINTS] = 1, 428 [PIPE_PRIM_LINES] = 2, 429 [PIPE_PRIM_LINE_LOOP] = 2, 430 [PIPE_PRIM_LINE_STRIP] = 2, 431 [PIPE_PRIM_TRIANGLES] = 3, 432 [PIPE_PRIM_TRIANGLE_STRIP] = 3, 433 [PIPE_PRIM_TRIANGLE_FAN] = 3, 434 [PIPE_PRIM_QUADS] = 3, 435 [PIPE_PRIM_QUAD_STRIP] = 3, 436 [PIPE_PRIM_POLYGON] = 3, 437 [PIPE_PRIM_LINES_ADJACENCY] = 2, 438 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2, 439 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3, 440 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3 441}; 442 443static void 444nv50_draw_arrays(struct nv50_context *nv50, 445 unsigned mode, unsigned start, unsigned count, 446 unsigned instance_count) 447{ 448 struct nouveau_pushbuf *push = nv50->base.pushbuf; 449 unsigned prim; 450 451 if (nv50->state.index_bias) { 452 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 453 PUSH_DATA (push, 0); 454 nv50->state.index_bias = 0; 455 } 456 457 prim = nv50_prim_gl(mode); 458 459 while (instance_count--) { 460 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 461 PUSH_DATA (push, prim); 462 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2); 463 PUSH_DATA (push, start); 464 PUSH_DATA (push, count); 465 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 466 PUSH_DATA (push, 0); 467 468 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 469 } 470} 471 472static void 473nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map, 474 unsigned start, unsigned count) 475{ 476 map += start; 477 478 if (count & 3) { 479 unsigned i; 480 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3); 481 for (i = 0; i < (count & 3); ++i) 482 PUSH_DATA(push, *map++); 483 count &= ~3; 484 } 485 while (count) { 486 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4; 487 488 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr); 489 for (i = 0; i < nr; ++i) { 490 PUSH_DATA(push, 491 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]); 492 map += 4; 493 } 494 count -= nr * 4; 495 } 496} 497 498static void 499nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map, 500 unsigned start, unsigned count) 501{ 502 map += start; 503 504 if (count & 1) { 505 count &= ~1; 506 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 507 PUSH_DATA (push, *map++); 508 } 509 while (count) { 510 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 511 512 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 513 for (i = 0; i < nr; ++i) { 514 PUSH_DATA(push, (map[1] << 16) | map[0]); 515 map += 2; 516 } 517 count -= nr * 2; 518 } 519} 520 521static void 522nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map, 523 unsigned start, unsigned count) 524{ 525 map += start; 526 527 while (count) { 528 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN); 529 530 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr); 531 PUSH_DATAp(push, map, nr); 532 533 map += nr; 534 count -= nr; 535 } 536} 537 538static void 539nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, 540 const uint32_t *map, 541 unsigned start, unsigned count) 542{ 543 map += start; 544 545 if (count & 1) { 546 count--; 547 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 548 PUSH_DATA (push, *map++); 549 } 550 while (count) { 551 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 552 553 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 554 for (i = 0; i < nr; ++i) { 555 PUSH_DATA(push, (map[1] << 16) | map[0]); 556 map += 2; 557 } 558 count -= nr * 2; 559 } 560} 561 562static void 563nv50_draw_elements(struct nv50_context *nv50, boolean shorten, 564 unsigned mode, unsigned start, unsigned count, 565 unsigned instance_count, int32_t index_bias) 566{ 567 struct nouveau_pushbuf *push = nv50->base.pushbuf; 568 unsigned prim; 569 const unsigned index_size = nv50->idxbuf.index_size; 570 571 prim = nv50_prim_gl(mode); 572 573 if (index_bias != nv50->state.index_bias) { 574 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 575 PUSH_DATA (push, index_bias); 576 nv50->state.index_bias = index_bias; 577 } 578 579 if (nv50->idxbuf.buffer) { 580 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer); 581 unsigned pb_start; 582 unsigned pb_bytes; 583 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3; 584 585 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1); 586 587 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)); 588 589 while (instance_count--) { 590 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 591 PUSH_DATA (push, prim); 592 593 nouveau_pushbuf_space(push, 8, 0, 1); 594 595 switch (index_size) { 596 case 4: 597 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count); 598 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4); 599 break; 600 case 2: 601 pb_start = (start & ~1) * 2; 602 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start; 603 604 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 605 PUSH_DATA (push, (start << 31) | count); 606 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4); 607 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 608 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 609 PUSH_DATA (push, 0); 610 break; 611 default: 612 assert(index_size == 1); 613 pb_start = start & ~3; 614 pb_bytes = ((start + count + 3) & ~3) - pb_start; 615 616 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 617 PUSH_DATA (push, (start << 30) | count); 618 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4); 619 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 620 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 621 PUSH_DATA (push, 0); 622 break; 623 } 624 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 625 PUSH_DATA (push, 0); 626 627 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 628 } 629 } else { 630 const void *data = nv50->idxbuf.user_buffer; 631 632 while (instance_count--) { 633 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 634 PUSH_DATA (push, prim); 635 switch (index_size) { 636 case 1: 637 nv50_draw_elements_inline_u08(push, data, start, count); 638 break; 639 case 2: 640 nv50_draw_elements_inline_u16(push, data, start, count); 641 break; 642 case 4: 643 if (shorten) 644 nv50_draw_elements_inline_u32_short(push, data, start, count); 645 else 646 nv50_draw_elements_inline_u32(push, data, start, count); 647 break; 648 default: 649 assert(0); 650 return; 651 } 652 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 653 PUSH_DATA (push, 0); 654 655 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 656 } 657 } 658} 659 660static void 661nva0_draw_stream_output(struct nv50_context *nv50, 662 const struct pipe_draw_info *info) 663{ 664 struct nouveau_pushbuf *push = nv50->base.pushbuf; 665 struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output); 666 struct nv04_resource *res = nv04_resource(so->pipe.buffer); 667 unsigned num_instances = info->instance_count; 668 unsigned mode = nv50_prim_gl(info->mode); 669 670 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) { 671 /* A proper implementation without waiting doesn't seem possible, 672 * so don't bother. 673 */ 674 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n"); 675 return; 676 } 677 678 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 679 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 680 PUSH_SPACE(push, 4); 681 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1); 682 PUSH_DATA (push, 0); 683 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 684 PUSH_DATA (push, 0); 685 } 686 687 assert(num_instances); 688 do { 689 PUSH_SPACE(push, 8); 690 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 691 PUSH_DATA (push, mode); 692 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1); 693 PUSH_DATA (push, 0); 694 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1); 695 PUSH_DATA (push, 0); 696 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BYTES), 1); 697 nv50_query_pushbuf_submit(push, so->pq, 0x4); 698 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 699 PUSH_DATA (push, 0); 700 701 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 702 } while (--num_instances); 703} 704 705static void 706nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan) 707{ 708 struct nv50_screen *screen = chan->user_priv; 709 710 nouveau_fence_update(&screen->base, TRUE); 711 712 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, TRUE); 713} 714 715void 716nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) 717{ 718 struct nv50_context *nv50 = nv50_context(pipe); 719 struct nouveau_pushbuf *push = nv50->base.pushbuf; 720 721 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */ 722 nv50->vb_elt_first = info->min_index + info->index_bias; 723 nv50->vb_elt_limit = info->max_index - info->min_index; 724 nv50->instance_off = info->start_instance; 725 nv50->instance_max = info->instance_count - 1; 726 727 /* For picking only a few vertices from a large user buffer, push is better, 728 * if index count is larger and we expect repeated vertices, suggest upload. 729 */ 730 nv50->vbo_push_hint = /* the 64 is heuristic */ 731 !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count)); 732 733 if (nv50->vbo_user && !(nv50->dirty & (NV50_NEW_ARRAYS | NV50_NEW_VERTEX))) { 734 if (!!nv50->vbo_fifo != nv50->vbo_push_hint) 735 nv50->dirty |= NV50_NEW_ARRAYS; 736 else 737 if (!nv50->vbo_fifo) 738 nv50_update_user_vbufs(nv50); 739 } 740 741 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog)) 742 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode]; 743 744 nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */ 745 746 push->kick_notify = nv50_draw_vbo_kick_notify; 747 748 if (nv50->vbo_fifo) { 749 nv50_push_vbo(nv50, info); 750 push->kick_notify = nv50_default_kick_notify; 751 nouveau_pushbuf_bufctx(push, NULL); 752 return; 753 } 754 755 if (nv50->state.instance_base != info->start_instance) { 756 nv50->state.instance_base = info->start_instance; 757 /* NOTE: this does not affect the shader input, should it ? */ 758 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1); 759 PUSH_DATA (push, info->start_instance); 760 } 761 762 if (nv50->base.vbo_dirty) { 763 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 764 PUSH_DATA (push, 0); 765 nv50->base.vbo_dirty = FALSE; 766 } 767 768 if (info->indexed) { 769 boolean shorten = info->max_index <= 65535; 770 771 if (info->primitive_restart != nv50->state.prim_restart) { 772 if (info->primitive_restart) { 773 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2); 774 PUSH_DATA (push, 1); 775 PUSH_DATA (push, info->restart_index); 776 777 if (info->restart_index > 65535) 778 shorten = FALSE; 779 } else { 780 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1); 781 PUSH_DATA (push, 0); 782 } 783 nv50->state.prim_restart = info->primitive_restart; 784 } else 785 if (info->primitive_restart) { 786 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1); 787 PUSH_DATA (push, info->restart_index); 788 789 if (info->restart_index > 65535) 790 shorten = FALSE; 791 } 792 793 nv50_draw_elements(nv50, shorten, 794 info->mode, info->start, info->count, 795 info->instance_count, info->index_bias); 796 } else 797 if (unlikely(info->count_from_stream_output)) { 798 nva0_draw_stream_output(nv50, info); 799 } else { 800 nv50_draw_arrays(nv50, 801 info->mode, info->start, info->count, 802 info->instance_count); 803 } 804 push->kick_notify = nv50_default_kick_notify; 805 806 nv50_release_user_vbufs(nv50); 807 808 nouveau_pushbuf_bufctx(push, NULL); 809} 810