1/************************************************************************** 2 3Copyright (C) 2004-2005 Nicolai Haehnle et al. 4 5Permission is hereby granted, free of charge, to any person obtaining a 6copy of this software and associated documentation files (the "Software"), 7to deal in the Software without restriction, including without limitation 8on the rights to use, copy, modify, merge, publish, distribute, sub 9license, and/or sell copies of the Software, and to permit persons to whom 10the Software is furnished to do so, subject to the following conditions: 11 12The above copyright notice and this permission notice (including the next 13paragraph) shall be included in all copies or substantial portions of the 14Software. 15 16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22USE OR OTHER DEALINGS IN THE SOFTWARE. 23 24**************************************************************************/ 25 26/* *INDENT-OFF* */ 27 28#ifndef _R300_REG_H 29#define _R300_REG_H 30 31#define R300_MC_INIT_MISC_LAT_TIMER 0x180 32# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 33# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 34# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 35# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 36# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 37# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 38# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 39# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 40 41 42#define R300_MC_INIT_GFX_LAT_TIMER 0x154 43# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 44# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 45# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 46# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 47# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 48# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 49# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 50# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 51 52/* 53 * This file contains registers and constants for the R300. They have been 54 * found mostly by examining command buffers captured using glxtest, as well 55 * as by extrapolating some known registers and constants from the R200. 56 * I am fairly certain that they are correct unless stated otherwise 57 * in comments. 58 */ 59 60#define R300_SE_VPORT_XSCALE 0x1D98 61#define R300_SE_VPORT_XOFFSET 0x1D9C 62#define R300_SE_VPORT_YSCALE 0x1DA0 63#define R300_SE_VPORT_YOFFSET 0x1DA4 64#define R300_SE_VPORT_ZSCALE 0x1DA8 65#define R300_SE_VPORT_ZOFFSET 0x1DAC 66 67#define R300_VAP_PORT_IDX0 0x2040 68/* 69 * Vertex Array Processing (VAP) Control 70 */ 71#define R300_VAP_CNTL 0x2080 72# define R300_PVS_NUM_SLOTS_SHIFT 0 73# define R300_PVS_NUM_CNTLRS_SHIFT 4 74# define R300_PVS_NUM_FPUS_SHIFT 8 75# define R300_VF_MAX_VTX_NUM_SHIFT 18 76# define R300_PVS_NUM_SLOTS(x) ((x) << 0) 77# define R300_PVS_NUM_CNTLRS(x) ((x) << 4) 78# define R300_PVS_NUM_FPUS(x) ((x) << 8) 79# define R300_PVS_VF_MAX_VTX_NUM(x) ((x) << 18) 80# define R300_GL_CLIP_SPACE_DEF (0 << 22) 81# define R300_DX_CLIP_SPACE_DEF (1 << 22) 82# define R500_TCL_STATE_OPTIMIZATION (1 << 23) 83 84/* This register is written directly and also starts data section 85 * in many 3d CP_PACKET3's 86 */ 87#define R300_VAP_VF_CNTL 0x2084 88# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 89# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) 90# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) 91# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) 92# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) 93# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) 94# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) 95# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) 96# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) 97# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) 98# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) 99# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) 100 101# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 102 /* State based - direct writes to registers trigger vertex 103 generation */ 104# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) 105# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) 106# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) 107# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) 108 109 /* I don't think I saw these three used.. */ 110# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 111# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 112# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 113 114 /* index size - when not set the indices are assumed to be 16 bit */ 115# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) 116# define R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS (1<<14) 117 /* number of vertices */ 118# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 119 120#define R500_VAP_INDEX_OFFSET 0x208c 121 122#define R500_VAP_ALT_NUM_VERTICES 0x2088 123 124#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 125# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 126# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 127# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) 128# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) 129# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) 130# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) 131 132#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 133 /* each of the following is 3 bits wide, specifies number 134 of components */ 135# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 136# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 137# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 138# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 139# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 140# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 141# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 142# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 143# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0 144# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1 145# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2 146# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3 147# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4 148 149#define R300_VAP_VPORT_XSCALE 0x2098 150#define R300_VAP_VPORT_XOFFSET 0x209c 151#define R300_VAP_VPORT_YSCALE 0x20a0 152#define R300_VAP_VPORT_YOFFSET 0x20a4 153#define R300_VAP_VPORT_ZSCALE 0x20a8 154#define R300_VAP_VPORT_ZOFFSET 0x20ac 155 156#define R300_VAP_VTE_CNTL 0x20b0 157#define R300_SE_VTE_CNTL R300_VAP_VTE_CNTL 158# define R300_VPORT_X_SCALE_ENA (1 << 0) 159# define R300_VPORT_X_OFFSET_ENA (1 << 1) 160# define R300_VPORT_Y_SCALE_ENA (1 << 2) 161# define R300_VPORT_Y_OFFSET_ENA (1 << 3) 162# define R300_VPORT_Z_SCALE_ENA (1 << 4) 163# define R300_VPORT_Z_OFFSET_ENA (1 << 5) 164# define R300_VTX_XY_FMT (1 << 8) 165# define R300_VTX_Z_FMT (1 << 9) 166# define R300_VTX_W0_FMT (1 << 10) 167# define R300_SERIAL_PROC_ENA (1 << 11) 168 169#define R300_VAP_VTX_SIZE 0x20b4 170 171/* BEGIN: Vertex data assembly - lots of uncertainties */ 172 173/* gap */ 174 175/* Maximum Vertex Indx Clamp */ 176#define R300_VAP_VF_MAX_VTX_INDX 0x2134 177/* Minimum Vertex Indx Clamp */ 178#define R300_VAP_VF_MIN_VTX_INDX 0x2138 179 180/** Vertex assembler/processor control status */ 181#define R300_VAP_CNTL_STATUS 0x2140 182/* No swap at all (default) */ 183# define R300_VC_NO_SWAP (0 << 0) 184/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */ 185# define R300_VC_16BIT_SWAP (1 << 0) 186/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */ 187# define R300_VC_32BIT_SWAP (2 << 0) 188/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */ 189# define R300_VC_HALF_DWORD_SWAP (3 << 0) 190/* The TCL engine will not be used (as it is logically or even physically removed) */ 191# define R300_VAP_TCL_BYPASS (1 << 8) 192/* Read only flag if TCL engine is busy. */ 193# define R300_VAP_PVS_BUSY (1 << 11) 194/* TODO: gap for MAX_MPS */ 195/* Read only flag if the vertex store is busy. */ 196# define R300_VAP_VS_BUSY (1 << 24) 197/* Read only flag if the reciprocal engine is busy. */ 198# define R300_VAP_RCP_BUSY (1 << 25) 199/* Read only flag if the viewport transform engine is busy. */ 200# define R300_VAP_VTE_BUSY (1 << 26) 201/* Read only flag if the memory interface unit is busy. */ 202# define R300_VAP_MUI_BUSY (1 << 27) 203/* Read only flag if the vertex cache is busy. */ 204# define R300_VAP_VC_BUSY (1 << 28) 205/* Read only flag if the vertex fetcher is busy. */ 206# define R300_VAP_VF_BUSY (1 << 29) 207/* Read only flag if the register pipeline is busy. */ 208# define R300_VAP_REGPIPE_BUSY (1 << 30) 209/* Read only flag if the VAP engine is busy. */ 210# define R300_VAP_VAP_BUSY (1 << 31) 211 212/* gap */ 213 214/* Where do we get our vertex data? 215 * 216 * Vertex data either comes either from immediate mode registers or from 217 * vertex arrays. 218 * There appears to be no mixed mode (though we can force the pitch of 219 * vertex arrays to 0, effectively reusing the same element over and over 220 * again). 221 * 222 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure 223 * if these registers influence vertex array processing. 224 * 225 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. 226 * 227 * In both cases, vertex attributes are then passed through INPUT_ROUTE. 228 * 229 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data 230 * into the vertex processor's input registers. 231 * The first word routes the first input, the second word the second, etc. 232 * The corresponding input is routed into the register with the given index. 233 * The list is ended by a word with INPUT_ROUTE_END set. 234 * 235 * Always set COMPONENTS_4 in immediate mode. 236 */ 237 238#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 239# define R300_DATA_TYPE_0_SHIFT 0 240# define R300_DATA_TYPE_FLOAT_1 0 241# define R300_DATA_TYPE_FLOAT_2 1 242# define R300_DATA_TYPE_FLOAT_3 2 243# define R300_DATA_TYPE_FLOAT_4 3 244# define R300_DATA_TYPE_BYTE 4 245# define R300_DATA_TYPE_D3DCOLOR 5 246# define R300_DATA_TYPE_SHORT_2 6 247# define R300_DATA_TYPE_SHORT_4 7 248# define R300_DATA_TYPE_VECTOR_3_TTT 8 249# define R300_DATA_TYPE_VECTOR_3_EET 9 250# define R300_DATA_TYPE_FLOAT_8 10 251# define R300_DATA_TYPE_FLT16_2 11 252# define R300_DATA_TYPE_FLT16_4 12 253# define R300_SKIP_DWORDS_SHIFT 4 254# define R300_DST_VEC_LOC_SHIFT 8 255# define R300_LAST_VEC (1 << 13) 256# define R300_SIGNED (1 << 14) 257# define R300_NORMALIZE (1 << 15) 258# define R300_DATA_TYPE_1_SHIFT 16 259#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 260#define R300_VAP_PROG_STREAM_CNTL_2 0x2158 261#define R300_VAP_PROG_STREAM_CNTL_3 0x215C 262#define R300_VAP_PROG_STREAM_CNTL_4 0x2160 263#define R300_VAP_PROG_STREAM_CNTL_5 0x2164 264#define R300_VAP_PROG_STREAM_CNTL_6 0x2168 265#define R300_VAP_PROG_STREAM_CNTL_7 0x216C 266/* gap */ 267 268/* Notes: 269 * - always set up to produce at least two attributes: 270 * if vertex program uses only position, fglrx will set normal, too 271 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. 272 */ 273#define R300_VAP_VTX_STATE_CNTL 0x2180 274# define R300_COLOR_0_ASSEMBLY_SHIFT 0 275# define R300_SEL_COLOR 0 276# define R300_SEL_USER_COLOR_0 1 277# define R300_SEL_USER_COLOR_1 2 278# define R300_COLOR_1_ASSEMBLY_SHIFT 2 279# define R300_COLOR_2_ASSEMBLY_SHIFT 4 280# define R300_COLOR_3_ASSEMBLY_SHIFT 6 281# define R300_COLOR_4_ASSEMBLY_SHIFT 8 282# define R300_COLOR_5_ASSEMBLY_SHIFT 10 283# define R300_COLOR_6_ASSEMBLY_SHIFT 12 284# define R300_COLOR_7_ASSEMBLY_SHIFT 14 285# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16) 286 287/* 288 * Each bit in this field applies to the corresponding vector in the VSM 289 * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit 290 * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream. 291 */ 292#define R300_VAP_VSM_VTX_ASSM 0x2184 293# define R300_INPUT_CNTL_POS 0x00000001 294# define R300_INPUT_CNTL_NORMAL 0x00000002 295# define R300_INPUT_CNTL_COLOR 0x00000004 296# define R300_INPUT_CNTL_TC0 0x00000400 297# define R300_INPUT_CNTL_TC1 0x00000800 298# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 299# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 300# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 301# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 302# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 303# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 304 305/* Programmable Stream Control Signed Normalize Control */ 306#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc 307# define SGN_NORM_ZERO 0 308# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1 309# define SGN_NORM_NO_ZERO 2 310# define R300_SGN_NORM_NO_ZERO (SGN_NORM_NO_ZERO | \ 311 (SGN_NORM_NO_ZERO << 2) | (SGN_NORM_NO_ZERO << 4) | \ 312 (SGN_NORM_NO_ZERO << 6) | (SGN_NORM_NO_ZERO << 8) | \ 313 (SGN_NORM_NO_ZERO << 10) | (SGN_NORM_NO_ZERO << 12) | \ 314 (SGN_NORM_NO_ZERO << 14) | (SGN_NORM_NO_ZERO << 16) | \ 315 (SGN_NORM_NO_ZERO << 18) | (SGN_NORM_NO_ZERO << 20) | \ 316 (SGN_NORM_NO_ZERO << 22) | (SGN_NORM_NO_ZERO << 24) | \ 317 (SGN_NORM_NO_ZERO << 26) | (SGN_NORM_NO_ZERO << 28) | \ 318 (SGN_NORM_NO_ZERO << 30)) 319 320/* gap */ 321 322/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 323 * are set to a swizzling bit pattern, other words are 0. 324 * 325 * In immediate mode, the pattern is always set to xyzw. In vertex array 326 * mode, the swizzling pattern is e.g. used to set zw components in texture 327 * coordinates with only tweo components. 328 */ 329#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 330# define R300_SWIZZLE0_SHIFT 0 331# define R300_SWIZZLE_SELECT_X_SHIFT 0 332# define R300_SWIZZLE_SELECT_Y_SHIFT 3 333# define R300_SWIZZLE_SELECT_Z_SHIFT 6 334# define R300_SWIZZLE_SELECT_W_SHIFT 9 335 336# define R300_SWIZZLE_SELECT_X 0 337# define R300_SWIZZLE_SELECT_Y 1 338# define R300_SWIZZLE_SELECT_Z 2 339# define R300_SWIZZLE_SELECT_W 3 340# define R300_SWIZZLE_SELECT_FP_ZERO 4 341# define R300_SWIZZLE_SELECT_FP_ONE 5 342/* alternate forms for r300_emit.c */ 343# define R300_INPUT_ROUTE_SELECT_X 0 344# define R300_INPUT_ROUTE_SELECT_Y 1 345# define R300_INPUT_ROUTE_SELECT_Z 2 346# define R300_INPUT_ROUTE_SELECT_W 3 347# define R300_INPUT_ROUTE_SELECT_ZERO 4 348# define R300_INPUT_ROUTE_SELECT_ONE 5 349 350# define R300_WRITE_ENA_SHIFT 12 351# define R300_WRITE_ENA_X 1 352# define R300_WRITE_ENA_Y 2 353# define R300_WRITE_ENA_Z 4 354# define R300_WRITE_ENA_W 8 355# define R300_SWIZZLE1_SHIFT 16 356 357# define R300_VAP_SWIZZLE_X001 \ 358 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \ 359 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Y_SHIFT) | \ 360 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | \ 361 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \ 362 (0xf << R300_WRITE_ENA_SHIFT)) 363 364# define R300_VAP_SWIZZLE_XY01 \ 365 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \ 366 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \ 367 (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | \ 368 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \ 369 (0xf << R300_WRITE_ENA_SHIFT)) 370 371# define R300_VAP_SWIZZLE_XYZ1 \ 372 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \ 373 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \ 374 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | \ 375 (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \ 376 (0xf << R300_WRITE_ENA_SHIFT)) 377 378# define R300_VAP_SWIZZLE_XYZW \ 379 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \ 380 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \ 381 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | \ 382 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | \ 383 (0xf << R300_WRITE_ENA_SHIFT)) 384 385#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 386#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8 387#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec 388#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0 389#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4 390#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8 391#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc 392 393/* END: Vertex data assembly */ 394 395/* gap */ 396 397/* BEGIN: Upload vertex program and data */ 398 399/* 400 * The programmable vertex shader unit has a memory bank of unknown size 401 * that can be written to in 16 byte units by writing the address into 402 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). 403 * 404 * Pointers into the memory bank are always in multiples of 16 bytes. 405 * 406 * The memory bank is divided into areas with fixed meaning. 407 * 408 * Starting at address UPLOAD_PROGRAM: Vertex program instructions. 409 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), 410 * whereas the difference between known addresses suggests size 512. 411 * 412 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. 413 * Native reported limits and the VPI layout suggest size 256, whereas 414 * difference between known addresses suggests size 512. 415 * 416 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the 417 * floating point pointsize. The exact purpose of this state is uncertain, 418 * as there is also the R300_RE_POINTSIZE register. 419 * 420 * Multiple vertex programs and parameter sets can be loaded at once, 421 * which could explain the size discrepancy. 422 */ 423#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 424# define R300_PVS_CODE_START 0 425# define R300_MAX_PVS_CODE_LINES 256 426# define R500_MAX_PVS_CODE_LINES 1024 427# define R300_PVS_CONST_START 512 428# define R500_PVS_CONST_START 1024 429# define R300_MAX_PVS_CONST_VECS 256 430# define R500_MAX_PVS_CONST_VECS 256 431# define R300_PVS_UCP_START 1024 432# define R500_PVS_UCP_START 1536 433# define R300_POINT_VPORT_SCALE_OFFSET 1030 434# define R500_POINT_VPORT_SCALE_OFFSET 1542 435# define R300_POINT_GEN_TEX_OFFSET 1031 436# define R500_POINT_GEN_TEX_OFFSET 1543 437 438/* 439 * These are obsolete defines form r300_context.h, but they might give some 440 * clues when investigating the addresses further... 441 */ 442#if 0 443#define VSF_DEST_PROGRAM 0x0 444#define VSF_DEST_MATRIX0 0x200 445#define VSF_DEST_MATRIX1 0x204 446#define VSF_DEST_MATRIX2 0x208 447#define VSF_DEST_VECTOR0 0x20c 448#define VSF_DEST_VECTOR1 0x20d 449#define VSF_DEST_UNKNOWN1 0x400 450#define VSF_DEST_UNKNOWN2 0x406 451#endif 452 453/* gap */ 454 455#define R300_VAP_PVS_UPLOAD_DATA 0x2208 456 457/* END: Upload vertex program and data */ 458 459/* gap */ 460 461/* I do not know the purpose of this register. However, I do know that 462 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL 463 * for normal rendering. 464 * 465 * 2007-11-05: This register is the user clip plane control register, but there 466 * also seems to be a rendering mode control; the NORMAL/CLEAR defines. 467 * 468 * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view 469 */ 470#define R500_VAP_TEX_TO_COLOR_CNTL 0x2218 471 472#define R300_VAP_CLIP_CNTL 0x221C 473# define R300_VAP_UCP_ENABLE_0 (1 << 0) 474# define R300_VAP_UCP_ENABLE_1 (1 << 1) 475# define R300_VAP_UCP_ENABLE_2 (1 << 2) 476# define R300_VAP_UCP_ENABLE_3 (1 << 3) 477# define R300_VAP_UCP_ENABLE_4 (1 << 4) 478# define R300_VAP_UCP_ENABLE_5 (1 << 5) 479# define R300_PS_UCP_MODE_DIST_COP (0 << 14) 480# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14) 481# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14) 482# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14) 483# define R300_CLIP_DISABLE (1 << 16) 484# define R300_UCP_CULL_ONLY_ENABLE (1 << 17) 485# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) 486# define R500_COLOR2_IS_TEXTURE (1 << 20) 487# define R500_COLOR3_IS_TEXTURE (1 << 21) 488 489/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first 490 * plane is per-pixel and the second plane is per-vertex. 491 * 492 * This was determined by experimentation alone but I believe it is correct. 493 * 494 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. 495 */ 496#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 497#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 498#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 499#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c 500 501#define R300_VAP_PVS_FLOW_CNTL_ADDRS_0 0x2230 502#define R300_PVS_FC_ACT_ADRS(x) ((x) << 0) 503#define R300_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 8) 504#define R300_PVS_FC_LAST_INST(x) ((x) << 16) 505#define R300_PVS_FC_RTN_INST(x) ((x) << 24) 506 507/* gap */ 508 509/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between 510 * rendering commands and overwriting vertex program parameters. 511 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 512 * avoids bugs caused by still running shaders reading bad data from memory. 513 */ 514#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 515 516/* This register is used to define the number of core clocks to wait for a 517 * vertex to be received by the VAP input controller (while the primitive 518 * path is backed up) before forcing any accumulated vertices to be submitted 519 * to the vertex processing path. 520 */ 521#define VAP_PVS_VTX_TIMEOUT_REG 0x2288 522# define R300_2288_R300 0x00750000 /* -- nh */ 523# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 524 525#define R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 0x2290 526#define R300_PVS_FC_LOOP_INIT_VAL(x) ((x) << 0) 527#define R300_PVS_FC_LOOP_STEP_VAL(x) ((x) << 8) 528 529/* gap */ 530 531/* Addresses are relative to the vertex program instruction area of the 532 * memory bank. PROGRAM_END points to the last instruction of the active 533 * program 534 * 535 * The meaning of the two UNKNOWN fields is obviously not known. However, 536 * experiments so far have shown that both *must* point to an instruction 537 * inside the vertex program, otherwise the GPU locks up. 538 * 539 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 540 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to 541 * position takes place. 542 * 543 * Most likely this is used to ignore rest of the program in cases 544 * where group of verts arent visible. For some reason this "section" 545 * is sometimes accepted other instruction that have no relationship with 546 * position calculations. 547 */ 548#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 549# define R300_PVS_FIRST_INST_SHIFT 0 550# define R300_PVS_XYZW_VALID_INST_SHIFT 10 551# define R300_PVS_LAST_INST_SHIFT 20 552# define R300_PVS_FIRST_INST(x) ((x) << 0) 553# define R300_PVS_XYZW_VALID_INST(x) ((x) << 10) 554# define R300_PVS_LAST_INST(x) ((x) << 20) 555/* Addresses are relative to the vertex program parameters area. */ 556#define R300_VAP_PVS_CONST_CNTL 0x22D4 557# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0 558# define R300_PVS_CONST_BASE_OFFSET(x) (x) 559# define R300_PVS_MAX_CONST_ADDR_SHIFT 16 560# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) 561#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 562# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 563#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC 564#define R300_VAP_PVS_FC_OPC_JUMP(x) (1 << (2 * (x))) 565#define R300_VAP_PVS_FC_OPC_LOOP(x) (2 << (2 * (x))) 566#define R300_VAP_PVS_FC_OPC_JSR(x) (3 << (2 * (x))) 567 568/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for 569 * immediate vertices 570 */ 571#define R300_VAP_VTX_COLOR_R 0x2464 572#define R300_VAP_VTX_COLOR_G 0x2468 573#define R300_VAP_VTX_COLOR_B 0x246C 574#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 575#define R300_VAP_VTX_POS_0_Y_1 0x2494 576#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 577#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 578#define R300_VAP_VTX_POS_0_Y_2 0x24A4 579#define R300_VAP_VTX_POS_0_Z_2 0x24A8 580/* write 0 to indicate end of packet? */ 581#define R300_VAP_VTX_END_OF_PKT 0x24AC 582 583#define R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0 0x2500 584#define R500_PVS_FC_ACT_ADRS(x) ((x) << 0) 585#define R500_PVS_FC_LOOP_CNT_JMP_INST(x) ((x) << 16) 586 587#define R500_VAP_PVS_FLOW_CNTL_ADDRS_UW_0 0x2504 588#define R500_PVS_FC_LAST_INST(x) ((x) << 0) 589#define R500_PVS_FC_RTN_INST(x) ((x) << 16) 590 591/* gap */ 592 593/* These are values from r300_reg/r300_reg.h - they are known to be correct 594 * and are here so we can use one register file instead of several 595 * - Vladimir 596 */ 597#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 598# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) 599# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 600# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) 601# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) 602# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) 603# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) 604# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) 605 606#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 607 /* each of the following is 3 bits wide, specifies number 608 of components */ 609# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 610# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 611# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 612# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 613# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 614# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 615# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 616# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 617 618/* UNK30 seems to enables point to quad transformation on textures 619 * (or something closely related to that). 620 * This bit is rather fatal at the time being due to lackings at pixel 621 * shader side 622 * Specifies top of Raster pipe specific enable controls. 623 */ 624#define R300_GB_ENABLE 0x4008 625# define R300_GB_POINT_STUFF_DISABLE (0 << 0) 626# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */ 627# define R300_GB_LINE_STUFF_DISABLE (0 << 1) 628# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */ 629# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2) 630# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */ 631# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4) 632# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */ 633# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */ 634 635 /* each of the following is 2 bits wide */ 636#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */ 637#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */ 638#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */ 639# define R300_GB_TEX0_SOURCE_SHIFT 16 640# define R300_GB_TEX1_SOURCE_SHIFT 18 641# define R300_GB_TEX2_SOURCE_SHIFT 20 642# define R300_GB_TEX3_SOURCE_SHIFT 22 643# define R300_GB_TEX4_SOURCE_SHIFT 24 644# define R300_GB_TEX5_SOURCE_SHIFT 26 645# define R300_GB_TEX6_SOURCE_SHIFT 28 646# define R300_GB_TEX7_SOURCE_SHIFT 30 647 648/* MSPOS - positions for multisample antialiasing (?) */ 649#define R300_GB_MSPOS0 0x4010 650 /* shifts - each of the fields is 4 bits */ 651# define R300_GB_MSPOS0__MS_X0_SHIFT 0 652# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 653# define R300_GB_MSPOS0__MS_X1_SHIFT 8 654# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 655# define R300_GB_MSPOS0__MS_X2_SHIFT 16 656# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 657# define R300_GB_MSPOS0__MSBD0_Y 24 658# define R300_GB_MSPOS0__MSBD0_X 28 659 660#define R300_GB_MSPOS1 0x4014 661# define R300_GB_MSPOS1__MS_X3_SHIFT 0 662# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 663# define R300_GB_MSPOS1__MS_X4_SHIFT 8 664# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 665# define R300_GB_MSPOS1__MS_X5_SHIFT 16 666# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 667# define R300_GB_MSPOS1__MSBD1 24 668 669/* Specifies the graphics pipeline configuration for rasterization. */ 670#define R300_GB_TILE_CONFIG 0x4018 671# define R300_GB_TILE_DISABLE (0 << 0) 672# define R300_GB_TILE_ENABLE (1 << 0) 673# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */ 674# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */ 675# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */ 676# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */ 677# define R300_GB_TILE_SIZE_8 (0 << 4) 678# define R300_GB_TILE_SIZE_16 (1 << 4) 679# define R300_GB_TILE_SIZE_32 (2 << 4) 680# define R300_GB_SUPER_SIZE_1 (0 << 6) 681# define R300_GB_SUPER_SIZE_2 (1 << 6) 682# define R300_GB_SUPER_SIZE_4 (2 << 6) 683# define R300_GB_SUPER_SIZE_8 (3 << 6) 684# define R300_GB_SUPER_SIZE_16 (4 << 6) 685# define R300_GB_SUPER_SIZE_32 (5 << 6) 686# define R300_GB_SUPER_SIZE_64 (6 << 6) 687# define R300_GB_SUPER_SIZE_128 (7 << 6) 688# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ 689# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ 690# define R300_GB_SUPER_TILE_A (0 << 15) 691# define R300_GB_SUPER_TILE_B (1 << 15) 692# define R300_GB_SUBPIXEL_1_12 (0 << 16) 693# define R300_GB_SUBPIXEL_1_16 (1 << 16) 694# define R300_GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17) 695# define R300_GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17) 696# define R300_GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17) 697# define R300_GB_TILE_CONFIG_QUADS_PER_RAS_32 (3 << 17) 698# define R300_GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19) 699# define R300_GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19) 700# define R300_GB_TILE_CONFIG_ALT_SCAN_EN_LR (0 << 20) 701# define R300_GB_TILE_CONFIG_ALT_SCAN_EN_LRL (1 << 20) 702# define R300_GB_TILE_CONFIG_ALT_OFFSET (0 << 21) 703# define R300_GB_TILE_CONFIG_SUBPRECISION (0 << 22) 704# define R300_GB_TILE_CONFIG_ALT_TILING_DEF (0 << 23) 705# define R300_GB_TILE_CONFIG_ALT_TILING_3_2 (1 << 23) 706# define R300_GB_TILE_CONFIG_Z_EXTENDED_24_1 (0 << 24) 707# define R300_GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24) 708 709/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */ 710#define R300_GB_FIFO_SIZE 0x4024 711 /* each of the following is 2 bits wide */ 712#define R300_GB_FIFO_SIZE_32 0 713#define R300_GB_FIFO_SIZE_64 1 714#define R300_GB_FIFO_SIZE_128 2 715#define R300_GB_FIFO_SIZE_256 3 716# define R300_SC_IFIFO_SIZE_SHIFT 0 717# define R300_SC_TZFIFO_SIZE_SHIFT 2 718# define R300_SC_BFIFO_SIZE_SHIFT 4 719 720# define R300_US_OFIFO_SIZE_SHIFT 12 721# define R300_US_WFIFO_SIZE_SHIFT 14 722 /* the following use the same constants as above, but meaning is 723 is times 2 (i.e. instead of 32 words it means 64 */ 724# define R300_RS_TFIFO_SIZE_SHIFT 6 725# define R300_RS_CFIFO_SIZE_SHIFT 8 726# define R300_US_RAM_SIZE_SHIFT 10 727 /* watermarks, 3 bits wide */ 728# define R300_RS_HIGHWATER_COL_SHIFT 16 729# define R300_RS_HIGHWATER_TEX_SHIFT 19 730# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ 731# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 732 733#define R300_GB_Z_PEQ_CONFIG 0x4028 734# define R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0) 735# define R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0) 736 737/* Specifies various polygon specific selects (fog, depth, perspective). */ 738#define R300_GB_SELECT 0x401c 739# define R300_GB_FOG_SELECT_C0A (0 << 0) 740# define R300_GB_FOG_SELECT_C1A (1 << 0) 741# define R300_GB_FOG_SELECT_C2A (2 << 0) 742# define R300_GB_FOG_SELECT_C3A (3 << 0) 743# define R300_GB_FOG_SELECT_1_1_W (4 << 0) 744# define R300_GB_FOG_SELECT_Z (5 << 0) 745# define R300_GB_DEPTH_SELECT_Z (0 << 3) 746# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3) 747# define R300_GB_W_SELECT_1_W (0 << 4) 748# define R300_GB_W_SELECT_1 (1 << 4) 749# define R300_GB_FOG_STUFF_DISABLE (0 << 5) 750# define R300_GB_FOG_STUFF_ENABLE (1 << 5) 751# define R300_GB_FOG_STUFF_TEX_SHIFT 6 752# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0 753# define R300_GB_FOG_STUFF_COMP_SHIFT 10 754# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00 755 756/* Specifies the graphics pipeline configuration for antialiasing. */ 757#define R300_GB_AA_CONFIG 0x4020 758# define R300_GB_AA_CONFIG_AA_DISABLE (0 << 0) 759# define R300_GB_AA_CONFIG_AA_ENABLE (1 << 0) 760# define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1) 761# define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3 (1 << 1) 762# define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4 (2 << 1) 763# define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6 (3 << 1) 764 765/* Selects which of 4 pipes are active. */ 766#define R300_GB_PIPE_SELECT 0x402c 767# define R300_GB_PIPE_SELECT_PIPE0_ID_SHIFT 0 768# define R300_GB_PIPE_SELECT_PIPE1_ID_SHIFT 2 769# define R300_GB_PIPE_SELECT_PIPE2_ID_SHIFT 4 770# define R300_GB_PIPE_SELECT_PIPE3_ID_SHIFT 6 771# define R300_GB_PIPE_SELECT_PIPE_MASK_SHIFT 8 772# define R300_GB_PIPE_SELECT_MAX_PIPE 12 773# define R300_GB_PIPE_SELECT_BAD_PIPES 14 774# define R300_GB_PIPE_SELECT_CONFIG_PIPES 18 775 776 777/* Specifies the sizes of the various FIFO`s in the sc/rs. */ 778#define R300_GB_FIFO_SIZE1 0x4070 779/* High water mark for SC input fifo */ 780# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0 781# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK 0x0000003f 782/* High water mark for SC input fifo (B) */ 783# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6 784# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK 0x00000fc0 785/* High water mark for RS colors' fifo */ 786# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT 12 787# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK 0x0003f000 788/* High water mark for RS textures' fifo */ 789# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18 790# define R300_GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000 791 792/* This table specifies the source location and format for up to 16 texture 793 * addresses (i[0]:i[15]) and four colors (c[0]:c[3]) 794 */ 795#define R500_RS_IP_0 0x4074 796#define R500_RS_IP_1 0x4078 797#define R500_RS_IP_2 0x407C 798#define R500_RS_IP_3 0x4080 799#define R500_RS_IP_4 0x4084 800#define R500_RS_IP_5 0x4088 801#define R500_RS_IP_6 0x408C 802#define R500_RS_IP_7 0x4090 803#define R500_RS_IP_8 0x4094 804#define R500_RS_IP_9 0x4098 805#define R500_RS_IP_10 0x409C 806#define R500_RS_IP_11 0x40A0 807#define R500_RS_IP_12 0x40A4 808#define R500_RS_IP_13 0x40A8 809#define R500_RS_IP_14 0x40AC 810#define R500_RS_IP_15 0x40B0 811#define R500_RS_IP_PTR_K0 62 812#define R500_RS_IP_PTR_K1 63 813#define R500_RS_IP_TEX_PTR_S_SHIFT 0 814#define R500_RS_IP_TEX_PTR_T_SHIFT 6 815#define R500_RS_IP_TEX_PTR_R_SHIFT 12 816#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 817#define R500_RS_IP_COL_PTR_SHIFT 24 818#define R500_RS_IP_COL_FMT_SHIFT 27 819# define R500_RS_SEL_S(x) ((x) << 0) 820# define R500_RS_SEL_T(x) ((x) << 6) 821# define R500_RS_SEL_R(x) ((x) << 12) 822# define R500_RS_SEL_Q(x) ((x) << 18) 823# define R500_RS_COL_PTR(x) ((x) << 24) 824# define R500_RS_COL_FMT(x) ((x) << 27) 825/* gap */ 826#define R500_RS_IP_OFFSET_DIS (0 << 31) 827#define R500_RS_IP_OFFSET_EN (1 << 31) 828 829/* gap */ 830 831/* Zero to flush caches. */ 832#define R300_TX_INVALTAGS 0x4100 833#define R300_TX_FLUSH 0x0 834 835/* The upper enable bits are guessed, based on fglrx reported limits. */ 836#define R300_TX_ENABLE 0x4104 837# define R300_TX_ENABLE_0 (1 << 0) 838# define R300_TX_ENABLE_1 (1 << 1) 839# define R300_TX_ENABLE_2 (1 << 2) 840# define R300_TX_ENABLE_3 (1 << 3) 841# define R300_TX_ENABLE_4 (1 << 4) 842# define R300_TX_ENABLE_5 (1 << 5) 843# define R300_TX_ENABLE_6 (1 << 6) 844# define R300_TX_ENABLE_7 (1 << 7) 845# define R300_TX_ENABLE_8 (1 << 8) 846# define R300_TX_ENABLE_9 (1 << 9) 847# define R300_TX_ENABLE_10 (1 << 10) 848# define R300_TX_ENABLE_11 (1 << 11) 849# define R300_TX_ENABLE_12 (1 << 12) 850# define R300_TX_ENABLE_13 (1 << 13) 851# define R300_TX_ENABLE_14 (1 << 14) 852# define R300_TX_ENABLE_15 (1 << 15) 853 854#define R500_TX_FILTER_4 0x4110 855# define R500_TX_WEIGHT_1_SHIFT (0) 856# define R500_TX_WEIGHT_0_SHIFT (11) 857# define R500_TX_WEIGHT_PAIR (1<<22) 858# define R500_TX_PHASE_SHIFT (23) 859# define R500_TX_DIRECTION_HORIZONTAL (0<<27) 860# define R500_TX_DIRECTION_VERITCAL (1<<27) 861 862#define R500_SU_TEX_WRAP_PS3 0x4114 863 864/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ 865#define R300_GA_POINT_S0 0x4200 866 867/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ 868#define R300_GA_POINT_T0 0x4204 869 870/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ 871#define R300_GA_POINT_S1 0x4208 872 873/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ 874#define R300_GA_POINT_T1 0x420c 875 876/* Specifies amount to shift integer position of vertex (screen space) before 877 * converting to float for triangle stipple. 878 */ 879#define R300_GA_TRIANGLE_STIPPLE 0x4214 880# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0 881# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f 882# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16 883# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000 884 885/* The pointsize is given in multiples of 6. The pointsize can be enormous: 886 * Clear() renders a single point that fills the entire framebuffer. 887 * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in 888 * 8b precision). 889 */ 890#define R300_GA_POINT_SIZE 0x421C 891# define R300_POINTSIZE_Y_SHIFT 0 892# define R300_POINTSIZE_Y_MASK 0x0000ffff 893# define R300_POINTSIZE_X_SHIFT 16 894# define R300_POINTSIZE_X_MASK 0xffff0000 895# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 896 897/* Red fill color */ 898#define R500_GA_FILL_R 0x4220 899 900/* Green fill color */ 901#define R500_GA_FILL_G 0x4224 902 903/* Blue fill color */ 904#define R500_GA_FILL_B 0x4228 905 906/* Alpha fill color */ 907#define R500_GA_FILL_A 0x422c 908 909 910/* Specifies maximum and minimum point & sprite sizes for per vertex size 911 * specification. The lower part (15:0) is MIN and (31:16) is max. 912 */ 913#define R300_GA_POINT_MINMAX 0x4230 914# define R300_GA_POINT_MINMAX_MIN_SHIFT 0 915# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0) 916# define R300_GA_POINT_MINMAX_MAX_SHIFT 16 917# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16) 918 919/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b 920 * subprecision); (16.0) fixed format. 921 * 922 * The line width is given in multiples of 6. 923 * In default mode lines are classified as vertical lines. 924 * HO: horizontal 925 * VE: vertical or horizontal 926 * HO & VE: no classification 927 */ 928#define R300_GA_LINE_CNTL 0x4234 929# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0 930# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff 931# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16) 932# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16) 933# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ 934# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ 935# define R500_GA_LINE_CNTL_SORT_NO (0 << 18) 936# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) 937/** TODO: looks wrong */ 938# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6) 939/** TODO: looks wrong */ 940# define R300_LINE_CNT_HO (1 << 16) 941/** TODO: looks wrong */ 942# define R300_LINE_CNT_VE (1 << 17) 943 944/* Line Stipple configuration information. */ 945#define R300_GA_LINE_STIPPLE_CONFIG 0x4238 946# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0) 947# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0) 948# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0) 949# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 950# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc 951 952/* Used to load US instructions and constants */ 953#define R500_GA_US_VECTOR_INDEX 0x4250 954# define R500_GA_US_VECTOR_INDEX_SHIFT 0 955# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff 956# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16) 957# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16) 958# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17) 959# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17) 960 961/* Data register for loading US instructions and constants */ 962#define R500_GA_US_VECTOR_DATA 0x4254 963 964/* Specifies color properties and mappings of textures. */ 965#define R500_GA_COLOR_CONTROL_PS3 0x4258 966# define R500_TEX0_SHADING_PS3_SOLID (0 << 0) 967# define R500_TEX0_SHADING_PS3_FLAT (1 << 0) 968# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0) 969# define R500_TEX1_SHADING_PS3_SOLID (0 << 2) 970# define R500_TEX1_SHADING_PS3_FLAT (1 << 2) 971# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2) 972# define R500_TEX2_SHADING_PS3_SOLID (0 << 4) 973# define R500_TEX2_SHADING_PS3_FLAT (1 << 4) 974# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4) 975# define R500_TEX3_SHADING_PS3_SOLID (0 << 6) 976# define R500_TEX3_SHADING_PS3_FLAT (1 << 6) 977# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6) 978# define R500_TEX4_SHADING_PS3_SOLID (0 << 8) 979# define R500_TEX4_SHADING_PS3_FLAT (1 << 8) 980# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8) 981# define R500_TEX5_SHADING_PS3_SOLID (0 << 10) 982# define R500_TEX5_SHADING_PS3_FLAT (1 << 10) 983# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10) 984# define R500_TEX6_SHADING_PS3_SOLID (0 << 12) 985# define R500_TEX6_SHADING_PS3_FLAT (1 << 12) 986# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12) 987# define R500_TEX7_SHADING_PS3_SOLID (0 << 14) 988# define R500_TEX7_SHADING_PS3_FLAT (1 << 14) 989# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14) 990# define R500_TEX8_SHADING_PS3_SOLID (0 << 16) 991# define R500_TEX8_SHADING_PS3_FLAT (1 << 16) 992# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16) 993# define R500_TEX9_SHADING_PS3_SOLID (0 << 18) 994# define R500_TEX9_SHADING_PS3_FLAT (1 << 18) 995# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18) 996# define R500_TEX10_SHADING_PS3_SOLID (0 << 20) 997# define R500_TEX10_SHADING_PS3_FLAT (1 << 20) 998# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20) 999# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22) 1000# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22) 1001# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22) 1002# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22) 1003# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22) 1004# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22) 1005# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22) 1006# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22) 1007# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22) 1008# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22) 1009# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22) 1010# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26) 1011# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26) 1012# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26) 1013# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26) 1014# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26) 1015# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26) 1016# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26) 1017# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26) 1018# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26) 1019# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26) 1020# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26) 1021 1022/* Returns idle status of various G3D block, captured when GA_IDLE written or 1023 * when hard or soft reset asserted. 1024 */ 1025#define R500_GA_IDLE 0x425c 1026# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0) 1027# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1) 1028# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2) 1029# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3) 1030# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4) 1031# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5) 1032# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6) 1033# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7) 1034# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8) 1035# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9) 1036# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10) 1037# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11) 1038# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12) 1039# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13) 1040# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14) 1041# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15) 1042# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16) 1043# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17) 1044# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18) 1045# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19) 1046# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20) 1047# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21) 1048# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22) 1049# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23) 1050# define R500_GA_IDLE_SU_IDLE (0 << 24) 1051# define R500_GA_IDLE_GA_IDLE (0 << 25) 1052# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26) 1053 1054/* Current value of stipple accumulator. */ 1055#define R300_GA_LINE_STIPPLE_VALUE 0x4260 1056 1057/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */ 1058#define R300_GA_LINE_S0 0x4264 1059/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */ 1060#define R300_GA_LINE_S1 0x4268 1061 1062/* GA Input fifo high water marks */ 1063#define R500_GA_FIFO_CNTL 0x4270 1064# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007 1065# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0 1066# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038 1067# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3 1068# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0 1069# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6 1070 1071/* GA enhance/tweaks */ 1072#define R300_GA_ENHANCE 0x4274 1073# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) 1074# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ 1075# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) 1076# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ 1077# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */ 1078# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */ 1079# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3) 1080# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */ 1081 1082#define R300_GA_COLOR_CONTROL 0x4278 1083# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) 1084# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0) 1085# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0) 1086# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2) 1087# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2) 1088# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2) 1089# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4) 1090# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4) 1091# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4) 1092# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6) 1093# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6) 1094# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6) 1095# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8) 1096# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8) 1097# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8) 1098# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10) 1099# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10) 1100# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10) 1101# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12) 1102# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12) 1103# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12) 1104# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14) 1105# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14) 1106# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14) 1107# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16) 1108# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16) 1109# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16) 1110# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16) 1111 1112# define R300_SHADE_MODEL_FLAT ( \ 1113 R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | \ 1114 R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \ 1115 R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | \ 1116 R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT | \ 1117 R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | \ 1118 R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \ 1119 R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | \ 1120 R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT ) 1121 1122# define R300_SHADE_MODEL_SMOOTH ( \ 1123 R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | \ 1124 R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \ 1125 R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | \ 1126 R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ 1127 R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | \ 1128 R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \ 1129 R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | \ 1130 R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD ) 1131 1132/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */ 1133#define R300_GA_SOLID_RG 0x427c 1134# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0 1135# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff 1136# define GA_SOLID_RG_COLOR_RED_SHIFT 16 1137# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000 1138/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */ 1139#define R300_GA_SOLID_BA 0x4280 1140# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0 1141# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff 1142# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16 1143# define GA_SOLID_BA_COLOR_BLUE_MASK 0xffff0000 1144 1145/* Polygon Mode 1146 * Dangerous 1147 */ 1148#define R300_GA_POLY_MODE 0x4288 1149# define R300_GA_POLY_MODE_DISABLE (0 << 0) 1150# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */ 1151/* reserved */ 1152# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4) 1153# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4) 1154# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4) 1155/* reserved */ 1156# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7) 1157# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7) 1158# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7) 1159/* reserved */ 1160 1161/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */ 1162#define R300_GA_ROUND_MODE 0x428c 1163# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0) 1164# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0) 1165# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2) 1166# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2) 1167# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4) 1168# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) 1169# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) 1170# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) 1171# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6 1172# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0 1173 1174/* Specifies x & y offsets for vertex data after conversion to FP. 1175 * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b 1176 * subprecision). 1177 */ 1178#define R300_GA_OFFSET 0x4290 1179# define R300_GA_OFFSET_X_OFFSET_SHIFT 0 1180# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff 1181# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16 1182# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000 1183 1184/* Specifies the scale to apply to fog. */ 1185#define R300_GA_FOG_SCALE 0x4294 1186/* Specifies the offset to apply to fog. */ 1187#define R300_GA_FOG_OFFSET 0x4298 1188/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */ 1189#define R300_GA_SOFT_RESET 0x429c 1190 1191/* Not sure why there are duplicate of factor and constant values. 1192 * My best guess so far is that there are seperate zbiases for test and write. 1193 * Ordering might be wrong. 1194 * Some of the tests indicate that fgl has a fallback implementation of zbias 1195 * via pixel shaders. 1196 */ 1197#define R300_SU_TEX_WRAP 0x42A0 1198#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4 1199#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8 1200#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC 1201#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0 1202 1203/* This register needs to be set to (1<<1) for RV350 to correctly 1204 * perform depth test (see --vb-triangles in r300_demo) 1205 * Don't know about other chips. - Vladimir 1206 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. 1207 * My guess is that there are two bits for each zbias primitive 1208 * (FILL, LINE, POINT). 1209 * One to enable depth test and one for depth write. 1210 * Yet this doesnt explain why depth writes work ... 1211 */ 1212#define R300_SU_POLY_OFFSET_ENABLE 0x42B4 1213# define R300_FRONT_ENABLE (1 << 0) 1214# define R300_BACK_ENABLE (1 << 1) 1215# define R300_PARA_ENABLE (1 << 2) 1216 1217#define R300_SU_CULL_MODE 0x42B8 1218# define R300_CULL_FRONT (1 << 0) 1219# define R300_CULL_BACK (1 << 1) 1220# define R300_FRONT_FACE_CCW (0 << 2) 1221# define R300_FRONT_FACE_CW (1 << 2) 1222 1223/* SU Depth Scale value */ 1224#define R300_SU_DEPTH_SCALE 0x42c0 1225/* SU Depth Offset value */ 1226#define R300_SU_DEPTH_OFFSET 0x42c4 1227 1228#define R300_SU_REG_DEST 0x42c8 1229# define R300_RASTER_PIPE_SELECT_0 (1 << 0) 1230# define R300_RASTER_PIPE_SELECT_1 (1 << 1) 1231# define R300_RASTER_PIPE_SELECT_2 (1 << 2) 1232# define R300_RASTER_PIPE_SELECT_3 (1 << 3) 1233# define R300_RASTER_PIPE_SELECT_ALL 0xf 1234 1235 1236/* BEGIN: Rasterization / Interpolators - many guesses */ 1237 1238/* 1239 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 1240 * on the vertex program, *not* the fragment program) 1241 */ 1242#define R300_RS_COUNT 0x4300 1243# define R300_IT_COUNT_SHIFT 0 1244# define R300_IT_COUNT_MASK 0x0000007f 1245# define R300_IC_COUNT_SHIFT 7 1246# define R300_IC_COUNT_MASK 0x00000780 1247# define R300_W_ADDR_SHIFT 12 1248# define R300_W_ADDR_MASK 0x0003f000 1249# define R300_HIRES_DIS (0 << 18) 1250# define R300_HIRES_EN (1 << 18) 1251# define R300_IT_COUNT(x) ((x) << 0) 1252# define R300_IC_COUNT(x) ((x) << 7) 1253# define R300_W_COUNT(x) ((x) << 12) 1254 1255#define R300_RS_INST_COUNT 0x4304 1256# define R300_RS_INST_COUNT_SHIFT 0 1257# define R300_RS_INST_COUNT_MASK 0x0000000f 1258# define R300_RS_TX_OFFSET_SHIFT 5 1259# define R300_RS_TX_OFFSET_MASK 0x000000e0 1260# define R300_RS_TX_OFFSET(x) ((x) << 5) 1261 1262/* gap */ 1263 1264/* Only used for texture coordinates. 1265 * Use the source field to route texture coordinate input from the 1266 * vertex program to the desired interpolator. Note that the source 1267 * field is relative to the outputs the vertex program *actually* 1268 * writes. If a vertex program only writes texcoord[1], this will 1269 * be source index 0. 1270 * Set INTERP_USED on all interpolators that produce data used by 1271 * the fragment program. INTERP_USED looks like a swizzling mask, 1272 * but I haven't seen it used that way. 1273 * 1274 * Note: The _UNKNOWN constants are always set in their respective 1275 * register. I don't know if this is necessary. 1276 */ 1277#define R300_RS_IP_0 0x4310 1278#define R300_RS_IP_1 0x4314 1279#define R300_RS_IP_2 0x4318 1280#define R300_RS_IP_3 0x431C 1281# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ 1282# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ 1283# define R300_RS_TEX_PTR(x) (x << 0) 1284# define R300_RS_COL_PTR(x) ((x) << 6) 1285# define R300_RS_COL_FMT(x) ((x) << 9) 1286# define R300_RS_COL_FMT_RGBA 0 1287# define R300_RS_COL_FMT_RGB0 1 1288# define R300_RS_COL_FMT_RGB1 2 1289# define R300_RS_COL_FMT_000A 4 1290# define R300_RS_COL_FMT_0000 5 1291# define R300_RS_COL_FMT_0001 6 1292# define R300_RS_COL_FMT_111A 8 1293# define R300_RS_COL_FMT_1110 9 1294# define R300_RS_COL_FMT_1111 10 1295# define R300_RS_SEL_S(x) ((x) << 13) 1296# define R300_RS_SEL_T(x) ((x) << 16) 1297# define R300_RS_SEL_R(x) ((x) << 19) 1298# define R300_RS_SEL_Q(x) ((x) << 22) 1299# define R300_RS_SEL_C0 0 1300# define R300_RS_SEL_C1 1 1301# define R300_RS_SEL_C2 2 1302# define R300_RS_SEL_C3 3 1303# define R300_RS_SEL_K0 4 1304# define R300_RS_SEL_K1 5 1305 1306 1307/* */ 1308#define R500_RS_INST_0 0x4320 1309#define R500_RS_INST_1 0x4324 1310#define R500_RS_INST_2 0x4328 1311#define R500_RS_INST_3 0x432c 1312#define R500_RS_INST_4 0x4330 1313#define R500_RS_INST_5 0x4334 1314#define R500_RS_INST_6 0x4338 1315#define R500_RS_INST_7 0x433c 1316#define R500_RS_INST_8 0x4340 1317#define R500_RS_INST_9 0x4344 1318#define R500_RS_INST_10 0x4348 1319#define R500_RS_INST_11 0x434c 1320#define R500_RS_INST_12 0x4350 1321#define R500_RS_INST_13 0x4354 1322#define R500_RS_INST_14 0x4358 1323#define R500_RS_INST_15 0x435c 1324#define R500_RS_INST_TEX_ID_SHIFT 0 1325# define R500_RS_INST_TEX_ID(x) ((x) << 0) 1326#define R500_RS_INST_TEX_CN_WRITE (1 << 4) 1327#define R500_RS_INST_TEX_ADDR_SHIFT 5 1328# define R500_RS_INST_TEX_ADDR(x) ((x) << 5) 1329#define R500_RS_INST_COL_ID_SHIFT 12 1330# define R500_RS_INST_COL_ID(x) ((x) << 12) 1331#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) 1332#define R500_RS_INST_COL_CN_WRITE (1 << 16) 1333#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) 1334#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) 1335#define R500_RS_INST_COL_ADDR_SHIFT 18 1336# define R500_RS_INST_COL_ADDR(x) ((x) << 18) 1337#define R500_RS_INST_TEX_ADJ (1 << 25) 1338#define R500_RS_INST_W_CN (1 << 26) 1339 1340/* These DWORDs control how vertex data is routed into fragment program 1341 * registers, after interpolators. 1342 */ 1343#define R300_RS_INST_0 0x4330 1344#define R300_RS_INST_1 0x4334 1345#define R300_RS_INST_2 0x4338 1346#define R300_RS_INST_3 0x433C 1347#define R300_RS_INST_4 0x4340 1348#define R300_RS_INST_5 0x4344 1349#define R300_RS_INST_6 0x4348 1350#define R300_RS_INST_7 0x434C 1351# define R300_RS_INST_TEX_ID(x) ((x) << 0) 1352# define R300_RS_INST_TEX_CN_WRITE (1 << 3) 1353# define R300_RS_INST_TEX_ADDR(x) ((x) << 6) 1354# define R300_RS_INST_TEX_ADDR_SHIFT 6 1355# define R300_RS_INST_COL_ID(x) ((x) << 11) 1356# define R300_RS_INST_COL_CN_WRITE (1 << 14) 1357# define R300_RS_INST_COL_ADDR(x) ((x) << 17) 1358# define R300_RS_INST_COL_ADDR_SHIFT 17 1359# define R300_RS_INST_TEX_ADJ (1 << 22) 1360# define R300_RS_COL_BIAS_UNUSED_SHIFT 23 1361 1362/* END: Rasterization / Interpolators - many guesses */ 1363 1364/* Hierarchical Z Enable */ 1365#define R300_SC_HYPERZ 0x43a4 1366# define R300_SC_HYPERZ_DISABLE (0 << 0) 1367# define R300_SC_HYPERZ_ENABLE (1 << 0) 1368# define R300_SC_HYPERZ_MIN (0 << 1) 1369# define R300_SC_HYPERZ_MAX (1 << 1) 1370# define R300_SC_HYPERZ_ADJ_256 (0 << 2) 1371# define R300_SC_HYPERZ_ADJ_128 (1 << 2) 1372# define R300_SC_HYPERZ_ADJ_64 (2 << 2) 1373# define R300_SC_HYPERZ_ADJ_32 (3 << 2) 1374# define R300_SC_HYPERZ_ADJ_16 (4 << 2) 1375# define R300_SC_HYPERZ_ADJ_8 (5 << 2) 1376# define R300_SC_HYPERZ_ADJ_4 (6 << 2) 1377# define R300_SC_HYPERZ_ADJ_2 (7 << 2) 1378# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) 1379# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) 1380# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) 1381# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) 1382 1383#define R300_SC_EDGERULE 0x43a8 1384 1385/* BEGIN: Scissors and cliprects */ 1386 1387/* There are four clipping rectangles. Their corner coordinates are inclusive. 1388 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending 1389 * on whether the pixel is inside cliprects 0-3, respectively. For example, 1390 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned 1391 * the number 3 (binary 0011). 1392 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, 1393 * the pixel is rasterized. 1394 * 1395 * In addition to this, there is a scissors rectangle. Only pixels inside the 1396 * scissors rectangle are drawn. (coordinates are inclusive) 1397 * 1398 * For some reason, the top-left corner of the framebuffer is at (1440, 1440) 1399 * for the purpose of clipping and scissors. 1400 */ 1401#define R300_SC_CLIPRECT_TL_0 0x43B0 1402#define R300_SC_CLIPRECT_BR_0 0x43B4 1403#define R300_SC_CLIPRECT_TL_1 0x43B8 1404#define R300_SC_CLIPRECT_BR_1 0x43BC 1405#define R300_SC_CLIPRECT_TL_2 0x43C0 1406#define R300_SC_CLIPRECT_BR_2 0x43C4 1407#define R300_SC_CLIPRECT_TL_3 0x43C8 1408#define R300_SC_CLIPRECT_BR_3 0x43CC 1409# define R300_CLIPRECT_OFFSET 1440 1410# define R300_CLIPRECT_MASK 0x1FFF 1411# define R300_CLIPRECT_X_SHIFT 0 1412# define R300_CLIPRECT_X_MASK (0x1FFF << 0) 1413# define R300_CLIPRECT_Y_SHIFT 13 1414# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) 1415#define R300_SC_CLIP_RULE 0x43D0 1416# define R300_CLIP_OUT (1 << 0) 1417# define R300_CLIP_0 (1 << 1) 1418# define R300_CLIP_1 (1 << 2) 1419# define R300_CLIP_10 (1 << 3) 1420# define R300_CLIP_2 (1 << 4) 1421# define R300_CLIP_20 (1 << 5) 1422# define R300_CLIP_21 (1 << 6) 1423# define R300_CLIP_210 (1 << 7) 1424# define R300_CLIP_3 (1 << 8) 1425# define R300_CLIP_30 (1 << 9) 1426# define R300_CLIP_31 (1 << 10) 1427# define R300_CLIP_310 (1 << 11) 1428# define R300_CLIP_32 (1 << 12) 1429# define R300_CLIP_320 (1 << 13) 1430# define R300_CLIP_321 (1 << 14) 1431# define R300_CLIP_3210 (1 << 15) 1432 1433/* gap */ 1434 1435#define R300_SC_SCISSORS_TL 0x43E0 1436#define R300_SC_SCISSORS_BR 0x43E4 1437# define R300_SCISSORS_OFFSET 1440 1438# define R300_SCISSORS_X_SHIFT 0 1439# define R300_SCISSORS_X_MASK (0x1FFF << 0) 1440# define R300_SCISSORS_Y_SHIFT 13 1441# define R300_SCISSORS_Y_MASK (0x1FFF << 13) 1442 1443/* Screen door sample mask */ 1444#define R300_SC_SCREENDOOR 0x43e8 1445 1446/* END: Scissors and cliprects */ 1447 1448/* BEGIN: Texture specification */ 1449 1450/* 1451 * The texture specification dwords are grouped by meaning and not by texture 1452 * unit. This means that e.g. the offset for texture image unit N is found in 1453 * register TX_OFFSET_0 + (4*N) 1454 */ 1455#define R300_TX_FILTER0_0 0x4400 1456#define R300_TX_FILTER0_1 0x4404 1457#define R300_TX_FILTER0_2 0x4408 1458#define R300_TX_FILTER0_3 0x440c 1459#define R300_TX_FILTER0_4 0x4410 1460#define R300_TX_FILTER0_5 0x4414 1461#define R300_TX_FILTER0_6 0x4418 1462#define R300_TX_FILTER0_7 0x441c 1463#define R300_TX_FILTER0_8 0x4420 1464#define R300_TX_FILTER0_9 0x4424 1465#define R300_TX_FILTER0_10 0x4428 1466#define R300_TX_FILTER0_11 0x442c 1467#define R300_TX_FILTER0_12 0x4430 1468#define R300_TX_FILTER0_13 0x4434 1469#define R300_TX_FILTER0_14 0x4438 1470#define R300_TX_FILTER0_15 0x443c 1471# define R300_TX_REPEAT 0 1472# define R300_TX_MIRRORED 1 1473# define R300_TX_CLAMP_TO_EDGE 2 1474# define R300_TX_MIRROR_ONCE_TO_EDGE 3 1475# define R300_TX_CLAMP 4 1476# define R300_TX_MIRROR_ONCE 5 1477# define R300_TX_CLAMP_TO_BORDER 6 1478# define R300_TX_MIRROR_ONCE_TO_BORDER 7 1479# define R300_TX_WRAP_S_SHIFT 0 1480# define R300_TX_WRAP_S_MASK (7 << 0) 1481# define R300_TX_WRAP_T_SHIFT 3 1482# define R300_TX_WRAP_T_MASK (7 << 3) 1483# define R300_TX_WRAP_R_SHIFT 6 1484# define R300_TX_WRAP_R_MASK (7 << 6) 1485# define R300_TX_MAG_FILTER_4 (0 << 9) 1486# define R300_TX_MAG_FILTER_NEAREST (1 << 9) 1487# define R300_TX_MAG_FILTER_LINEAR (2 << 9) 1488# define R300_TX_MAG_FILTER_ANISO (3 << 9) 1489# define R300_TX_MAG_FILTER_MASK (3 << 9) 1490# define R300_TX_MIN_FILTER_NEAREST (1 << 11) 1491# define R300_TX_MIN_FILTER_LINEAR (2 << 11) 1492# define R300_TX_MIN_FILTER_ANISO (3 << 11) 1493# define R300_TX_MIN_FILTER_MASK (3 << 11) 1494# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13) 1495# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13) 1496# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13) 1497# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13) 1498# define R300_TX_MAX_MIP_LEVEL_SHIFT 17 1499# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 17) 1500# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 1501# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21) 1502# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21) 1503# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21) 1504# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21) 1505# define R300_TX_MAX_ANISO_MASK (7 << 21) 1506# define R300_TX_WRAP_S(x) ((x) << 0) 1507# define R300_TX_WRAP_T(x) ((x) << 3) 1508# define R300_TX_MAX_MIP_LEVEL(x) ((x) << 17) 1509 1510#define R300_TX_FILTER1_0 0x4440 1511# define R300_CHROMA_KEY_MODE_DISABLE 0 1512# define R300_CHROMA_KEY_FORCE 1 1513# define R300_CHROMA_KEY_BLEND 2 1514# define R300_MC_ROUND_NORMAL (0<<2) 1515# define R300_MC_ROUND_MPEG4 (1<<2) 1516# define R300_LOD_BIAS_SHIFT 3 1517# define R300_LOD_BIAS_MASK 0x1ff8 1518# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) 1519# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) 1520# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) 1521# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) 1522# define R300_TX_TRI_PERF_0_8 (0<<15) 1523# define R300_TX_TRI_PERF_1_8 (1<<15) 1524# define R300_TX_TRI_PERF_1_4 (2<<15) 1525# define R300_TX_TRI_PERF_3_8 (3<<15) 1526# define R300_ANISO_THRESHOLD_MASK (7<<17) 1527 1528# define R400_DXTC_SWIZZLE_ENABLE (1<<21) 1529# define R500_MACRO_SWITCH (1<<22) 1530# define R500_TX_MAX_ANISO(x) ((x) << 23) 1531# define R500_TX_MAX_ANISO_MASK (63 << 23) 1532# define R500_TX_ANISO_HIGH_QUALITY (1 << 30) 1533# define R500_BORDER_FIX (1<<31) 1534 1535#define R300_TX_FORMAT0_0 0x4480 1536# define R300_TX_WIDTHMASK_SHIFT 0 1537# define R300_TX_WIDTHMASK_MASK (2047 << 0) 1538# define R300_TX_HEIGHTMASK_SHIFT 11 1539# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 1540# define R300_TX_DEPTHMASK_SHIFT 22 1541# define R300_TX_DEPTHMASK_MASK (0xf << 22) 1542# define R300_TX_SIZE_PROJECTED (1 << 30) 1543# define R300_TX_PITCH_EN (1 << 31) 1544# define R300_TX_WIDTH(x) ((x) << 0) 1545# define R300_TX_HEIGHT(x) ((x) << 11) 1546# define R300_TX_DEPTH(x) ((x) << 22) 1547# define R300_TX_NUM_LEVELS(x) ((x) << 26) 1548 1549#define R300_TX_FORMAT1_0 0x44C0 1550 /* The interpretation of the format word by Wladimir van der Laan */ 1551 /* The X, Y, Z and W refer to the layout of the components. 1552 They are given meanings as R, G, B and Alpha by the swizzle 1553 specification */ 1554# define R300_TX_FORMAT_X8 0x0 1555# define R300_TX_FORMAT_X16 0x1 1556# define R300_TX_FORMAT_Y4X4 0x2 1557# define R300_TX_FORMAT_Y8X8 0x3 1558# define R300_TX_FORMAT_Y16X16 0x4 1559# define R300_TX_FORMAT_Z3Y3X2 0x5 1560# define R300_TX_FORMAT_Z5Y6X5 0x6 1561# define R300_TX_FORMAT_Z6Y5X5 0x7 1562# define R300_TX_FORMAT_Z11Y11X10 0x8 1563# define R300_TX_FORMAT_Z10Y11X11 0x9 1564# define R300_TX_FORMAT_W4Z4Y4X4 0xA 1565# define R300_TX_FORMAT_W1Z5Y5X5 0xB 1566# define R300_TX_FORMAT_W8Z8Y8X8 0xC 1567# define R300_TX_FORMAT_W2Z10Y10X10 0xD 1568# define R300_TX_FORMAT_W16Z16Y16X16 0xE 1569# define R300_TX_FORMAT_DXT1 0xF 1570# define R300_TX_FORMAT_DXT3 0x10 1571# define R300_TX_FORMAT_DXT5 0x11 1572# define R300_TX_FORMAT_CxV8U8 0x12 1573# define R300_TX_FORMAT_AVYU444 0x13 1574# define R300_TX_FORMAT_VYUY422 0x14 1575# define R300_TX_FORMAT_YVYU422 0x15 1576# define R300_TX_FORMAT_16_MPEG 0x16 1577# define R300_TX_FORMAT_16_16_MPEG 0x17 1578# define R300_TX_FORMAT_16F 0x18 1579# define R300_TX_FORMAT_16F_16F 0x19 1580# define R300_TX_FORMAT_16F_16F_16F_16F 0x1A 1581# define R300_TX_FORMAT_32F 0x1B 1582# define R300_TX_FORMAT_32F_32F 0x1C 1583# define R300_TX_FORMAT_32F_32F_32F_32F 0x1D 1584# define R300_TX_FORMAT_W24_FP 0x1E 1585# define R400_TX_FORMAT_ATI2N 0x1F 1586 1587/* These need TX_FORMAT2_[0-15].TXFORMAT_MSB set. 1588 1589 My guess is the 10-bit formats are the 8-bit ones but with filtering being 1590 performed with the precision of 10 bits per channel. This makes sense 1591 with sRGB textures since the conversion to linear space reduces the precision 1592 significantly so the shader gets approximately the 8-bit precision 1593 in the end. It might also improve the quality of HDR rendering where 1594 high-precision filtering is desirable. 1595 1596 Again, this is guessed, the formats might mean something entirely else. 1597 The others should be fine. */ 1598# define R500_TX_FORMAT_X1 0x0 1599# define R500_TX_FORMAT_X1_REV 0x1 1600# define R500_TX_FORMAT_X10 0x2 1601# define R500_TX_FORMAT_Y10X10 0x3 1602# define R500_TX_FORMAT_W10Z10Y10X10 0x4 1603# define R500_TX_FORMAT_ATI1N 0x5 1604# define R500_TX_FORMAT_Y8X24 0x6 1605 1606 1607# define R300_TX_FORMAT_SIGNED_W (1 << 5) 1608# define R300_TX_FORMAT_SIGNED_Z (1 << 6) 1609# define R300_TX_FORMAT_SIGNED_Y (1 << 7) 1610# define R300_TX_FORMAT_SIGNED_X (1 << 8) 1611# define R300_TX_FORMAT_SIGNED (0xf << 5) 1612 1613# define R300_TX_FORMAT_3D (1 << 25) 1614# define R300_TX_FORMAT_CUBIC_MAP (2 << 25) 1615# define R300_TX_FORMAT_TEX_COORD_TYPE_MASK (0x3 << 25) 1616 1617 /* alpha modes, convenience mostly */ 1618 /* if you have alpha, pick constant appropriate to the 1619 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 1620# define R300_TX_FORMAT_ALPHA_1CH 0x000 1621# define R300_TX_FORMAT_ALPHA_2CH 0x200 1622# define R300_TX_FORMAT_ALPHA_4CH 0x600 1623# define R300_TX_FORMAT_ALPHA_NONE 0xA00 1624 /* Swizzling */ 1625 /* constants */ 1626# define R300_TX_FORMAT_X 0 1627# define R300_TX_FORMAT_Y 1 1628# define R300_TX_FORMAT_Z 2 1629# define R300_TX_FORMAT_W 3 1630# define R300_TX_FORMAT_ZERO 4 1631# define R300_TX_FORMAT_ONE 5 1632 /* 2.0*Z, everything above 1.0 is set to 0.0 */ 1633# define R300_TX_FORMAT_CUT_Z 6 1634 /* 2.0*W, everything above 1.0 is set to 0.0 */ 1635# define R300_TX_FORMAT_CUT_W 7 1636 1637# define R300_TX_FORMAT_B_SHIFT 18 1638# define R300_TX_FORMAT_G_SHIFT 15 1639# define R300_TX_FORMAT_R_SHIFT 12 1640# define R300_TX_FORMAT_A_SHIFT 9 1641 /* Convenience macro to take care of layout and swizzling */ 1642# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ 1643 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ 1644 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ 1645 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ 1646 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ 1647 | (R300_TX_FORMAT_##FMT) \ 1648 ) 1649 /* These can be ORed with result of R300_EASY_TX_FORMAT() 1650 We don't really know what they do. Take values from a 1651 constant color ? */ 1652# define R300_TX_FORMAT_CONST_X (1<<5) 1653# define R300_TX_FORMAT_CONST_Y (2<<5) 1654# define R300_TX_FORMAT_CONST_Z (4<<5) 1655# define R300_TX_FORMAT_CONST_W (8<<5) 1656 1657# define R300_TX_FORMAT_GAMMA (1 << 21) 1658# define R300_TX_FORMAT_YUV_TO_RGB (1 << 22) 1659 1660# define R300_TX_CACHE(x) ((x) << 27) 1661# define R300_TX_CACHE_WHOLE 0 1662/* reserved */ 1663# define R300_TX_CACHE_HALF_0 2 1664# define R300_TX_CACHE_HALF_1 3 1665# define R300_TX_CACHE_FOURTH_0 4 1666# define R300_TX_CACHE_FOURTH_1 5 1667# define R300_TX_CACHE_FOURTH_2 6 1668# define R300_TX_CACHE_FOURTH_3 7 1669# define R300_TX_CACHE_EIGHTH_0 8 1670# define R300_TX_CACHE_EIGHTH_1 9 1671# define R300_TX_CACHE_EIGHTH_2 10 1672# define R300_TX_CACHE_EIGHTH_3 11 1673# define R300_TX_CACHE_EIGHTH_4 12 1674# define R300_TX_CACHE_EIGHTH_5 13 1675# define R300_TX_CACHE_EIGHTH_6 14 1676# define R300_TX_CACHE_EIGHTH_7 15 1677# define R300_TX_CACHE_SIXTEENTH_0 16 1678# define R300_TX_CACHE_SIXTEENTH_1 17 1679# define R300_TX_CACHE_SIXTEENTH_2 18 1680# define R300_TX_CACHE_SIXTEENTH_3 19 1681# define R300_TX_CACHE_SIXTEENTH_4 20 1682# define R300_TX_CACHE_SIXTEENTH_5 21 1683# define R300_TX_CACHE_SIXTEENTH_6 22 1684# define R300_TX_CACHE_SIXTEENTH_7 23 1685# define R300_TX_CACHE_SIXTEENTH_8 24 1686# define R300_TX_CACHE_SIXTEENTH_9 25 1687# define R300_TX_CACHE_SIXTEENTH_10 26 1688# define R300_TX_CACHE_SIXTEENTH_11 27 1689# define R300_TX_CACHE_SIXTEENTH_12 28 1690# define R300_TX_CACHE_SIXTEENTH_13 29 1691# define R300_TX_CACHE_SIXTEENTH_14 30 1692# define R300_TX_CACHE_SIXTEENTH_15 31 1693 1694#define R300_TX_FORMAT2_0 0x4500 /* obvious missing in gap */ 1695# define R300_TX_PITCHMASK_SHIFT 0 1696# define R300_TX_PITCHMASK_MASK (2047 << 0) 1697# define R500_TXFORMAT_MSB (1 << 14) 1698# define R500_TXWIDTH_BIT11 (1 << 15) 1699# define R500_TXHEIGHT_BIT11 (1 << 16) 1700# define R500_POW2FIX2FLT (1 << 17) 1701# define R500_SEL_FILTER4_TC0 (0 << 18) 1702# define R500_SEL_FILTER4_TC1 (1 << 18) 1703# define R500_SEL_FILTER4_TC2 (2 << 18) 1704# define R500_SEL_FILTER4_TC3 (3 << 18) 1705 1706#define R300_TX_OFFSET_0 0x4540 1707#define R300_TX_OFFSET_1 0x4544 1708#define R300_TX_OFFSET_2 0x4548 1709#define R300_TX_OFFSET_3 0x454C 1710#define R300_TX_OFFSET_4 0x4550 1711#define R300_TX_OFFSET_5 0x4554 1712#define R300_TX_OFFSET_6 0x4558 1713#define R300_TX_OFFSET_7 0x455C 1714 1715# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 1716# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 1717# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 1718# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1719# define R300_TXO_MACRO_TILE_LINEAR (0 << 2) 1720# define R300_TXO_MACRO_TILE_TILED (1 << 2) 1721# define R300_TXO_MACRO_TILE(x) ((x) << 2) 1722# define R300_TXO_MICRO_TILE_LINEAR (0 << 3) 1723# define R300_TXO_MICRO_TILE_TILED (1 << 3) 1724# define R300_TXO_MICRO_TILE_TILED_SQUARE (2 << 3) 1725# define R300_TXO_MICRO_TILE(x) ((x) << 3) 1726# define R300_TXO_OFFSET_MASK 0xffffffe0 1727# define R300_TXO_OFFSET_SHIFT 5 1728 1729/* 32 bit chroma key */ 1730#define R300_TX_CHROMA_KEY_0 0x4580 1731#define R300_TX_CHROMA_KEY_1 0x4584 1732#define R300_TX_CHROMA_KEY_2 0x4588 1733#define R300_TX_CHROMA_KEY_3 0x458c 1734#define R300_TX_CHROMA_KEY_4 0x4590 1735#define R300_TX_CHROMA_KEY_5 0x4594 1736#define R300_TX_CHROMA_KEY_6 0x4598 1737#define R300_TX_CHROMA_KEY_7 0x459c 1738#define R300_TX_CHROMA_KEY_8 0x45a0 1739#define R300_TX_CHROMA_KEY_9 0x45a4 1740#define R300_TX_CHROMA_KEY_10 0x45a8 1741#define R300_TX_CHROMA_KEY_11 0x45ac 1742#define R300_TX_CHROMA_KEY_12 0x45b0 1743#define R300_TX_CHROMA_KEY_13 0x45b4 1744#define R300_TX_CHROMA_KEY_14 0x45b8 1745#define R300_TX_CHROMA_KEY_15 0x45bc 1746/* ff00ff00 == { 0, 1.0, 0, 1.0 } */ 1747 1748/* Border Color */ 1749#define R300_TX_BORDER_COLOR_0 0x45c0 1750#define R300_TX_BORDER_COLOR_1 0x45c4 1751#define R300_TX_BORDER_COLOR_2 0x45c8 1752#define R300_TX_BORDER_COLOR_3 0x45cc 1753#define R300_TX_BORDER_COLOR_4 0x45d0 1754#define R300_TX_BORDER_COLOR_5 0x45d4 1755#define R300_TX_BORDER_COLOR_6 0x45d8 1756#define R300_TX_BORDER_COLOR_7 0x45dc 1757#define R300_TX_BORDER_COLOR_8 0x45e0 1758#define R300_TX_BORDER_COLOR_9 0x45e4 1759#define R300_TX_BORDER_COLOR_10 0x45e8 1760#define R300_TX_BORDER_COLOR_11 0x45ec 1761#define R300_TX_BORDER_COLOR_12 0x45f0 1762#define R300_TX_BORDER_COLOR_13 0x45f4 1763#define R300_TX_BORDER_COLOR_14 0x45f8 1764#define R300_TX_BORDER_COLOR_15 0x45fc 1765 1766 1767/* END: Texture specification */ 1768 1769/* BEGIN: Fragment program instruction set */ 1770 1771/* Fragment programs are written directly into register space. 1772 * There are separate instruction streams for texture instructions and ALU 1773 * instructions. 1774 * In order to synchronize these streams, the program is divided into up 1775 * to 4 nodes. Each node begins with a number of TEX operations, followed 1776 * by a number of ALU operations. 1777 * The first node can have zero TEX ops, all subsequent nodes must have at 1778 * least 1779 * one TEX ops. 1780 * All nodes must have at least one ALU op. 1781 * 1782 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means 1783 * 1 node, a value of 3 means 4 nodes. 1784 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are 1785 * offsets into the respective instruction streams, while *_END points to the 1786 * last instruction relative to this offset. 1787 */ 1788#define R300_US_CONFIG 0x4600 1789# define R300_PFS_CNTL_LAST_NODES_SHIFT 0 1790# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) 1791# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) 1792#define R300_US_PIXSIZE 0x4604 1793/* There is an unshifted value here which has so far always been equal to the 1794 * index of the highest used temporary register. 1795 */ 1796#define R300_US_CODE_OFFSET 0x4608 1797# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 1798# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) 1799# define R300_PFS_CNTL_ALU_END_SHIFT 6 1800# define R300_PFS_CNTL_ALU_END_MASK (63 << 6) 1801# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 13 1802# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 13) 1803# define R300_PFS_CNTL_TEX_END_SHIFT 18 1804# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) 1805# define R400_PFS_CNTL_TEX_OFFSET_MSB_SHIFT 24 1806# define R400_PFS_CNTL_TEX_OFFSET_MSB_MASK (0xf << 24) 1807# define R400_PFS_CNTL_TEX_END_MSB_SHIFT 28 1808# define R400_PFS_CNTL_TEX_END_MSB_MASK (0xf << 28) 1809 1810/* gap */ 1811 1812/* Nodes are stored backwards. The last active node is always stored in 1813 * PFS_NODE_3. 1814 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The 1815 * first node is stored in NODE_2, the second node is stored in NODE_3. 1816 * 1817 * Offsets are relative to the master offset from PFS_CNTL_2. 1818 */ 1819#define R300_US_CODE_ADDR_0 0x4610 1820#define R300_US_CODE_ADDR_1 0x4614 1821#define R300_US_CODE_ADDR_2 0x4618 1822#define R300_US_CODE_ADDR_3 0x461C 1823# define R300_ALU_START_SHIFT 0 1824# define R300_ALU_START_MASK (63 << 0) 1825# define R300_ALU_SIZE_SHIFT 6 1826# define R300_ALU_SIZE_MASK (63 << 6) 1827# define R300_TEX_START_SHIFT 12 1828# define R300_TEX_START_MASK (31 << 12) 1829# define R300_TEX_SIZE_SHIFT 17 1830# define R300_TEX_SIZE_MASK (31 << 17) 1831# define R300_RGBA_OUT (1 << 22) 1832# define R300_W_OUT (1 << 23) 1833# define R400_TEX_START_MSB_SHIFT 24 1834# define R400_TEX_START_MSG_MASK (0xf << 24) 1835# define R400_TEX_SIZE_MSB_SHIFT 28 1836# define R400_TEX_SIZE_MSG_MASK (0xf << 28) 1837 1838/* TEX 1839 * As far as I can tell, texture instructions cannot write into output 1840 * registers directly. A subsequent ALU instruction is always necessary, 1841 * even if it's just MAD o0, r0, 1, 0 1842 */ 1843#define R300_US_TEX_INST_0 0x4620 1844# define R300_SRC_ADDR_SHIFT 0 1845# define R300_SRC_ADDR_MASK (31 << 0) 1846# define R300_DST_ADDR_SHIFT 6 1847# define R300_DST_ADDR_MASK (31 << 6) 1848# define R300_TEX_ID_SHIFT 11 1849# define R300_TEX_ID_MASK (15 << 11) 1850# define R300_TEX_INST_SHIFT 15 1851# define R300_TEX_OP_NOP 0 1852# define R300_TEX_OP_LD 1 1853# define R300_TEX_OP_KIL 2 1854# define R300_TEX_OP_TXP 3 1855# define R300_TEX_OP_TXB 4 1856# define R300_TEX_INST_MASK (7 << 15) 1857# define R400_SRC_ADDR_EXT_BIT (1 << 19) 1858# define R400_DST_ADDR_EXT_BIT (1 << 20) 1859 1860/* Output format from the unfied shader */ 1861#define R300_US_OUT_FMT_0 0x46A4 1862# define R300_US_OUT_FMT_C4_8 (0 << 0) 1863# define R300_US_OUT_FMT_C4_10 (1 << 0) 1864# define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0) 1865# define R300_US_OUT_FMT_C_16 (3 << 0) 1866# define R300_US_OUT_FMT_C2_16 (4 << 0) 1867# define R300_US_OUT_FMT_C4_16 (5 << 0) 1868# define R300_US_OUT_FMT_C_16_MPEG (6 << 0) 1869# define R300_US_OUT_FMT_C2_16_MPEG (7 << 0) 1870# define R300_US_OUT_FMT_C2_4 (8 << 0) 1871# define R300_US_OUT_FMT_C_3_3_2 (9 << 0) 1872# define R300_US_OUT_FMT_C_6_5_6 (10 << 0) 1873# define R300_US_OUT_FMT_C_11_11_10 (11 << 0) 1874# define R300_US_OUT_FMT_C_10_11_11 (12 << 0) 1875# define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0) 1876/* reserved */ 1877# define R300_US_OUT_FMT_UNUSED (15 << 0) 1878# define R300_US_OUT_FMT_C_16_FP (16 << 0) 1879# define R300_US_OUT_FMT_C2_16_FP (17 << 0) 1880# define R300_US_OUT_FMT_C4_16_FP (18 << 0) 1881# define R300_US_OUT_FMT_C_32_FP (19 << 0) 1882# define R300_US_OUT_FMT_C2_32_FP (20 << 0) 1883# define R300_US_OUT_FMT_C4_32_FP (21 << 0) 1884# define R300_C0_SEL_A (0 << 8) 1885# define R300_C0_SEL_R (1 << 8) 1886# define R300_C0_SEL_G (2 << 8) 1887# define R300_C0_SEL_B (3 << 8) 1888# define R300_C1_SEL_A (0 << 10) 1889# define R300_C1_SEL_R (1 << 10) 1890# define R300_C1_SEL_G (2 << 10) 1891# define R300_C1_SEL_B (3 << 10) 1892# define R300_C2_SEL_A (0 << 12) 1893# define R300_C2_SEL_R (1 << 12) 1894# define R300_C2_SEL_G (2 << 12) 1895# define R300_C2_SEL_B (3 << 12) 1896# define R300_C3_SEL_A (0 << 14) 1897# define R300_C3_SEL_R (1 << 14) 1898# define R300_C3_SEL_G (2 << 14) 1899# define R300_C3_SEL_B (3 << 14) 1900# define R300_OUT_SIGN(x) ((x) << 16) 1901# define R500_ROUND_ADJ (1 << 20) 1902 1903/* ALU 1904 * The ALU instructions register blocks are enumerated according to the order 1905 * in which fglrx. I assume there is space for 64 instructions, since 1906 * each block has space for a maximum of 64 DWORDs, and this matches reported 1907 * native limits. 1908 * 1909 * The basic functional block seems to be one MAD for each color and alpha, 1910 * and an adder that adds all components after the MUL. 1911 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands 1912 * - DP4: Use OUTC_DP4, OUTA_DP4 1913 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands 1914 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands 1915 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 1916 * - CMP: If ARG2 < 0, return ARG1, else return ARG0 1917 * - FLR: use FRC+MAD 1918 * - XPD: use MAD+MAD 1919 * - SGE, SLT: use MAD+CMP 1920 * - RSQ: use ABS modifier for argument 1921 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation 1922 * (e.g. RCP) into color register 1923 * - apparently, there's no quick DST operation 1924 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" 1925 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" 1926 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" 1927 * 1928 * Operand selection 1929 * First stage selects three sources from the available registers and 1930 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). 1931 * fglrx sorts the three source fields: Registers before constants, 1932 * lower indices before higher indices; I do not know whether this is 1933 * necessary. 1934 * 1935 * fglrx fills unused sources with "read constant 0" 1936 * According to specs, you cannot select more than two different constants. 1937 * 1938 * Second stage selects the operands from the sources. This is defined in 1939 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants 1940 * zero and one. 1941 * Swizzling and negation happens in this stage, as well. 1942 * 1943 * Important: Color and alpha seem to be mostly separate, i.e. their sources 1944 * selection appears to be fully independent (the register storage is probably 1945 * physically split into a color and an alpha section). 1946 * However (because of the apparent physical split), there is some interaction 1947 * WRT swizzling. If, for example, you want to load an R component into an 1948 * Alpha operand, this R component is taken from a *color* source, not from 1949 * an alpha source. The corresponding register doesn't even have to appear in 1950 * the alpha sources list. (I hope this all makes sense to you) 1951 * 1952 * Destination selection 1953 * The destination register index is in FPI1 (color) and FPI3 (alpha) 1954 * together with enable bits. 1955 * There are separate enable bits for writing into temporary registers 1956 * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_* 1957 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the 1958 * same index must be used for both). 1959 * 1960 * Note: There is a special form for LRP 1961 * - Argument order is the same as in ARB_fragment_program. 1962 * - Operation is MAD 1963 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP 1964 * - Set FPI0/FPI2_SPECIAL_LRP 1965 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD 1966 */ 1967#define R300_US_ALU_RGB_ADDR_0 0x46C0 1968# define R300_ALU_SRC0C_SHIFT 0 1969# define R300_ALU_SRC0C_MASK (31 << 0) 1970# define R300_ALU_SRC0C_CONST (1 << 5) 1971# define R300_ALU_SRC1C_SHIFT 6 1972# define R300_ALU_SRC1C_MASK (31 << 6) 1973# define R300_ALU_SRC1C_CONST (1 << 11) 1974# define R300_ALU_SRC2C_SHIFT 12 1975# define R300_ALU_SRC2C_MASK (31 << 12) 1976# define R300_ALU_SRC2C_CONST (1 << 17) 1977# define R300_ALU_SRC_MASK 0x0003ffff 1978# define R300_ALU_DSTC_SHIFT 18 1979# define R300_ALU_DSTC_MASK (31 << 18) 1980# define R300_ALU_DSTC_REG_MASK_SHIFT 23 1981# define R300_ALU_DSTC_REG_X (1 << 23) 1982# define R300_ALU_DSTC_REG_Y (1 << 24) 1983# define R300_ALU_DSTC_REG_Z (1 << 25) 1984# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26 1985# define R300_ALU_DSTC_OUTPUT_X (1 << 26) 1986# define R300_ALU_DSTC_OUTPUT_Y (1 << 27) 1987# define R300_ALU_DSTC_OUTPUT_Z (1 << 28) 1988# define R300_ALU_DSTC_OUTPUT_XYZ (7 << 26) 1989# define R300_RGB_ADDR0(x) ((x) << 0) 1990# define R300_RGB_ADDR1(x) ((x) << 6) 1991# define R300_RGB_ADDR2(x) ((x) << 12) 1992# define R300_RGB_TARGET(x) ((x) << 29) 1993 1994#define R300_US_ALU_ALPHA_ADDR_0 0x47C0 1995# define R300_ALU_SRC0A_SHIFT 0 1996# define R300_ALU_SRC0A_MASK (31 << 0) 1997# define R300_ALU_SRC0A_CONST (1 << 5) 1998# define R300_ALU_SRC1A_SHIFT 6 1999# define R300_ALU_SRC1A_MASK (31 << 6) 2000# define R300_ALU_SRC1A_CONST (1 << 11) 2001# define R300_ALU_SRC2A_SHIFT 12 2002# define R300_ALU_SRC2A_MASK (31 << 12) 2003# define R300_ALU_SRC2A_CONST (1 << 17) 2004# define R300_ALU_SRC_MASK 0x0003ffff 2005# define R300_ALU_DSTA_SHIFT 18 2006# define R300_ALU_DSTA_MASK (31 << 18) 2007# define R300_ALU_DSTA_REG (1 << 23) 2008# define R300_ALU_DSTA_OUTPUT (1 << 24) 2009# define R300_ALU_DSTA_DEPTH (1 << 27) 2010# define R300_ALPHA_ADDR0(x) ((x) << 0) 2011# define R300_ALPHA_ADDR1(x) ((x) << 6) 2012# define R300_ALPHA_ADDR2(x) ((x) << 12) 2013# define R300_ALPHA_TARGET(x) ((x) << 25) 2014 2015#define R300_US_ALU_RGB_INST_0 0x48C0 2016# define R300_ALU_ARGC_SRC0C_XYZ 0 2017# define R300_ALU_ARGC_SRC0C_XXX 1 2018# define R300_ALU_ARGC_SRC0C_YYY 2 2019# define R300_ALU_ARGC_SRC0C_ZZZ 3 2020# define R300_ALU_ARGC_SRC1C_XYZ 4 2021# define R300_ALU_ARGC_SRC1C_XXX 5 2022# define R300_ALU_ARGC_SRC1C_YYY 6 2023# define R300_ALU_ARGC_SRC1C_ZZZ 7 2024# define R300_ALU_ARGC_SRC2C_XYZ 8 2025# define R300_ALU_ARGC_SRC2C_XXX 9 2026# define R300_ALU_ARGC_SRC2C_YYY 10 2027# define R300_ALU_ARGC_SRC2C_ZZZ 11 2028# define R300_ALU_ARGC_SRC0A 12 2029# define R300_ALU_ARGC_SRC1A 13 2030# define R300_ALU_ARGC_SRC2A 14 2031# define R300_ALU_ARGC_SRCP_XYZ 15 2032# define R300_ALU_ARGC_SRCP_XXX 16 2033# define R300_ALU_ARGC_SRCP_YYY 17 2034# define R300_ALU_ARGC_SRCP_ZZZ 18 2035# define R300_ALU_ARGC_SRCP_WWW 19 2036# define R300_ALU_ARGC_ZERO 20 2037# define R300_ALU_ARGC_ONE 21 2038# define R300_ALU_ARGC_HALF 22 2039# define R300_ALU_ARGC_SRC0C_YZX 23 2040# define R300_ALU_ARGC_SRC1C_YZX 24 2041# define R300_ALU_ARGC_SRC2C_YZX 25 2042# define R300_ALU_ARGC_SRC0C_ZXY 26 2043# define R300_ALU_ARGC_SRC1C_ZXY 27 2044# define R300_ALU_ARGC_SRC2C_ZXY 28 2045# define R300_ALU_ARGC_SRC0CA_WZY 29 2046# define R300_ALU_ARGC_SRC1CA_WZY 30 2047# define R300_ALU_ARGC_SRC2CA_WZY 31 2048# define R300_RGB_SWIZA(x) ((x) << 0) 2049# define R300_RGB_SWIZB(x) ((x) << 7) 2050# define R300_RGB_SWIZC(x) ((x) << 14) 2051 2052# define R300_ALU_ARG0C_SHIFT 0 2053# define R300_ALU_ARG0C_MASK (31 << 0) 2054# define R300_ALU_ARG0C_NOP (0 << 5) 2055# define R300_ALU_ARG0C_NEG (1 << 5) 2056# define R300_ALU_ARG0C_ABS (2 << 5) 2057# define R300_ALU_ARG0C_NAB (3 << 5) 2058# define R300_ALU_ARG1C_SHIFT 7 2059# define R300_ALU_ARG1C_MASK (31 << 7) 2060# define R300_ALU_ARG1C_NOP (0 << 12) 2061# define R300_ALU_ARG1C_NEG (1 << 12) 2062# define R300_ALU_ARG1C_ABS (2 << 12) 2063# define R300_ALU_ARG1C_NAB (3 << 12) 2064# define R300_ALU_ARG2C_SHIFT 14 2065# define R300_ALU_ARG2C_MASK (31 << 14) 2066# define R300_ALU_ARG2C_NOP (0 << 19) 2067# define R300_ALU_ARG2C_NEG (1 << 19) 2068# define R300_ALU_ARG2C_ABS (2 << 19) 2069# define R300_ALU_ARG2C_NAB (3 << 19) 2070# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) 2071# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) 2072# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) 2073# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) 2074 2075# define R300_ALU_OUTC_MAD (0 << 23) 2076# define R300_ALU_OUTC_DP3 (1 << 23) 2077# define R300_ALU_OUTC_DP4 (2 << 23) 2078# define R300_ALU_OUTC_D2A (3 << 23) 2079# define R300_ALU_OUTC_MIN (4 << 23) 2080# define R300_ALU_OUTC_MAX (5 << 23) 2081# define R300_ALU_OUTC_CND (7 << 23) 2082# define R300_ALU_OUTC_CMP (8 << 23) 2083# define R300_ALU_OUTC_FRC (9 << 23) 2084# define R300_ALU_OUTC_REPL_ALPHA (10 << 23) 2085 2086# define R300_ALU_OUTC_MOD_SHIFT 27 2087# define R300_ALU_OUTC_MOD_NOP (0 << R300_ALU_OUTC_MOD_SHIFT) 2088# define R300_ALU_OUTC_MOD_MUL2 (1 << R300_ALU_OUTC_MOD_SHIFT) 2089# define R300_ALU_OUTC_MOD_MUL4 (2 << R300_ALU_OUTC_MOD_SHIFT) 2090# define R300_ALU_OUTC_MOD_MUL8 (3 << R300_ALU_OUTC_MOD_SHIFT) 2091# define R300_ALU_OUTC_MOD_DIV2 (4 << R300_ALU_OUTC_MOD_SHIFT) 2092# define R300_ALU_OUTC_MOD_DIV4 (5 << R300_ALU_OUTC_MOD_SHIFT) 2093# define R300_ALU_OUTC_MOD_DIV8 (6 << R300_ALU_OUTC_MOD_SHIFT) 2094 2095# define R300_ALU_OUTC_CLAMP (1 << 30) 2096# define R300_ALU_INSERT_NOP (1 << 31) 2097 2098#define R300_US_ALU_ALPHA_INST_0 0x49C0 2099# define R300_ALU_ARGA_SRC0C_X 0 2100# define R300_ALU_ARGA_SRC0C_Y 1 2101# define R300_ALU_ARGA_SRC0C_Z 2 2102# define R300_ALU_ARGA_SRC1C_X 3 2103# define R300_ALU_ARGA_SRC1C_Y 4 2104# define R300_ALU_ARGA_SRC1C_Z 5 2105# define R300_ALU_ARGA_SRC2C_X 6 2106# define R300_ALU_ARGA_SRC2C_Y 7 2107# define R300_ALU_ARGA_SRC2C_Z 8 2108# define R300_ALU_ARGA_SRC0A 9 2109# define R300_ALU_ARGA_SRC1A 10 2110# define R300_ALU_ARGA_SRC2A 11 2111# define R300_ALU_ARGA_SRCP_X 12 2112# define R300_ALU_ARGA_SRCP_Y 13 2113# define R300_ALU_ARGA_SRCP_Z 14 2114# define R300_ALU_ARGA_SRCP_W 15 2115# define R300_ALU_ARGA_ZERO 16 2116# define R300_ALU_ARGA_ONE 17 2117# define R300_ALU_ARGA_HALF 18 2118# define R300_ALPHA_SWIZA(x) ((x) << 0) 2119# define R300_ALPHA_SWIZB(x) ((x) << 7) 2120# define R300_ALPHA_SWIZC(x) ((x) << 14) 2121 2122# define R300_ALU_ARG0A_SHIFT 0 2123# define R300_ALU_ARG0A_MASK (31 << 0) 2124# define R300_ALU_ARG0A_NOP (0 << 5) 2125# define R300_ALU_ARG0A_NEG (1 << 5) 2126# define R300_ALU_ARG0A_ABS (2 << 5) 2127# define R300_ALU_ARG0A_NAB (3 << 5) 2128# define R300_ALU_ARG1A_SHIFT 7 2129# define R300_ALU_ARG1A_MASK (31 << 7) 2130# define R300_ALU_ARG1A_NOP (0 << 12) 2131# define R300_ALU_ARG1A_NEG (1 << 12) 2132# define R300_ALU_ARG1A_ABS (2 << 12) 2133# define R300_ALU_ARG1A_NAB (3 << 12) 2134# define R300_ALU_ARG2A_SHIFT 14 2135# define R300_ALU_ARG2A_MASK (31 << 14) 2136# define R300_ALU_ARG2A_NOP (0 << 19) 2137# define R300_ALU_ARG2A_NEG (1 << 19) 2138# define R300_ALU_ARG2A_ABS (2 << 19) 2139# define R300_ALU_ARG2A_NAB (3 << 19) 2140# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) 2141# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) 2142# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) 2143# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) 2144 2145# define R300_ALU_OUTA_MAD (0 << 23) 2146# define R300_ALU_OUTA_DP4 (1 << 23) 2147# define R300_ALU_OUTA_MIN (2 << 23) 2148# define R300_ALU_OUTA_MAX (3 << 23) 2149# define R300_ALU_OUTA_CND (5 << 23) 2150# define R300_ALU_OUTA_CMP (6 << 23) 2151# define R300_ALU_OUTA_FRC (7 << 23) 2152# define R300_ALU_OUTA_EX2 (8 << 23) 2153# define R300_ALU_OUTA_LG2 (9 << 23) 2154# define R300_ALU_OUTA_RCP (10 << 23) 2155# define R300_ALU_OUTA_RSQ (11 << 23) 2156 2157# define R300_ALU_OUTA_MOD_NOP (0 << 27) 2158# define R300_ALU_OUTA_MOD_MUL2 (1 << 27) 2159# define R300_ALU_OUTA_MOD_MUL4 (2 << 27) 2160# define R300_ALU_OUTA_MOD_MUL8 (3 << 27) 2161# define R300_ALU_OUTA_MOD_DIV2 (4 << 27) 2162# define R300_ALU_OUTA_MOD_DIV4 (5 << 27) 2163# define R300_ALU_OUTA_MOD_DIV8 (6 << 27) 2164 2165# define R300_ALU_OUTA_CLAMP (1 << 30) 2166/* END: Fragment program instruction set */ 2167 2168/* R4xx extended fragment shader registers. */ 2169#define R400_US_ALU_EXT_ADDR_0 0x4ac0 /* up to 63 (0x4bbc) */ 2170# define R400_ADDR_EXT_RGB_MSB_BIT(x) (1 << (x)) 2171# define R400_ADDRD_EXT_RGB_MSB_BIT 0x08 2172# define R400_ADDR_EXT_A_MSB_BIT(x) (1 << ((x) + 4)) 2173# define R400_ADDRD_EXT_A_MSB_BIT 0x80 2174 2175#define R400_US_CODE_BANK 0x46b8 2176# define R400_BANK_SHIFT 0 2177# define R400_BANK_MASK 0xf 2178# define R400_R390_MODE_ENABLE (1 << 4) 2179#define R400_US_CODE_EXT 0x46bc 2180# define R400_ALU_OFFSET_MSB_SHIFT 0 2181# define R400_ALU_OFFSET_MSB_MASK (0x7 << 0) 2182# define R400_ALU_SIZE_MSB_SHIFT 3 2183# define R400_ALU_SIZE_MSB_MASK (0x7 << 3) 2184# define R400_ALU_START0_MSB_SHIFT 6 2185# define R400_ALU_START0_MSB_MASK (0x7 << 6) 2186# define R400_ALU_SIZE0_MSB_SHIFT 9 2187# define R400_ALU_SIZE0_MSB_MASK (0x7 << 9) 2188# define R400_ALU_START1_MSB_SHIFT 12 2189# define R400_ALU_START1_MSB_MASK (0x7 << 12) 2190# define R400_ALU_SIZE1_MSB_SHIFT 15 2191# define R400_ALU_SIZE1_MSB_MASK (0x7 << 15) 2192# define R400_ALU_START2_MSB_SHIFT 18 2193# define R400_ALU_START2_MSB_MASK (0x7 << 18) 2194# define R400_ALU_SIZE2_MSB_SHIFT 21 2195# define R400_ALU_SIZE2_MSB_MASK (0x7 << 21) 2196# define R400_ALU_START3_MSB_SHIFT 24 2197# define R400_ALU_START3_MSB_MASK (0x7 << 24) 2198# define R400_ALU_SIZE3_MSB_SHIFT 27 2199# define R400_ALU_SIZE3_MSB_MASK (0x7 << 27) 2200/* END: R4xx extended fragment shader registers. */ 2201 2202/* Fog: Fog Blending Enable */ 2203#define R300_FG_FOG_BLEND 0x4bc0 2204# define R300_FG_FOG_BLEND_DISABLE (0 << 0) 2205# define R300_FG_FOG_BLEND_ENABLE (1 << 0) 2206# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1) 2207# define R300_FG_FOG_BLEND_FN_EXP (1 << 1) 2208# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1) 2209# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1) 2210# define R300_FG_FOG_BLEND_FN_MASK (3 << 1) 2211 2212/* Fog: Red Component of Fog Color */ 2213#define R300_FG_FOG_COLOR_R 0x4bc8 2214/* Fog: Green Component of Fog Color */ 2215#define R300_FG_FOG_COLOR_G 0x4bcc 2216/* Fog: Blue Component of Fog Color */ 2217#define R300_FG_FOG_COLOR_B 0x4bd0 2218# define R300_FG_FOG_COLOR_MASK 0x000003ff 2219 2220/* Fog: Constant Factor for Fog Blending */ 2221#define R300_FG_FOG_FACTOR 0x4bc4 2222# define FG_FOG_FACTOR_MASK 0x000003ff 2223 2224/* Fog: Alpha function */ 2225#define R300_FG_ALPHA_FUNC 0x4bd4 2226# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff 2227# define R300_FG_ALPHA_FUNC_NEVER (0 << 8) 2228# define R300_FG_ALPHA_FUNC_LESS (1 << 8) 2229# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8) 2230# define R300_FG_ALPHA_FUNC_LE (3 << 8) 2231# define R300_FG_ALPHA_FUNC_GREATER (4 << 8) 2232# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8) 2233# define R300_FG_ALPHA_FUNC_GE (6 << 8) 2234# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8) 2235# define R300_ALPHA_TEST_OP_MASK (7 << 8) 2236# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11) 2237# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11) 2238 2239# define R500_FG_ALPHA_FUNC_10BIT (0 << 12) 2240# define R500_FG_ALPHA_FUNC_8BIT (1 << 12) 2241 2242# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16) 2243# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16) 2244# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17) 2245# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17) 2246 2247# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20) 2248# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20) 2249 2250# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24) 2251# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */ 2252# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25) 2253# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25) 2254 2255# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28) 2256# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28) 2257 2258 2259/* Fog: Where does the depth come from? */ 2260#define R300_FG_DEPTH_SRC 0x4bd8 2261# define R300_FG_DEPTH_SRC_SCAN (0 << 0) 2262# define R300_FG_DEPTH_SRC_SHADER (1 << 0) 2263 2264/* Fog: Alpha Compare Value */ 2265#define R500_FG_ALPHA_VALUE 0x4be0 2266# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff 2267 2268#define RV530_FG_ZBREG_DEST 0x4be8 2269# define RV530_FG_ZBREG_DEST_PIPE_SELECT_0 (1 << 0) 2270# define RV530_FG_ZBREG_DEST_PIPE_SELECT_1 (1 << 1) 2271# define RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL (3 << 0) 2272/* gap */ 2273 2274/* Fragment program parameters in 7.16 floating point */ 2275#define R300_PFS_PARAM_0_X 0x4C00 2276#define R300_PFS_PARAM_0_Y 0x4C04 2277#define R300_PFS_PARAM_0_Z 0x4C08 2278#define R300_PFS_PARAM_0_W 0x4C0C 2279/* last consts */ 2280#define R300_PFS_PARAM_31_X 0x4DF0 2281#define R300_PFS_PARAM_31_Y 0x4DF4 2282#define R300_PFS_PARAM_31_Z 0x4DF8 2283#define R300_PFS_PARAM_31_W 0x4DFC 2284 2285/* Unpipelined. */ 2286#define R300_RB3D_CCTL 0x4e00 2287# define R300_RB3D_CCTL_NUM_MULTIWRITES(x) (MAX2(((x)-1), 0) << 5) 2288# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5) 2289# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5) 2290# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5) 2291# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5) 2292# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7) 2293# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7) 2294# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9) 2295# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9) 2296# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10) 2297# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10) 2298/* reserved */ 2299# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12) 2300# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12) 2301# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13) 2302# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13) 2303# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14) 2304# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14) 2305 2306 2307/* Notes: 2308 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in 2309 * the application 2310 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND 2311 * are set to the same 2312 * function (both registers are always set up completely in any case) 2313 * - Most blend flags are simply copied from R200 and not tested yet 2314 */ 2315#define R300_RB3D_CBLEND 0x4E04 2316#define R300_RB3D_ABLEND 0x4E08 2317/* the following only appear in CBLEND */ 2318# define R300_ALPHA_BLEND_ENABLE (1 << 0) 2319# define R300_SEPARATE_ALPHA_ENABLE (1 << 1) 2320# define R300_READ_ENABLE (1 << 2) 2321# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3) 2322# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3) 2323# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3) 2324# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3) 2325# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3) 2326# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3) 2327# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3) 2328# define R500_SRC_ALPHA_0_NO_READ (1 << 30) 2329# define R500_SRC_ALPHA_1_NO_READ (1 << 31) 2330 2331/* the following are shared between CBLEND and ABLEND */ 2332# define R300_FCN_MASK (3 << 12) 2333# define R300_COMB_FCN_ADD_CLAMP (0 << 12) 2334# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) 2335# define R300_COMB_FCN_SUB_CLAMP (2 << 12) 2336# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) 2337# define R300_COMB_FCN_MIN (4 << 12) 2338# define R300_COMB_FCN_MAX (5 << 12) 2339# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) 2340# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) 2341# define R300_BLEND_GL_ZERO (32) 2342# define R300_BLEND_GL_ONE (33) 2343# define R300_BLEND_GL_SRC_COLOR (34) 2344# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) 2345# define R300_BLEND_GL_DST_COLOR (36) 2346# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) 2347# define R300_BLEND_GL_SRC_ALPHA (38) 2348# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) 2349# define R300_BLEND_GL_DST_ALPHA (40) 2350# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) 2351# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) 2352# define R300_BLEND_GL_CONST_COLOR (43) 2353# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) 2354# define R300_BLEND_GL_CONST_ALPHA (45) 2355# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) 2356# define R300_BLEND_MASK (63) 2357# define R300_SRC_BLEND_SHIFT (16) 2358# define R300_DST_BLEND_SHIFT (24) 2359 2360/* Constant color used by the blender. Pipelined through the blender. 2361 * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE, 2362 * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead. 2363 */ 2364#define R300_RB3D_BLEND_COLOR 0x4E10 2365 2366 2367/* 3D Color Channel Mask. If all the channels used in the current color format 2368 * are disabled, then the cb will discard all the incoming quads. Pipelined 2369 * through the blender. 2370 */ 2371#define RB3D_COLOR_CHANNEL_MASK 0x4E0C 2372# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 (1 << 0) 2373# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1) 2374# define RB3D_COLOR_CHANNEL_MASK_RED_MASK0 (1 << 2) 2375# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3) 2376# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1 (1 << 4) 2377# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5) 2378# define RB3D_COLOR_CHANNEL_MASK_RED_MASK1 (1 << 6) 2379# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7) 2380# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2 (1 << 8) 2381# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9) 2382# define RB3D_COLOR_CHANNEL_MASK_RED_MASK2 (1 << 10) 2383# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11) 2384# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3 (1 << 12) 2385# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13) 2386# define RB3D_COLOR_CHANNEL_MASK_RED_MASK3 (1 << 14) 2387# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15) 2388 2389/* Clear color that is used when the color mask is set to 00. Unpipelined. 2390 * Program this register with a 32-bit value in ARGB8888 or ARGB2101010 2391 * formats, ignoring the fields. 2392 */ 2393#define RB3D_COLOR_CLEAR_VALUE 0x4e14 2394 2395/* gap */ 2396 2397/* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */ 2398#define RB3D_CLRCMP_CLR 0x4e20 2399 2400/* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */ 2401#define RB3D_CLRCMP_MSK 0x4e24 2402 2403/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */ 2404#define R300_RB3D_COLOROFFSET0 0x4E28 2405# define R300_COLOROFFSET_MASK 0xFFFFFFE0 2406/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */ 2407#define R300_RB3D_COLOROFFSET1 0x4E2C 2408/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */ 2409#define R300_RB3D_COLOROFFSET2 0x4E30 2410/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */ 2411#define R300_RB3D_COLOROFFSET3 0x4E34 2412 2413/* Color buffer format and tiling control for all the multibuffers and the 2414 * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any 2415 * of the registers are changed. 2416 * 2417 * Bit 16: Larger tiles 2418 * Bit 17: 4x2 tiles 2419 * Bit 18: Extremely weird tile like, but some pixels duplicated? 2420 */ 2421#define R300_RB3D_COLORPITCH0 0x4E38 2422# define R300_COLORPITCH_MASK 0x00003FFE 2423# define R300_COLOR_TILE_DISABLE (0 << 16) 2424# define R300_COLOR_TILE_ENABLE (1 << 16) 2425# define R300_COLOR_TILE(x) ((x) << 16) 2426# define R300_COLOR_MICROTILE_DISABLE (0 << 17) 2427# define R300_COLOR_MICROTILE_ENABLE (1 << 17) 2428# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */ 2429# define R300_COLOR_MICROTILE(x) ((x) << 17) 2430# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19) 2431# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19) 2432# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19) 2433# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19) 2434# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21) 2435# define R500_COLOR_FORMAT_UV1010 (1 << 21) 2436# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */ 2437# define R300_COLOR_FORMAT_ARGB1555 (3 << 21) 2438# define R300_COLOR_FORMAT_RGB565 (4 << 21) 2439# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21) 2440# define R300_COLOR_FORMAT_ARGB8888 (6 << 21) 2441# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21) 2442/* reserved */ 2443# define R300_COLOR_FORMAT_I8 (9 << 21) 2444# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21) 2445# define R300_COLOR_FORMAT_VYUY (11 << 21) 2446# define R300_COLOR_FORMAT_YVYU (12 << 21) 2447# define R300_COLOR_FORMAT_UV88 (13 << 21) 2448# define R500_COLOR_FORMAT_I10 (14 << 21) 2449# define R300_COLOR_FORMAT_ARGB4444 (15 << 21) 2450#define R300_RB3D_COLORPITCH1 0x4E3C 2451#define R300_RB3D_COLORPITCH2 0x4E40 2452#define R300_RB3D_COLORPITCH3 0x4E44 2453 2454/* gap */ 2455 2456/* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then 2457 * a flush or free will not occur upon a write to this register, but a sync 2458 * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE 2459 * are zero but DC_FINISH is one, then a sync will be sent immediately -- the 2460 * cb will not wait for all the previous operations to complete before sending 2461 * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to 2462 * zero. 2463 * 2464 * Set to 0A before 3D operations, set to 02 afterwards. 2465 */ 2466#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 2467# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0) 2468# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0) 2469# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0) 2470# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0) 2471# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2) 2472# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2) 2473# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2) 2474# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2) 2475# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4) 2476# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4) 2477 2478#define R300_RB3D_DITHER_CTL 0x4E50 2479# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0) 2480# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0) 2481# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0) 2482/* reserved */ 2483# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2) 2484# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2) 2485# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2) 2486/* reserved */ 2487 2488/* Resolve buffer destination address. The cache must be empty before changing 2489 * this register if the cb is in resolve mode. Unpipelined 2490 */ 2491#define R300_RB3D_AARESOLVE_OFFSET 0x4e80 2492# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5 2493# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */ 2494 2495/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before 2496 * changing this register if the cb is in resolve mode. Unpipelined 2497 */ 2498#define R300_RB3D_AARESOLVE_PITCH 0x4e84 2499# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1 2500# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */ 2501 2502/* Resolve Buffer Control. Unpipelined */ 2503#define R300_RB3D_AARESOLVE_CTL 0x4e88 2504# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0) 2505# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0) 2506# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1) 2507# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1) 2508# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2) 2509# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2) 2510 2511 2512/* Discard src pixels less than or equal to threshold. */ 2513#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0 2514/* Discard src pixels greater than or equal to threshold. */ 2515#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4 2516# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0 2517# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff 2518# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8 2519# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00 2520# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16 2521# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000 2522# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24 2523# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000 2524 2525/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */ 2526#define R300_RB3D_ROPCNTL 0x4e18 2527# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004 2528# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8) 2529# define R300_RB3D_ROPCNTL_ROP_SHIFT 8 2530 2531/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */ 2532#define R300_RB3D_CLRCMP_FLIPE 0x4e1c 2533 2534/* Sets the fifo sizes */ 2535#define R500_RB3D_FIFO_SIZE 0x4ef4 2536# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0) 2537# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0) 2538# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0) 2539# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0) 2540 2541/* Constant color used by the blender. Pipelined through the blender. */ 2542#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 2543# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff 2544# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0 2545# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000 2546# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16 2547 2548/* Constant color used by the blender. Pipelined through the blender. */ 2549#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc 2550# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff 2551# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0 2552# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000 2553# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16 2554 2555/* gap */ 2556/* There seems to be no "write only" setting, so use Z-test = ALWAYS 2557 * for this. 2558 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 2559 */ 2560#define R300_ZB_CNTL 0x4F00 2561# define R300_STENCIL_ENABLE (1 << 0) 2562# define R300_Z_ENABLE (1 << 1) 2563# define R300_Z_WRITE_ENABLE (1 << 2) 2564# define R300_Z_SIGNED_COMPARE (1 << 3) 2565# define R300_STENCIL_FRONT_BACK (1 << 4) 2566# define R500_STENCIL_ZSIGNED_MAGNITUDE (1 << 5) 2567# define R500_STENCIL_REFMASK_FRONT_BACK (1 << 6) 2568 2569#define R300_ZB_ZSTENCILCNTL 0x4f04 2570 /* functions */ 2571# define R300_ZS_NEVER 0 2572# define R300_ZS_LESS 1 2573# define R300_ZS_LEQUAL 2 2574# define R300_ZS_EQUAL 3 2575# define R300_ZS_GEQUAL 4 2576# define R300_ZS_GREATER 5 2577# define R300_ZS_NOTEQUAL 6 2578# define R300_ZS_ALWAYS 7 2579# define R300_ZS_MASK 7 2580 /* operations */ 2581# define R300_ZS_KEEP 0 2582# define R300_ZS_ZERO 1 2583# define R300_ZS_REPLACE 2 2584# define R300_ZS_INCR 3 2585# define R300_ZS_DECR 4 2586# define R300_ZS_INVERT 5 2587# define R300_ZS_INCR_WRAP 6 2588# define R300_ZS_DECR_WRAP 7 2589# define R300_Z_FUNC_SHIFT 0 2590 /* front and back refer to operations done for front 2591 and back faces, i.e. separate stencil function support */ 2592# define R300_S_FRONT_FUNC_SHIFT 3 2593# define R300_S_FRONT_SFAIL_OP_SHIFT 6 2594# define R300_S_FRONT_ZPASS_OP_SHIFT 9 2595# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 2596# define R300_S_BACK_FUNC_SHIFT 15 2597# define R300_S_BACK_SFAIL_OP_SHIFT 18 2598# define R300_S_BACK_ZPASS_OP_SHIFT 21 2599# define R300_S_BACK_ZFAIL_OP_SHIFT 24 2600 2601#define R300_ZB_STENCILREFMASK 0x4f08 2602# define R300_STENCILREF_SHIFT 0 2603# define R300_STENCILREF_MASK 0x000000ff 2604# define R300_STENCILMASK_SHIFT 8 2605# define R300_STENCILMASK_MASK 0x0000ff00 2606# define R300_STENCILWRITEMASK_SHIFT 16 2607# define R300_STENCILWRITEMASK_MASK 0x00ff0000 2608 2609/* gap */ 2610 2611#define R300_ZB_FORMAT 0x4f10 2612# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) 2613# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) 2614# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) 2615/* reserved up to (15 << 0) */ 2616# define R300_INVERT_13E3_LEADING_ONES (0 << 4) 2617# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) 2618 2619#define R300_ZB_ZTOP 0x4F14 2620# define R300_ZTOP_DISABLE (0 << 0) 2621# define R300_ZTOP_ENABLE (1 << 0) 2622 2623/* gap */ 2624 2625#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 2626# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) 2627# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) 2628# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) 2629# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) 2630# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) 2631# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) 2632 2633#define R300_ZB_BW_CNTL 0x4f1c 2634# define R300_HIZ_DISABLE (0 << 0) 2635# define R300_HIZ_ENABLE (1 << 0) 2636# define R300_HIZ_MAX (0 << 1) 2637# define R300_HIZ_MIN (1 << 1) 2638# define R300_FAST_FILL_DISABLE (0 << 2) 2639# define R300_FAST_FILL_ENABLE (1 << 2) 2640# define R300_RD_COMP_DISABLE (0 << 3) 2641# define R300_RD_COMP_ENABLE (1 << 3) 2642# define R300_WR_COMP_DISABLE (0 << 4) 2643# define R300_WR_COMP_ENABLE (1 << 4) 2644# define R300_ZB_CB_CLEAR_RMW (0 << 5) 2645# define R300_ZB_CB_CLEAR_CACHE_LINE_WRITE_ONLY (1 << 5) 2646# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) 2647# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) 2648 2649# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) 2650# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) 2651# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) 2652# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) 2653 2654# define R500_BMASK_ENABLE (0 << 10) 2655# define R500_BMASK_DISABLE (1 << 10) 2656# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) 2657# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) 2658# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) 2659# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) 2660# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) 2661# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) 2662# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) 2663# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) 2664# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) 2665# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) 2666# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) 2667# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) 2668# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) 2669# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) 2670# define R500_PEQ_PACKING_DISABLE (0 << 18) 2671# define R500_PEQ_PACKING_ENABLE (1 << 18) 2672# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) 2673# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) 2674 2675 2676/* gap */ 2677 2678/* Z Buffer Address Offset. 2679 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. 2680 */ 2681#define R300_ZB_DEPTHOFFSET 0x4f20 2682 2683/* Z Buffer Pitch and Endian Control */ 2684#define R300_ZB_DEPTHPITCH 0x4f24 2685# define R300_DEPTHPITCH_MASK 0x00003FFC 2686# define R300_DEPTHMACROTILE_DISABLE (0 << 16) 2687# define R300_DEPTHMACROTILE_ENABLE (1 << 16) 2688# define R300_DEPTHMACROTILE(x) ((x) << 16) 2689# define R300_DEPTHMICROTILE_LINEAR (0 << 17) 2690# define R300_DEPTHMICROTILE_TILED (1 << 17) 2691# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) 2692# define R300_DEPTHMICROTILE(x) ((x) << 17) 2693# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) 2694# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) 2695# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) 2696# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) 2697 2698/* Z Buffer Clear Value */ 2699#define R300_ZB_DEPTHCLEARVALUE 0x4f28 2700 2701/* Z Mask RAM is a Z compression buffer. 2702 * Each dword of the Z Mask contains compression info for 16 4x4 pixel blocks, 2703 * that is 2 bits for each block. 2704 * On chips with 2 Z pipes, every other dword maps to a different pipe. 2705 */ 2706 2707/* The dword offset into Z mask RAM (bits 18:4) */ 2708#define R300_ZB_ZMASK_OFFSET 0x4f30 2709 2710/* Z Mask Pitch. */ 2711#define R300_ZB_ZMASK_PITCH 0x4f34 2712 2713/* Access to Z Mask RAM in a manner similar to HiZ RAM. 2714 * The indices are autoincrementing. */ 2715#define R300_ZB_ZMASK_WRINDEX 0x4f38 2716#define R300_ZB_ZMASK_DWORD 0x4f3c 2717#define R300_ZB_ZMASK_RDINDEX 0x4f40 2718 2719/* Hierarchical Z Memory Offset */ 2720#define R300_ZB_HIZ_OFFSET 0x4f44 2721 2722/* Hierarchical Z Write Index */ 2723#define R300_ZB_HIZ_WRINDEX 0x4f48 2724 2725/* Hierarchical Z Data */ 2726#define R300_ZB_HIZ_DWORD 0x4f4c 2727 2728/* Hierarchical Z Read Index */ 2729#define R300_ZB_HIZ_RDINDEX 0x4f50 2730 2731/* Hierarchical Z Pitch */ 2732#define R300_ZB_HIZ_PITCH 0x4f54 2733 2734/* Z Buffer Z Pass Counter Data */ 2735#define R300_ZB_ZPASS_DATA 0x4f58 2736 2737/* Z Buffer Z Pass Counter Address */ 2738#define R300_ZB_ZPASS_ADDR 0x4f5c 2739 2740/* Depth buffer X and Y coordinate offset */ 2741#define R300_ZB_DEPTHXY_OFFSET 0x4f60 2742# define R300_DEPTHX_OFFSET_SHIFT 1 2743# define R300_DEPTHX_OFFSET_MASK 0x000007FE 2744# define R300_DEPTHY_OFFSET_SHIFT 17 2745# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 2746 2747/* Sets the fifo sizes */ 2748#define R500_ZB_FIFO_SIZE 0x4fd0 2749# define R500_OP_FIFO_SIZE_FULL (0 << 0) 2750# define R500_OP_FIFO_SIZE_HALF (1 << 0) 2751# define R500_OP_FIFO_SIZE_QUATER (2 << 0) 2752# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) 2753 2754/* Stencil Reference Value and Mask for backfacing quads */ 2755/* R300_ZB_STENCILREFMASK handles front face */ 2756#define R500_ZB_STENCILREFMASK_BF 0x4fd4 2757# define R500_STENCILREF_SHIFT 0 2758# define R500_STENCILREF_MASK 0x000000ff 2759# define R500_STENCILMASK_SHIFT 8 2760# define R500_STENCILMASK_MASK 0x0000ff00 2761# define R500_STENCILWRITEMASK_SHIFT 16 2762# define R500_STENCILWRITEMASK_MASK 0x00ff0000 2763 2764/** 2765 * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION 2766 * 2767 * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector 2768 * Engine instruction or a Math Engine instruction. 2769 */ 2770 2771/*\{*/ 2772 2773enum { 2774 /* R3XX */ 2775 VECTOR_NO_OP = 0, 2776 VE_DOT_PRODUCT = 1, 2777 VE_MULTIPLY = 2, 2778 VE_ADD = 3, 2779 VE_MULTIPLY_ADD = 4, 2780 VE_DISTANCE_VECTOR = 5, 2781 VE_FRACTION = 6, 2782 VE_MAXIMUM = 7, 2783 VE_MINIMUM = 8, 2784 VE_SET_GREATER_THAN_EQUAL = 9, 2785 VE_SET_LESS_THAN = 10, 2786 VE_MULTIPLYX2_ADD = 11, 2787 VE_MULTIPLY_CLAMP = 12, 2788 VE_FLT2FIX_DX = 13, 2789 VE_FLT2FIX_DX_RND = 14, 2790 /* R5XX */ 2791 VE_PRED_SET_EQ_PUSH = 15, 2792 VE_PRED_SET_GT_PUSH = 16, 2793 VE_PRED_SET_GTE_PUSH = 17, 2794 VE_PRED_SET_NEQ_PUSH = 18, 2795 VE_COND_WRITE_EQ = 19, 2796 VE_COND_WRITE_GT = 20, 2797 VE_COND_WRITE_GTE = 21, 2798 VE_COND_WRITE_NEQ = 22, 2799 VE_COND_MUX_EQ = 23, 2800 VE_COND_MUX_GT = 24, 2801 VE_COND_MUX_GTE = 25, 2802 VE_SET_GREATER_THAN = 26, 2803 VE_SET_EQUAL = 27, 2804 VE_SET_NOT_EQUAL = 28 2805}; 2806 2807enum { 2808 /* R3XX */ 2809 MATH_NO_OP = 0, 2810 ME_EXP_BASE2_DX = 1, 2811 ME_LOG_BASE2_DX = 2, 2812 ME_EXP_BASEE_FF = 3, 2813 ME_LIGHT_COEFF_DX = 4, 2814 ME_POWER_FUNC_FF = 5, 2815 ME_RECIP_DX = 6, 2816 ME_RECIP_FF = 7, 2817 ME_RECIP_SQRT_DX = 8, 2818 ME_RECIP_SQRT_FF = 9, 2819 ME_MULTIPLY = 10, 2820 ME_EXP_BASE2_FULL_DX = 11, 2821 ME_LOG_BASE2_FULL_DX = 12, 2822 ME_POWER_FUNC_FF_CLAMP_B = 13, 2823 ME_POWER_FUNC_FF_CLAMP_B1 = 14, 2824 ME_POWER_FUNC_FF_CLAMP_01 = 15, 2825 ME_SIN = 16, 2826 ME_COS = 17, 2827 /* R5XX */ 2828 ME_LOG_BASE2_IEEE = 18, 2829 ME_RECIP_IEEE = 19, 2830 ME_RECIP_SQRT_IEEE = 20, 2831 ME_PRED_SET_EQ = 21, 2832 ME_PRED_SET_GT = 22, 2833 ME_PRED_SET_GTE = 23, 2834 ME_PRED_SET_NEQ = 24, 2835 ME_PRED_SET_CLR = 25, 2836 ME_PRED_SET_INV = 26, 2837 ME_PRED_SET_POP = 27, 2838 ME_PRED_SET_RESTORE = 28 2839}; 2840 2841enum { 2842 /* R3XX */ 2843 PVS_MACRO_OP_2CLK_MADD = 0, 2844 PVS_MACRO_OP_2CLK_M2X_ADD = 1 2845}; 2846 2847enum { 2848 PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */ 2849 PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */ 2850 PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */ 2851 PVS_SRC_REG_ALT_TEMPORARY = 3 /* Alternate Intermediate Storage */ 2852}; 2853 2854enum { 2855 PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */ 2856 PVS_DST_REG_A0 = 1, /* Address Register Storage */ 2857 PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */ 2858 PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */ 2859 PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */ 2860 PVS_DST_REG_INPUT = 5 /* Output Memory & Replicate X to all channels */ 2861}; 2862 2863enum { 2864 PVS_SRC_SELECT_X = 0, /* Select X Component */ 2865 PVS_SRC_SELECT_Y = 1, /* Select Y Component */ 2866 PVS_SRC_SELECT_Z = 2, /* Select Z Component */ 2867 PVS_SRC_SELECT_W = 3, /* Select W Component */ 2868 PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */ 2869 PVS_SRC_SELECT_FORCE_1 = 5 /* Force Component to 1.0 */ 2870}; 2871 2872/* PVS Opcode & Destination Operand Description */ 2873 2874enum { 2875 PVS_DST_OPCODE_MASK = 0x3f, 2876 PVS_DST_OPCODE_SHIFT = 0, 2877 PVS_DST_MATH_INST_MASK = 0x1, 2878 PVS_DST_MATH_INST_SHIFT = 6, 2879 PVS_DST_MACRO_INST_MASK = 0x1, 2880 PVS_DST_MACRO_INST_SHIFT = 7, 2881 PVS_DST_REG_TYPE_MASK = 0xf, 2882 PVS_DST_REG_TYPE_SHIFT = 8, 2883 PVS_DST_ADDR_MODE_1_MASK = 0x1, 2884 PVS_DST_ADDR_MODE_1_SHIFT = 12, 2885 PVS_DST_OFFSET_MASK = 0x7f, 2886 PVS_DST_OFFSET_SHIFT = 13, 2887 PVS_DST_WE_X_MASK = 0x1, 2888 PVS_DST_WE_X_SHIFT = 20, 2889 PVS_DST_WE_Y_MASK = 0x1, 2890 PVS_DST_WE_Y_SHIFT = 21, 2891 PVS_DST_WE_Z_MASK = 0x1, 2892 PVS_DST_WE_Z_SHIFT = 22, 2893 PVS_DST_WE_W_MASK = 0x1, 2894 PVS_DST_WE_W_SHIFT = 23, 2895 PVS_DST_VE_SAT_MASK = 0x1, 2896 PVS_DST_VE_SAT_SHIFT = 24, 2897 PVS_DST_ME_SAT_MASK = 0x1, 2898 PVS_DST_ME_SAT_SHIFT = 25, 2899 PVS_DST_PRED_ENABLE_MASK = 0x1, 2900 PVS_DST_PRED_ENABLE_SHIFT = 26, 2901 PVS_DST_PRED_SENSE_MASK = 0x1, 2902 PVS_DST_PRED_SENSE_SHIFT = 27, 2903 PVS_DST_DUAL_MATH_OP_MASK = 0x3, 2904 PVS_DST_DUAL_MATH_OP_SHIFT = 27, 2905 PVS_DST_ADDR_SEL_MASK = 0x3, 2906 PVS_DST_ADDR_SEL_SHIFT = 29, 2907 PVS_DST_ADDR_MODE_0_MASK = 0x1, 2908 PVS_DST_ADDR_MODE_0_SHIFT = 31 2909}; 2910 2911/* PVS Source Operand Description */ 2912 2913enum { 2914 PVS_SRC_REG_TYPE_MASK = 0x3, 2915 PVS_SRC_REG_TYPE_SHIFT = 0, 2916 SPARE_0_MASK = 0x1, 2917 SPARE_0_SHIFT = 2, 2918 PVS_SRC_ABS_XYZW_MASK = 0x1, 2919 PVS_SRC_ABS_XYZW_SHIFT = 3, 2920 PVS_SRC_ADDR_MODE_0_MASK = 0x1, 2921 PVS_SRC_ADDR_MODE_0_SHIFT = 4, 2922 PVS_SRC_OFFSET_MASK = 0xff, 2923 PVS_SRC_OFFSET_SHIFT = 5, 2924 PVS_SRC_SWIZZLE_X_MASK = 0x7, 2925 PVS_SRC_SWIZZLE_X_SHIFT = 13, 2926 PVS_SRC_SWIZZLE_Y_MASK = 0x7, 2927 PVS_SRC_SWIZZLE_Y_SHIFT = 16, 2928 PVS_SRC_SWIZZLE_Z_MASK = 0x7, 2929 PVS_SRC_SWIZZLE_Z_SHIFT = 19, 2930 PVS_SRC_SWIZZLE_W_MASK = 0x7, 2931 PVS_SRC_SWIZZLE_W_SHIFT = 22, 2932 PVS_SRC_MODIFIER_X_MASK = 0x1, 2933 PVS_SRC_MODIFIER_X_SHIFT = 25, 2934 PVS_SRC_MODIFIER_Y_MASK = 0x1, 2935 PVS_SRC_MODIFIER_Y_SHIFT = 26, 2936 PVS_SRC_MODIFIER_Z_MASK = 0x1, 2937 PVS_SRC_MODIFIER_Z_SHIFT = 27, 2938 PVS_SRC_MODIFIER_W_MASK = 0x1, 2939 PVS_SRC_MODIFIER_W_SHIFT = 28, 2940 PVS_SRC_ADDR_SEL_MASK = 0x3, 2941 PVS_SRC_ADDR_SEL_SHIFT = 29, 2942 PVS_SRC_ADDR_MODE_1_MASK = 0x0, 2943 PVS_SRC_ADDR_MODE_1_SHIFT = 32 2944}; 2945 2946/*\}*/ 2947 2948#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class) \ 2949 (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \ 2950 | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \ 2951 | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \ 2952 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \ 2953 | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \ 2954 | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) 2955 2956#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \ 2957 (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \ 2958 | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \ 2959 | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \ 2960 | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \ 2961 | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \ 2962 | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \ 2963 | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT)) 2964 2965/* BEGIN: Packet 3 commands */ 2966 2967/* A primitive emission dword. */ 2968#define R300_PRIM_TYPE_NONE (0 << 0) 2969#define R300_PRIM_TYPE_POINT (1 << 0) 2970#define R300_PRIM_TYPE_LINE (2 << 0) 2971#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) 2972#define R300_PRIM_TYPE_TRI_LIST (4 << 0) 2973#define R300_PRIM_TYPE_TRI_FAN (5 << 0) 2974#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) 2975#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) 2976#define R300_PRIM_TYPE_RECT_LIST (8 << 0) 2977#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 2978#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 2979 /* GUESS (based on r200) */ 2980#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) 2981#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 2982#define R300_PRIM_TYPE_QUADS (13 << 0) 2983#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 2984#define R300_PRIM_TYPE_POLYGON (15 << 0) 2985#define R300_PRIM_TYPE_MASK 0xF 2986#define R300_PRIM_WALK_IND (1 << 4) 2987#define R300_PRIM_WALK_LIST (2 << 4) 2988#define R300_PRIM_WALK_RING (3 << 4) 2989#define R300_PRIM_WALK_MASK (3 << 4) 2990 /* GUESS (based on r200) */ 2991#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) 2992#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) 2993#define R300_PRIM_NUM_VERTICES_SHIFT 16 2994#define R300_PRIM_NUM_VERTICES_MASK 0xffff 2995 2996 2997 2998/* 2999 * The R500 unified shader (US) registers come in banks of 512 each, one 3000 * for each instruction slot in the shader. You can't touch them directly. 3001 * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive 3002 * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the 3003 * instruction is fully specified. 3004 */ 3005#define R500_US_ALU_ALPHA_INST_0 0xa800 3006# define R500_ALPHA_OP_MAD 0 3007# define R500_ALPHA_OP_DP 1 3008# define R500_ALPHA_OP_MIN 2 3009# define R500_ALPHA_OP_MAX 3 3010/* #define R500_ALPHA_OP_RESERVED 4 */ 3011# define R500_ALPHA_OP_CND 5 3012# define R500_ALPHA_OP_CMP 6 3013# define R500_ALPHA_OP_FRC 7 3014# define R500_ALPHA_OP_EX2 8 3015# define R500_ALPHA_OP_LN2 9 3016# define R500_ALPHA_OP_RCP 10 3017# define R500_ALPHA_OP_RSQ 11 3018# define R500_ALPHA_OP_SIN 12 3019# define R500_ALPHA_OP_COS 13 3020# define R500_ALPHA_OP_MDH 14 3021# define R500_ALPHA_OP_MDV 15 3022# define R500_ALPHA_ADDRD(x) ((x) << 4) 3023# define R500_ALPHA_ADDRD_REL (1 << 11) 3024# define R500_ALPHA_SEL_A_SHIFT 12 3025# define R500_ALPHA_SEL_A_SRC0 (0 << 12) 3026# define R500_ALPHA_SEL_A_SRC1 (1 << 12) 3027# define R500_ALPHA_SEL_A_SRC2 (2 << 12) 3028# define R500_ALPHA_SEL_A_SRCP (3 << 12) 3029# define R500_ALPHA_SWIZ_A_R (0 << 14) 3030# define R500_ALPHA_SWIZ_A_G (1 << 14) 3031# define R500_ALPHA_SWIZ_A_B (2 << 14) 3032# define R500_ALPHA_SWIZ_A_A (3 << 14) 3033# define R500_ALPHA_SWIZ_A_0 (4 << 14) 3034# define R500_ALPHA_SWIZ_A_HALF (5 << 14) 3035# define R500_ALPHA_SWIZ_A_1 (6 << 14) 3036/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ 3037# define R500_ALPHA_MOD_A_NOP (0 << 17) 3038# define R500_ALPHA_MOD_A_NEG (1 << 17) 3039# define R500_ALPHA_MOD_A_ABS (2 << 17) 3040# define R500_ALPHA_MOD_A_NAB (3 << 17) 3041# define R500_ALPHA_SEL_B_SHIFT 19 3042# define R500_ALPHA_SEL_B_SRC0 (0 << 19) 3043# define R500_ALPHA_SEL_B_SRC1 (1 << 19) 3044# define R500_ALPHA_SEL_B_SRC2 (2 << 19) 3045# define R500_ALPHA_SEL_B_SRCP (3 << 19) 3046# define R500_ALPHA_SWIZ_B_R (0 << 21) 3047# define R500_ALPHA_SWIZ_B_G (1 << 21) 3048# define R500_ALPHA_SWIZ_B_B (2 << 21) 3049# define R500_ALPHA_SWIZ_B_A (3 << 21) 3050# define R500_ALPHA_SWIZ_B_0 (4 << 21) 3051# define R500_ALPHA_SWIZ_B_HALF (5 << 21) 3052# define R500_ALPHA_SWIZ_B_1 (6 << 21) 3053/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ 3054# define R500_ALPHA_MOD_B_NOP (0 << 24) 3055# define R500_ALPHA_MOD_B_NEG (1 << 24) 3056# define R500_ALPHA_MOD_B_ABS (2 << 24) 3057# define R500_ALPHA_MOD_B_NAB (3 << 24) 3058# define R500_ALPHA_OMOD_SHIFT 26 3059# define R500_ALPHA_OMOD_IDENTITY (0 << R500_ALPHA_OMOD_SHIFT) 3060# define R500_ALPHA_OMOD_MUL_2 (1 << R500_ALPHA_OMOD_SHIFT) 3061# define R500_ALPHA_OMOD_MUL_4 (2 << R500_ALPHA_OMOD_SHIFT) 3062# define R500_ALPHA_OMOD_MUL_8 (3 << R500_ALPHA_OMOD_SHIFT) 3063# define R500_ALPHA_OMOD_DIV_2 (4 << R500_ALPHA_OMOD_SHIFT) 3064# define R500_ALPHA_OMOD_DIV_4 (5 << R500_ALPHA_OMOD_SHIFT) 3065# define R500_ALPHA_OMOD_DIV_8 (6 << R500_ALPHA_OMOD_SHIFT) 3066# define R500_ALPHA_OMOD_DISABLE (7 << R500_ALPHA_OMOD_SHIFT) 3067# define R500_ALPHA_TARGET(x) ((x) << 29) 3068# define R500_ALPHA_W_OMASK (1 << 31) 3069#define R500_US_ALU_ALPHA_ADDR_0 0x9800 3070# define R500_ALPHA_ADDR0(x) ((x) << 0) 3071# define R500_ALPHA_ADDR0_CONST (1 << 8) 3072# define R500_ALPHA_ADDR0_REL (1 << 9) 3073# define R500_ALPHA_ADDR1(x) ((x) << 10) 3074# define R500_ALPHA_ADDR1_CONST (1 << 18) 3075# define R500_ALPHA_ADDR1_REL (1 << 19) 3076# define R500_ALPHA_ADDR2(x) ((x) << 20) 3077# define R500_ALPHA_ADDR2_CONST (1 << 28) 3078# define R500_ALPHA_ADDR2_REL (1 << 29) 3079# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) 3080# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) 3081# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) 3082# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) 3083#define R500_US_ALU_RGBA_INST_0 0xb000 3084# define R500_ALU_RGBA_OP_MAD (0 << 0) 3085# define R500_ALU_RGBA_OP_DP3 (1 << 0) 3086# define R500_ALU_RGBA_OP_DP4 (2 << 0) 3087# define R500_ALU_RGBA_OP_D2A (3 << 0) 3088# define R500_ALU_RGBA_OP_MIN (4 << 0) 3089# define R500_ALU_RGBA_OP_MAX (5 << 0) 3090/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ 3091# define R500_ALU_RGBA_OP_CND (7 << 0) 3092# define R500_ALU_RGBA_OP_CMP (8 << 0) 3093# define R500_ALU_RGBA_OP_FRC (9 << 0) 3094# define R500_ALU_RGBA_OP_SOP (10 << 0) 3095# define R500_ALU_RGBA_OP_MDH (11 << 0) 3096# define R500_ALU_RGBA_OP_MDV (12 << 0) 3097# define R500_ALU_RGBA_ADDRD(x) ((x) << 4) 3098# define R500_ALU_RGBA_ADDRD_REL (1 << 11) 3099# define R500_ALU_RGBA_SEL_C_SHIFT 12 3100# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) 3101# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) 3102# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) 3103# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) 3104# define R500_ALU_RGBA_R_SWIZ_R (0 << 14) 3105# define R500_ALU_RGBA_R_SWIZ_G (1 << 14) 3106# define R500_ALU_RGBA_R_SWIZ_B (2 << 14) 3107# define R500_ALU_RGBA_R_SWIZ_A (3 << 14) 3108# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) 3109# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) 3110# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) 3111/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ 3112# define R500_ALU_RGBA_G_SWIZ_R (0 << 17) 3113# define R500_ALU_RGBA_G_SWIZ_G (1 << 17) 3114# define R500_ALU_RGBA_G_SWIZ_B (2 << 17) 3115# define R500_ALU_RGBA_G_SWIZ_A (3 << 17) 3116# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) 3117# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) 3118# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) 3119/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ 3120# define R500_ALU_RGBA_B_SWIZ_R (0 << 20) 3121# define R500_ALU_RGBA_B_SWIZ_G (1 << 20) 3122# define R500_ALU_RGBA_B_SWIZ_B (2 << 20) 3123# define R500_ALU_RGBA_B_SWIZ_A (3 << 20) 3124# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) 3125# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) 3126# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) 3127/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ 3128# define R500_ALU_RGBA_MOD_C_NOP (0 << 23) 3129# define R500_ALU_RGBA_MOD_C_NEG (1 << 23) 3130# define R500_ALU_RGBA_MOD_C_ABS (2 << 23) 3131# define R500_ALU_RGBA_MOD_C_NAB (3 << 23) 3132# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25 3133# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) 3134# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) 3135# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) 3136# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) 3137# define R500_ALU_RGBA_A_SWIZ_R (0 << 27) 3138# define R500_ALU_RGBA_A_SWIZ_G (1 << 27) 3139# define R500_ALU_RGBA_A_SWIZ_B (2 << 27) 3140# define R500_ALU_RGBA_A_SWIZ_A (3 << 27) 3141# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) 3142# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) 3143# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) 3144/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ 3145# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) 3146# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) 3147# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) 3148# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) 3149#define R500_US_ALU_RGB_INST_0 0xa000 3150# define R500_ALU_RGB_SEL_A_SHIFT 0 3151# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) 3152# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) 3153# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) 3154# define R500_ALU_RGB_SEL_A_SRCP (3 << 0) 3155# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) 3156# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) 3157# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) 3158# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) 3159# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) 3160# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) 3161# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) 3162/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ 3163# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) 3164# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) 3165# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) 3166# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) 3167# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) 3168# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) 3169# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) 3170/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ 3171# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) 3172# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) 3173# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) 3174# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) 3175# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) 3176# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) 3177# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) 3178/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ 3179# define R500_ALU_RGB_MOD_A_NOP (0 << 11) 3180# define R500_ALU_RGB_MOD_A_NEG (1 << 11) 3181# define R500_ALU_RGB_MOD_A_ABS (2 << 11) 3182# define R500_ALU_RGB_MOD_A_NAB (3 << 11) 3183# define R500_ALU_RGB_SEL_B_SHIFT 13 3184# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) 3185# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) 3186# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) 3187# define R500_ALU_RGB_SEL_B_SRCP (3 << 13) 3188# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) 3189# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) 3190# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) 3191# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) 3192# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) 3193# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) 3194# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) 3195/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ 3196# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) 3197# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) 3198# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) 3199# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) 3200# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) 3201# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) 3202# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) 3203/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ 3204# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) 3205# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) 3206# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) 3207# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) 3208# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) 3209# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) 3210# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) 3211/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ 3212# define R500_ALU_RGB_MOD_B_NOP (0 << 24) 3213# define R500_ALU_RGB_MOD_B_NEG (1 << 24) 3214# define R500_ALU_RGB_MOD_B_ABS (2 << 24) 3215# define R500_ALU_RGB_MOD_B_NAB (3 << 24) 3216# define R500_ALU_RGB_OMOD_SHIFT 26 3217# define R500_ALU_RGB_OMOD_IDENTITY (0 << R500_ALU_RGB_OMOD_SHIFT) 3218# define R500_ALU_RGB_OMOD_MUL_2 (1 << R500_ALU_RGB_OMOD_SHIFT) 3219# define R500_ALU_RGB_OMOD_MUL_4 (2 << R500_ALU_RGB_OMOD_SHIFT) 3220# define R500_ALU_RGB_OMOD_MUL_8 (3 << R500_ALU_RGB_OMOD_SHIFT) 3221# define R500_ALU_RGB_OMOD_DIV_2 (4 << R500_ALU_RGB_OMOD_SHIFT) 3222# define R500_ALU_RGB_OMOD_DIV_4 (5 << R500_ALU_RGB_OMOD_SHIFT) 3223# define R500_ALU_RGB_OMOD_DIV_8 (6 << R500_ALU_RGB_OMOD_SHIFT) 3224# define R500_ALU_RGB_OMOD_DISABLE (7 << R500_ALU_RGB_OMOD_SHIFT) 3225# define R500_ALU_RGB_TARGET(x) ((x) << 29) 3226# define R500_ALU_RGB_WMASK (1 << 31) 3227#define R500_US_ALU_RGB_ADDR_0 0x9000 3228# define R500_RGB_ADDR0(x) ((x) << 0) 3229# define R500_RGB_ADDR0_CONST (1 << 8) 3230# define R500_RGB_ADDR0_REL (1 << 9) 3231# define R500_RGB_ADDR1(x) ((x) << 10) 3232# define R500_RGB_ADDR1_CONST (1 << 18) 3233# define R500_RGB_ADDR1_REL (1 << 19) 3234# define R500_RGB_ADDR2(x) ((x) << 20) 3235# define R500_RGB_ADDR2_CONST (1 << 28) 3236# define R500_RGB_ADDR2_REL (1 << 29) 3237# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) 3238# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) 3239# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) 3240# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) 3241#define R500_US_CMN_INST_0 0xb800 3242# define R500_INST_TYPE_MASK (3 << 0) 3243# define R500_INST_TYPE_ALU (0 << 0) 3244# define R500_INST_TYPE_OUT (1 << 0) 3245# define R500_INST_TYPE_FC (2 << 0) 3246# define R500_INST_TYPE_TEX (3 << 0) 3247# define R500_INST_TEX_SEM_WAIT_SHIFT 2 3248# define R500_INST_TEX_SEM_WAIT (1 << R500_INST_TEX_SEM_WAIT_SHIFT) 3249# define R500_INST_RGB_PRED_SEL_NONE (0 << 3) 3250# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) 3251# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) 3252# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) 3253# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) 3254# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) 3255# define R500_INST_RGB_PRED_INV (1 << 6) 3256# define R500_INST_WRITE_INACTIVE (1 << 7) 3257# define R500_INST_LAST (1 << 8) 3258# define R500_INST_NOP (1 << 9) 3259# define R500_INST_ALU_WAIT (1 << 10) 3260# define R500_INST_RGB_WMASK_R (1 << 11) 3261# define R500_INST_RGB_WMASK_G (1 << 12) 3262# define R500_INST_RGB_WMASK_B (1 << 13) 3263# define R500_INST_RGB_WMASK_RGB (7 << 11) 3264# define R500_INST_ALPHA_WMASK (1 << 14) 3265# define R500_INST_RGB_OMASK_R (1 << 15) 3266# define R500_INST_RGB_OMASK_G (1 << 16) 3267# define R500_INST_RGB_OMASK_B (1 << 17) 3268# define R500_INST_RGB_OMASK_RGB (7 << 15) 3269# define R500_INST_ALPHA_OMASK (1 << 18) 3270# define R500_INST_RGB_CLAMP (1 << 19) 3271# define R500_INST_ALPHA_CLAMP (1 << 20) 3272# define R500_INST_ALU_RESULT_SEL (1 << 21) 3273# define R500_INST_ALU_RESULT_SEL_RED (0 << 21) 3274# define R500_INST_ALU_RESULT_SEL_ALPHA (1 << 21) 3275# define R500_INST_ALPHA_PRED_INV (1 << 22) 3276# define R500_INST_ALU_RESULT_OP_EQ (0 << 23) 3277# define R500_INST_ALU_RESULT_OP_LT (1 << 23) 3278# define R500_INST_ALU_RESULT_OP_GE (2 << 23) 3279# define R500_INST_ALU_RESULT_OP_NE (3 << 23) 3280# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) 3281# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) 3282# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) 3283# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) 3284# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) 3285# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) 3286/* XXX next four are kind of guessed */ 3287# define R500_INST_STAT_WE_R (1 << 28) 3288# define R500_INST_STAT_WE_G (1 << 29) 3289# define R500_INST_STAT_WE_B (1 << 30) 3290# define R500_INST_STAT_WE_A (1 << 31) 3291 3292/* note that these are 8 bit lengths, despite the offsets, at least for R500 */ 3293#define R500_US_CODE_ADDR 0x4630 3294# define R500_US_CODE_START_ADDR(x) ((x) << 0) 3295# define R500_US_CODE_END_ADDR(x) ((x) << 16) 3296#define R500_US_CODE_OFFSET 0x4638 3297# define R500_US_CODE_OFFSET_ADDR(x) ((x) << 0) 3298#define R500_US_CODE_RANGE 0x4634 3299# define R500_US_CODE_RANGE_ADDR(x) ((x) << 0) 3300# define R500_US_CODE_RANGE_SIZE(x) ((x) << 16) 3301#define R500_US_CONFIG 0x4600 3302# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) 3303#define R500_US_FC_ADDR_0 0xa000 3304# define R500_FC_BOOL_ADDR(x) ((x) << 0) 3305# define R500_FC_INT_ADDR(x) ((x) << 8) 3306# define R500_FC_JUMP_ADDR(x) ((x) << 16) 3307# define R500_FC_JUMP_GLOBAL (1 << 31) 3308#define R500_US_FC_BOOL_CONST 0x4620 3309# define R500_FC_KBOOL(x) (x) 3310#define R500_US_FC_CTRL 0x4624 3311# define R500_FC_TEST_EN (1 << 30) 3312# define R500_FC_FULL_FC_EN (1 << 31) 3313#define R500_US_FC_INST_0 0x9800 3314# define R500_FC_OP_JUMP (0 << 0) 3315# define R500_FC_OP_LOOP (1 << 0) 3316# define R500_FC_OP_ENDLOOP (2 << 0) 3317# define R500_FC_OP_REP (3 << 0) 3318# define R500_FC_OP_ENDREP (4 << 0) 3319# define R500_FC_OP_BREAKLOOP (5 << 0) 3320# define R500_FC_OP_BREAKREP (6 << 0) 3321# define R500_FC_OP_CONTINUE (7 << 0) 3322# define R500_FC_B_ELSE (1 << 4) 3323# define R500_FC_JUMP_ANY (1 << 5) 3324# define R500_FC_A_OP_NONE (0 << 6) 3325# define R500_FC_A_OP_POP (1 << 6) 3326# define R500_FC_A_OP_PUSH (2 << 6) 3327# define R500_FC_JUMP_FUNC(x) ((x) << 8) 3328# define R500_FC_B_POP_CNT(x) ((x) << 16) 3329# define R500_FC_B_OP0_NONE (0 << 24) 3330# define R500_FC_B_OP0_DECR (1 << 24) 3331# define R500_FC_B_OP0_INCR (2 << 24) 3332# define R500_FC_B_OP1_NONE (0 << 26) 3333# define R500_FC_B_OP1_DECR (1 << 26) 3334# define R500_FC_B_OP1_INCR (2 << 26) 3335# define R500_FC_IGNORE_UNCOVERED (1 << 28) 3336#define R500_US_FC_INT_CONST_0 0x4c00 3337# define R500_FC_INT_CONST_KR(x) ((x) << 0) 3338# define R500_FC_INT_CONST_KG(x) ((x) << 8) 3339# define R500_FC_INT_CONST_KB(x) ((x) << 16) 3340/* _0 through _15 */ 3341#define R500_US_FORMAT0_0 0x4640 3342# define R500_FORMAT_TXWIDTH(x) ((x) << 0) 3343# define R500_FORMAT_TXHEIGHT(x) ((x) << 11) 3344# define R500_FORMAT_TXDEPTH(x) ((x) << 22) 3345#define R500_US_PIXSIZE 0x4604 3346# define R500_PIX_SIZE(x) (x) 3347#define R500_US_TEX_ADDR_0 0x9800 3348# define R500_TEX_SRC_ADDR(x) ((x) << 0) 3349# define R500_TEX_SRC_ADDR_REL (1 << 7) 3350# define R500_TEX_SRC_S_SWIZ_R (0 << 8) 3351# define R500_TEX_SRC_S_SWIZ_G (1 << 8) 3352# define R500_TEX_SRC_S_SWIZ_B (2 << 8) 3353# define R500_TEX_SRC_S_SWIZ_A (3 << 8) 3354# define R500_TEX_SRC_T_SWIZ_R (0 << 10) 3355# define R500_TEX_SRC_T_SWIZ_G (1 << 10) 3356# define R500_TEX_SRC_T_SWIZ_B (2 << 10) 3357# define R500_TEX_SRC_T_SWIZ_A (3 << 10) 3358# define R500_TEX_SRC_R_SWIZ_R (0 << 12) 3359# define R500_TEX_SRC_R_SWIZ_G (1 << 12) 3360# define R500_TEX_SRC_R_SWIZ_B (2 << 12) 3361# define R500_TEX_SRC_R_SWIZ_A (3 << 12) 3362# define R500_TEX_SRC_Q_SWIZ_R (0 << 14) 3363# define R500_TEX_SRC_Q_SWIZ_G (1 << 14) 3364# define R500_TEX_SRC_Q_SWIZ_B (2 << 14) 3365# define R500_TEX_SRC_Q_SWIZ_A (3 << 14) 3366# define R500_TEX_DST_ADDR(x) ((x) << 16) 3367# define R500_TEX_DST_ADDR_REL (1 << 23) 3368# define R500_TEX_DST_R_SWIZ_R (0 << 24) 3369# define R500_TEX_DST_R_SWIZ_G (1 << 24) 3370# define R500_TEX_DST_R_SWIZ_B (2 << 24) 3371# define R500_TEX_DST_R_SWIZ_A (3 << 24) 3372# define R500_TEX_DST_G_SWIZ_R (0 << 26) 3373# define R500_TEX_DST_G_SWIZ_G (1 << 26) 3374# define R500_TEX_DST_G_SWIZ_B (2 << 26) 3375# define R500_TEX_DST_G_SWIZ_A (3 << 26) 3376# define R500_TEX_DST_B_SWIZ_R (0 << 28) 3377# define R500_TEX_DST_B_SWIZ_G (1 << 28) 3378# define R500_TEX_DST_B_SWIZ_B (2 << 28) 3379# define R500_TEX_DST_B_SWIZ_A (3 << 28) 3380# define R500_TEX_DST_A_SWIZ_R (0 << 30) 3381# define R500_TEX_DST_A_SWIZ_G (1 << 30) 3382# define R500_TEX_DST_A_SWIZ_B (2 << 30) 3383# define R500_TEX_DST_A_SWIZ_A (3 << 30) 3384#define R500_US_TEX_ADDR_DXDY_0 0xa000 3385# define R500_DX_ADDR(x) ((x) << 0) 3386# define R500_DX_ADDR_REL (1 << 7) 3387# define R500_DX_S_SWIZ_R (0 << 8) 3388# define R500_DX_S_SWIZ_G (1 << 8) 3389# define R500_DX_S_SWIZ_B (2 << 8) 3390# define R500_DX_S_SWIZ_A (3 << 8) 3391# define R500_DX_T_SWIZ_R (0 << 10) 3392# define R500_DX_T_SWIZ_G (1 << 10) 3393# define R500_DX_T_SWIZ_B (2 << 10) 3394# define R500_DX_T_SWIZ_A (3 << 10) 3395# define R500_DX_R_SWIZ_R (0 << 12) 3396# define R500_DX_R_SWIZ_G (1 << 12) 3397# define R500_DX_R_SWIZ_B (2 << 12) 3398# define R500_DX_R_SWIZ_A (3 << 12) 3399# define R500_DX_Q_SWIZ_R (0 << 14) 3400# define R500_DX_Q_SWIZ_G (1 << 14) 3401# define R500_DX_Q_SWIZ_B (2 << 14) 3402# define R500_DX_Q_SWIZ_A (3 << 14) 3403# define R500_DY_ADDR(x) ((x) << 16) 3404# define R500_DY_ADDR_REL (1 << 17) 3405# define R500_DY_S_SWIZ_R (0 << 24) 3406# define R500_DY_S_SWIZ_G (1 << 24) 3407# define R500_DY_S_SWIZ_B (2 << 24) 3408# define R500_DY_S_SWIZ_A (3 << 24) 3409# define R500_DY_T_SWIZ_R (0 << 26) 3410# define R500_DY_T_SWIZ_G (1 << 26) 3411# define R500_DY_T_SWIZ_B (2 << 26) 3412# define R500_DY_T_SWIZ_A (3 << 26) 3413# define R500_DY_R_SWIZ_R (0 << 28) 3414# define R500_DY_R_SWIZ_G (1 << 28) 3415# define R500_DY_R_SWIZ_B (2 << 28) 3416# define R500_DY_R_SWIZ_A (3 << 28) 3417# define R500_DY_Q_SWIZ_R (0 << 30) 3418# define R500_DY_Q_SWIZ_G (1 << 30) 3419# define R500_DY_Q_SWIZ_B (2 << 30) 3420# define R500_DY_Q_SWIZ_A (3 << 30) 3421#define R500_US_TEX_INST_0 0x9000 3422# define R500_TEX_ID(x) ((x) << 16) 3423# define R500_TEX_INST_NOP (0 << 22) 3424# define R500_TEX_INST_LD (1 << 22) 3425# define R500_TEX_INST_TEXKILL (2 << 22) 3426# define R500_TEX_INST_PROJ (3 << 22) 3427# define R500_TEX_INST_LODBIAS (4 << 22) 3428# define R500_TEX_INST_LOD (5 << 22) 3429# define R500_TEX_INST_DXDY (6 << 22) 3430# define R500_TEX_SEM_ACQUIRE_SHIFT 25 3431# define R500_TEX_SEM_ACQUIRE (1 << R500_TEX_SEM_ACQUIRE_SHIFT) 3432# define R500_TEX_IGNORE_UNCOVERED (1 << 26) 3433# define R500_TEX_UNSCALED (1 << 27) 3434#define R300_US_W_FMT 0x46b4 3435# define R300_W_FMT_W0 (0 << 0) 3436# define R300_W_FMT_W24 (1 << 0) 3437# define R300_W_FMT_W24FP (2 << 0) 3438# define R300_W_SRC_US (0 << 2) 3439# define R300_W_SRC_RAS (1 << 2) 3440 3441/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. 3442 * Two parameter dwords: 3443 * 0. VAP_VTX_FMT: The first parameter is not written to hardware 3444 * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. 3445 */ 3446#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 3447 3448/* Draw a primitive from immediate vertices in this packet 3449 * Up to 16382 dwords: 3450 * 0. VAP_VTX_FMT: The first parameter is not written to hardware 3451 * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. 3452 * 2 to end: Up to 16380 dwords of vertex data. 3453 */ 3454#define R300_PACKET3_3D_DRAW_IMMD 0x00002900 3455 3456/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and 3457 * immediate vertices in this packet 3458 * Up to 16382 dwords: 3459 * 0. VAP_VTX_FMT: The first parameter is not written to hardware 3460 * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. 3461 * 2 to end: Up to 16380 dwords of vertex data. 3462 */ 3463#define R300_PACKET3_3D_DRAW_INDX 0x00002A00 3464 3465 3466/* Specify the full set of vertex arrays as (address, stride). 3467 * The first parameter is the number of vertex arrays specified. 3468 * The rest of the command is a variable length list of blocks, where 3469 * each block is three dwords long and specifies two arrays. 3470 * The first dword of a block is split into two words, the lower significant 3471 * word refers to the first array, the more significant word to the second 3472 * array in the block. 3473 * The low byte of each word contains the size of an array entry in dwords, 3474 * the high byte contains the stride of the array. 3475 * The second dword of a block contains the pointer to the first array, 3476 * the third dword of a block contains the pointer to the second array. 3477 * Note that if the total number of arrays is odd, the third dword of 3478 * the last block is omitted. 3479 */ 3480#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 3481# define R300_VC_FORCE_PREFETCH (1 << 5) 3482# define R300_VBPNTR_SIZE0(x) ((x) >> 2) 3483# define R300_VBPNTR_STRIDE0(x) (((x) >> 2) << 8) 3484# define R300_VBPNTR_SIZE1(x) (((x) >> 2) << 16) 3485# define R300_VBPNTR_STRIDE1(x) (((x) >> 2) << 24) 3486 3487#define R300_PACKET3_3D_CLEAR_ZMASK 0x00003200 3488#define R300_PACKET3_INDX_BUFFER 0x00003300 3489# define R300_INDX_BUFFER_DST_SHIFT 0 3490# define R300_INDX_BUFFER_SKIP_SHIFT 16 3491# define R300_INDX_BUFFER_ONE_REG_WR (1<<31) 3492 3493/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */ 3494#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 3495/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */ 3496#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500 3497/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */ 3498#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 3499 3500/* Clears a portion of hierachical Z RAM 3501 * 3 dword parameters 3502 * 0. START 3503 * 1. COUNT: 13:0 (max is 0x3FFF) 3504 * 2. CLEAR_VALUE: Value to write into HIZ RAM. 3505 */ 3506#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700 3507 3508/* Draws a set of primitives using vertex buffers pointed by the state data. 3509 * At least 2 Parameters: 3510 * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword. 3511 * 2 to end: Data or indices (see other 3D_DRAW_* packets for details) 3512 */ 3513#define R300_PACKET3_3D_DRAW_128 0x00003900 3514 3515/* END: Packet 3 commands */ 3516 3517 3518/* Color formats for 2d packets 3519 */ 3520#define R300_CP_COLOR_FORMAT_CI8 2 3521#define R300_CP_COLOR_FORMAT_ARGB1555 3 3522#define R300_CP_COLOR_FORMAT_RGB565 4 3523#define R300_CP_COLOR_FORMAT_ARGB8888 6 3524#define R300_CP_COLOR_FORMAT_RGB332 7 3525#define R300_CP_COLOR_FORMAT_RGB8 9 3526#define R300_CP_COLOR_FORMAT_ARGB4444 15 3527 3528/* 3529 * CP type-3 packets 3530 */ 3531#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 3532 3533/* XXX Corbin's stuff from radeon and r200 */ 3534 3535#define RADEON_WAIT_UNTIL 0x1720 3536# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 3537# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 3538# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 3539# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 3540 3541#define R200_3D_DRAW_IMMD_2 0xC0003500 3542 3543#define RADEON_CP_PACKET0 0x0 /* XXX stolen from radeon_reg.h */ 3544#define RADEON_CP_PACKET3 0xC0000000 3545 3546#define RADEON_ONE_REG_WR (1 << 15) 3547 3548#define CP_PACKET0(register, count) \ 3549 (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2)) 3550 3551#define CP_PACKET3(op, count) \ 3552 (RADEON_CP_PACKET3 | (op) | ((count) << 16)) 3553 3554#endif /* _R300_REG_H */ 3555 3556/* *INDENT-ON* */ 3557 3558/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */ 3559