1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_math.h" 27#include "util/u_memory.h" 28#include "util/u_pack_color.h" 29 30#include "r300_context.h" 31#include "r300_fs.h" 32#include "r300_screen.h" 33#include "r300_shader_semantics.h" 34#include "r300_state_inlines.h" 35#include "r300_texture.h" 36#include "r300_vs.h" 37 38/* r300_state_derived: Various bits of state which are dependent upon 39 * currently bound CSO data. */ 40 41enum r300_rs_swizzle { 42 SWIZ_XYZW = 0, 43 SWIZ_X001, 44 SWIZ_XY01, 45 SWIZ_0001, 46}; 47 48enum r300_rs_col_write_type { 49 WRITE_COLOR = 0, 50 WRITE_FACE 51}; 52 53static void r300_draw_emit_attrib(struct r300_context* r300, 54 enum attrib_emit emit, 55 enum interp_mode interp, 56 int index) 57{ 58 struct r300_vertex_shader* vs = r300->vs_state.state; 59 struct tgsi_shader_info* info = &vs->info; 60 int output; 61 62 output = draw_find_shader_output(r300->draw, 63 info->output_semantic_name[index], 64 info->output_semantic_index[index]); 65 draw_emit_vertex_attr(&r300->vertex_info, emit, interp, output); 66} 67 68static void r300_draw_emit_all_attribs(struct r300_context* r300) 69{ 70 struct r300_vertex_shader* vs = r300->vs_state.state; 71 struct r300_shader_semantics* vs_outputs = &vs->outputs; 72 int i, gen_count; 73 74 /* Position. */ 75 if (vs_outputs->pos != ATTR_UNUSED) { 76 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE, 77 vs_outputs->pos); 78 } else { 79 assert(0); 80 } 81 82 /* Point size. */ 83 if (vs_outputs->psize != ATTR_UNUSED) { 84 r300_draw_emit_attrib(r300, EMIT_1F_PSIZE, INTERP_POS, 85 vs_outputs->psize); 86 } 87 88 /* Colors. */ 89 for (i = 0; i < ATTR_COLOR_COUNT; i++) { 90 if (vs_outputs->color[i] != ATTR_UNUSED) { 91 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_LINEAR, 92 vs_outputs->color[i]); 93 } 94 } 95 96 /* Back-face colors. */ 97 for (i = 0; i < ATTR_COLOR_COUNT; i++) { 98 if (vs_outputs->bcolor[i] != ATTR_UNUSED) { 99 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_LINEAR, 100 vs_outputs->bcolor[i]); 101 } 102 } 103 104 /* Texture coordinates. */ 105 /* Only 8 generic vertex attributes can be used. If there are more, 106 * they won't be rasterized. */ 107 gen_count = 0; 108 for (i = 0; i < ATTR_GENERIC_COUNT && gen_count < 8; i++) { 109 if (vs_outputs->generic[i] != ATTR_UNUSED && 110 !(r300->sprite_coord_enable & (1 << i))) { 111 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE, 112 vs_outputs->generic[i]); 113 gen_count++; 114 } 115 } 116 117 /* Fog coordinates. */ 118 if (gen_count < 8 && vs_outputs->fog != ATTR_UNUSED) { 119 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE, 120 vs_outputs->fog); 121 gen_count++; 122 } 123 124 /* WPOS. */ 125 if (r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED && gen_count < 8) { 126 DBG(r300, DBG_SWTCL, "draw_emit_attrib: WPOS, index: %i\n", 127 vs_outputs->wpos); 128 r300_draw_emit_attrib(r300, EMIT_4F, INTERP_PERSPECTIVE, 129 vs_outputs->wpos); 130 } 131} 132 133/* Update the PSC tables for SW TCL, using Draw. */ 134static void r300_swtcl_vertex_psc(struct r300_context *r300) 135{ 136 struct r300_vertex_stream_state *vstream = r300->vertex_stream_state.state; 137 struct vertex_info *vinfo = &r300->vertex_info; 138 uint16_t type, swizzle; 139 enum pipe_format format; 140 unsigned i, attrib_count; 141 int* vs_output_tab = r300->stream_loc_notcl; 142 143 memset(vstream, 0, sizeof(struct r300_vertex_stream_state)); 144 145 /* For each Draw attribute, route it to the fragment shader according 146 * to the vs_output_tab. */ 147 attrib_count = vinfo->num_attribs; 148 DBG(r300, DBG_SWTCL, "r300: attrib count: %d\n", attrib_count); 149 for (i = 0; i < attrib_count; i++) { 150 if (vs_output_tab[i] == -1) { 151 assert(0); 152 abort(); 153 } 154 155 format = draw_translate_vinfo_format(vinfo->attrib[i].emit); 156 157 DBG(r300, DBG_SWTCL, 158 "r300: swtcl_vertex_psc [%i] <- %s\n", 159 vs_output_tab[i], util_format_short_name(format)); 160 161 /* Obtain the type of data in this attribute. */ 162 type = r300_translate_vertex_data_type(format); 163 if (type == R300_INVALID_FORMAT) { 164 fprintf(stderr, "r300: Bad vertex format %s.\n", 165 util_format_short_name(format)); 166 assert(0); 167 abort(); 168 } 169 170 type |= vs_output_tab[i] << R300_DST_VEC_LOC_SHIFT; 171 172 /* Obtain the swizzle for this attribute. Note that the default 173 * swizzle in the hardware is not XYZW! */ 174 swizzle = r300_translate_vertex_data_swizzle(format); 175 176 /* Add the attribute to the PSC table. */ 177 if (i & 1) { 178 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 179 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 180 } else { 181 vstream->vap_prog_stream_cntl[i >> 1] |= type; 182 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 183 } 184 } 185 186 /* Set the last vector in the PSC. */ 187 if (i) { 188 i -= 1; 189 } 190 vstream->vap_prog_stream_cntl[i >> 1] |= 191 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 192 193 vstream->count = (i >> 1) + 1; 194 r300_mark_atom_dirty(r300, &r300->vertex_stream_state); 195 r300->vertex_stream_state.size = (1 + vstream->count) * 2; 196} 197 198static void r300_rs_col(struct r300_rs_block* rs, int id, int ptr, 199 enum r300_rs_swizzle swiz) 200{ 201 rs->ip[id] |= R300_RS_COL_PTR(ptr); 202 if (swiz == SWIZ_0001) { 203 rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_0001); 204 } else { 205 rs->ip[id] |= R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA); 206 } 207 rs->inst[id] |= R300_RS_INST_COL_ID(id); 208} 209 210static void r300_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset, 211 enum r300_rs_col_write_type type) 212{ 213 assert(type == WRITE_COLOR); 214 rs->inst[id] |= R300_RS_INST_COL_CN_WRITE | 215 R300_RS_INST_COL_ADDR(fp_offset); 216} 217 218static void r300_rs_tex(struct r300_rs_block* rs, int id, int ptr, 219 enum r300_rs_swizzle swiz) 220{ 221 if (swiz == SWIZ_X001) { 222 rs->ip[id] |= R300_RS_TEX_PTR(ptr) | 223 R300_RS_SEL_S(R300_RS_SEL_C0) | 224 R300_RS_SEL_T(R300_RS_SEL_K0) | 225 R300_RS_SEL_R(R300_RS_SEL_K0) | 226 R300_RS_SEL_Q(R300_RS_SEL_K1); 227 } else if (swiz == SWIZ_XY01) { 228 rs->ip[id] |= R300_RS_TEX_PTR(ptr) | 229 R300_RS_SEL_S(R300_RS_SEL_C0) | 230 R300_RS_SEL_T(R300_RS_SEL_C1) | 231 R300_RS_SEL_R(R300_RS_SEL_K0) | 232 R300_RS_SEL_Q(R300_RS_SEL_K1); 233 } else { 234 rs->ip[id] |= R300_RS_TEX_PTR(ptr) | 235 R300_RS_SEL_S(R300_RS_SEL_C0) | 236 R300_RS_SEL_T(R300_RS_SEL_C1) | 237 R300_RS_SEL_R(R300_RS_SEL_C2) | 238 R300_RS_SEL_Q(R300_RS_SEL_C3); 239 } 240 rs->inst[id] |= R300_RS_INST_TEX_ID(id); 241} 242 243static void r300_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset) 244{ 245 rs->inst[id] |= R300_RS_INST_TEX_CN_WRITE | 246 R300_RS_INST_TEX_ADDR(fp_offset); 247} 248 249static void r500_rs_col(struct r300_rs_block* rs, int id, int ptr, 250 enum r300_rs_swizzle swiz) 251{ 252 rs->ip[id] |= R500_RS_COL_PTR(ptr); 253 if (swiz == SWIZ_0001) { 254 rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_0001); 255 } else { 256 rs->ip[id] |= R500_RS_COL_FMT(R300_RS_COL_FMT_RGBA); 257 } 258 rs->inst[id] |= R500_RS_INST_COL_ID(id); 259} 260 261static void r500_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset, 262 enum r300_rs_col_write_type type) 263{ 264 if (type == WRITE_FACE) 265 rs->inst[id] |= R500_RS_INST_COL_CN_WRITE_BACKFACE | 266 R500_RS_INST_COL_ADDR(fp_offset); 267 else 268 rs->inst[id] |= R500_RS_INST_COL_CN_WRITE | 269 R500_RS_INST_COL_ADDR(fp_offset); 270 271} 272 273static void r500_rs_tex(struct r300_rs_block* rs, int id, int ptr, 274 enum r300_rs_swizzle swiz) 275{ 276 if (swiz == SWIZ_X001) { 277 rs->ip[id] |= R500_RS_SEL_S(ptr) | 278 R500_RS_SEL_T(R500_RS_IP_PTR_K0) | 279 R500_RS_SEL_R(R500_RS_IP_PTR_K0) | 280 R500_RS_SEL_Q(R500_RS_IP_PTR_K1); 281 } else if (swiz == SWIZ_XY01) { 282 rs->ip[id] |= R500_RS_SEL_S(ptr) | 283 R500_RS_SEL_T(ptr + 1) | 284 R500_RS_SEL_R(R500_RS_IP_PTR_K0) | 285 R500_RS_SEL_Q(R500_RS_IP_PTR_K1); 286 } else { 287 rs->ip[id] |= R500_RS_SEL_S(ptr) | 288 R500_RS_SEL_T(ptr + 1) | 289 R500_RS_SEL_R(ptr + 2) | 290 R500_RS_SEL_Q(ptr + 3); 291 } 292 rs->inst[id] |= R500_RS_INST_TEX_ID(id); 293} 294 295static void r500_rs_tex_write(struct r300_rs_block* rs, int id, int fp_offset) 296{ 297 rs->inst[id] |= R500_RS_INST_TEX_CN_WRITE | 298 R500_RS_INST_TEX_ADDR(fp_offset); 299} 300 301/* Set up the RS block. 302 * 303 * This is the part of the chipset that is responsible for linking vertex 304 * and fragment shaders and stuffed texture coordinates. 305 * 306 * The rasterizer reads data from VAP, which produces vertex shader outputs, 307 * and GA, which produces stuffed texture coordinates. VAP outputs have 308 * precedence over GA. All outputs must be rasterized otherwise it locks up. 309 * If there are more outputs rasterized than is set in VAP/GA, it locks up 310 * too. The funky part is that this info has been pretty much obtained by trial 311 * and error. */ 312static void r300_update_rs_block(struct r300_context *r300) 313{ 314 struct r300_vertex_shader *vs = r300->vs_state.state; 315 struct r300_shader_semantics *vs_outputs = &vs->outputs; 316 struct r300_shader_semantics *fs_inputs = &r300_fs(r300)->shader->inputs; 317 struct r300_rs_block rs = {0}; 318 int i, col_count = 0, tex_count = 0, fp_offset = 0, count, loc = 0, tex_ptr = 0; 319 void (*rX00_rs_col)(struct r300_rs_block*, int, int, enum r300_rs_swizzle); 320 void (*rX00_rs_col_write)(struct r300_rs_block*, int, int, enum r300_rs_col_write_type); 321 void (*rX00_rs_tex)(struct r300_rs_block*, int, int, enum r300_rs_swizzle); 322 void (*rX00_rs_tex_write)(struct r300_rs_block*, int, int); 323 boolean any_bcolor_used = vs_outputs->bcolor[0] != ATTR_UNUSED || 324 vs_outputs->bcolor[1] != ATTR_UNUSED; 325 int *stream_loc_notcl = r300->stream_loc_notcl; 326 uint32_t stuffing_enable = 0; 327 328 if (r300->screen->caps.is_r500) { 329 rX00_rs_col = r500_rs_col; 330 rX00_rs_col_write = r500_rs_col_write; 331 rX00_rs_tex = r500_rs_tex; 332 rX00_rs_tex_write = r500_rs_tex_write; 333 } else { 334 rX00_rs_col = r300_rs_col; 335 rX00_rs_col_write = r300_rs_col_write; 336 rX00_rs_tex = r300_rs_tex; 337 rX00_rs_tex_write = r300_rs_tex_write; 338 } 339 340 /* 0x5555 copied from classic, which means: 341 * Select user color 0 for COLOR0 up to COLOR7. 342 * What the hell does that mean? */ 343 rs.vap_vtx_state_cntl = 0x5555; 344 345 /* The position is always present in VAP. */ 346 rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_POS; 347 rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT; 348 stream_loc_notcl[loc++] = 0; 349 350 /* Set up the point size in VAP. */ 351 if (vs_outputs->psize != ATTR_UNUSED) { 352 rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT; 353 stream_loc_notcl[loc++] = 1; 354 } 355 356 /* Set up and rasterize colors. */ 357 for (i = 0; i < ATTR_COLOR_COUNT; i++) { 358 if (vs_outputs->color[i] != ATTR_UNUSED || any_bcolor_used || 359 vs_outputs->color[1] != ATTR_UNUSED) { 360 /* Set up the color in VAP. */ 361 rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_COLOR; 362 rs.vap_out_vtx_fmt[0] |= 363 R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << i; 364 stream_loc_notcl[loc++] = 2 + i; 365 366 /* Rasterize it. */ 367 rX00_rs_col(&rs, col_count, col_count, SWIZ_XYZW); 368 369 /* Write it to the FS input register if it's needed by the FS. */ 370 if (fs_inputs->color[i] != ATTR_UNUSED) { 371 rX00_rs_col_write(&rs, col_count, fp_offset, WRITE_COLOR); 372 fp_offset++; 373 374 DBG(r300, DBG_RS, 375 "r300: Rasterized color %i written to FS.\n", i); 376 } else { 377 DBG(r300, DBG_RS, "r300: Rasterized color %i unused.\n", i); 378 } 379 col_count++; 380 } else { 381 /* Skip the FS input register, leave it uninitialized. */ 382 /* If we try to set it to (0,0,0,1), it will lock up. */ 383 if (fs_inputs->color[i] != ATTR_UNUSED) { 384 fp_offset++; 385 386 DBG(r300, DBG_RS, "r300: FS input color %i unassigned%s.\n", 387 i); 388 } 389 } 390 } 391 392 /* Set up back-face colors. The rasterizer will do the color selection 393 * automatically. */ 394 if (any_bcolor_used) { 395 if (r300->two_sided_color) { 396 /* Rasterize as back-face colors. */ 397 for (i = 0; i < ATTR_COLOR_COUNT; i++) { 398 rs.vap_vsm_vtx_assm |= R300_INPUT_CNTL_COLOR; 399 rs.vap_out_vtx_fmt[0] |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT << (2+i); 400 stream_loc_notcl[loc++] = 4 + i; 401 } 402 } else { 403 /* Rasterize two fake texcoords to prevent from the two-sided color 404 * selection. */ 405 /* XXX Consider recompiling the vertex shader to save 2 RS units. */ 406 for (i = 0; i < 2; i++) { 407 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count); 408 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count)); 409 stream_loc_notcl[loc++] = 6 + tex_count; 410 411 /* Rasterize it. */ 412 rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_XYZW); 413 tex_count++; 414 tex_ptr += 4; 415 } 416 } 417 } 418 419 /* gl_FrontFacing. 420 * Note that we can use either the two-sided color selection based on 421 * the front and back vertex shader colors, or gl_FrontFacing, 422 * but not both! It locks up otherwise. 423 * 424 * In Direct3D 9, the two-sided color selection can be used 425 * with shaders 2.0 only, while gl_FrontFacing can be used 426 * with shaders 3.0 only. The hardware apparently hasn't been designed 427 * to support both at the same time. */ 428 if (r300->screen->caps.is_r500 && fs_inputs->face != ATTR_UNUSED && 429 !(any_bcolor_used && r300->two_sided_color)) { 430 rX00_rs_col(&rs, col_count, col_count, SWIZ_XYZW); 431 rX00_rs_col_write(&rs, col_count, fp_offset, WRITE_FACE); 432 fp_offset++; 433 col_count++; 434 DBG(r300, DBG_RS, "r300: Rasterized FACE written to FS.\n"); 435 } else if (fs_inputs->face != ATTR_UNUSED) { 436 fprintf(stderr, "r300: ERROR: FS input FACE unassigned.\n"); 437 } 438 439 /* Rasterize texture coordinates. */ 440 for (i = 0; i < ATTR_GENERIC_COUNT && tex_count < 8; i++) { 441 boolean sprite_coord = false; 442 443 if (fs_inputs->generic[i] != ATTR_UNUSED) { 444 sprite_coord = !!(r300->sprite_coord_enable & (1 << i)); 445 } 446 447 if (vs_outputs->generic[i] != ATTR_UNUSED || sprite_coord) { 448 if (!sprite_coord) { 449 /* Set up the texture coordinates in VAP. */ 450 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count); 451 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count)); 452 stream_loc_notcl[loc++] = 6 + tex_count; 453 } else 454 stuffing_enable |= 455 R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (tex_count*2)); 456 457 /* Rasterize it. */ 458 rX00_rs_tex(&rs, tex_count, tex_ptr, 459 sprite_coord ? SWIZ_XY01 : SWIZ_XYZW); 460 461 /* Write it to the FS input register if it's needed by the FS. */ 462 if (fs_inputs->generic[i] != ATTR_UNUSED) { 463 rX00_rs_tex_write(&rs, tex_count, fp_offset); 464 fp_offset++; 465 466 DBG(r300, DBG_RS, 467 "r300: Rasterized generic %i written to FS%s in texcoord %d.\n", 468 i, sprite_coord ? " (sprite coord)" : "", tex_count); 469 } else { 470 DBG(r300, DBG_RS, 471 "r300: Rasterized generic %i unused%s.\n", 472 i, sprite_coord ? " (sprite coord)" : ""); 473 } 474 tex_count++; 475 tex_ptr += sprite_coord ? 2 : 4; 476 } else { 477 /* Skip the FS input register, leave it uninitialized. */ 478 /* If we try to set it to (0,0,0,1), it will lock up. */ 479 if (fs_inputs->generic[i] != ATTR_UNUSED) { 480 fp_offset++; 481 482 DBG(r300, DBG_RS, "r300: FS input generic %i unassigned%s.\n", 483 i, sprite_coord ? " (sprite coord)" : ""); 484 } 485 } 486 } 487 488 for (; i < ATTR_GENERIC_COUNT; i++) { 489 if (fs_inputs->generic[i] != ATTR_UNUSED) { 490 fprintf(stderr, "r300: ERROR: FS input generic %i unassigned, " 491 "not enough hardware slots (it's not a bug, do not " 492 "report it).\n", i); 493 } 494 } 495 496 /* Rasterize fog coordinates. */ 497 if (vs_outputs->fog != ATTR_UNUSED && tex_count < 8) { 498 /* Set up the fog coordinates in VAP. */ 499 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count); 500 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count)); 501 stream_loc_notcl[loc++] = 6 + tex_count; 502 503 /* Rasterize it. */ 504 rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_X001); 505 506 /* Write it to the FS input register if it's needed by the FS. */ 507 if (fs_inputs->fog != ATTR_UNUSED) { 508 rX00_rs_tex_write(&rs, tex_count, fp_offset); 509 fp_offset++; 510 511 DBG(r300, DBG_RS, "r300: Rasterized fog written to FS.\n"); 512 } else { 513 DBG(r300, DBG_RS, "r300: Rasterized fog unused.\n"); 514 } 515 tex_count++; 516 tex_ptr += 4; 517 } else { 518 /* Skip the FS input register, leave it uninitialized. */ 519 /* If we try to set it to (0,0,0,1), it will lock up. */ 520 if (fs_inputs->fog != ATTR_UNUSED) { 521 fp_offset++; 522 523 if (tex_count < 8) { 524 DBG(r300, DBG_RS, "r300: FS input fog unassigned.\n"); 525 } else { 526 fprintf(stderr, "r300: ERROR: FS input fog unassigned, " 527 "not enough hardware slots. (it's not a bug, " 528 "do not report it)\n"); 529 } 530 } 531 } 532 533 /* Rasterize WPOS. */ 534 /* Don't set it in VAP if the FS doesn't need it. */ 535 if (fs_inputs->wpos != ATTR_UNUSED && tex_count < 8) { 536 /* Set up the WPOS coordinates in VAP. */ 537 rs.vap_vsm_vtx_assm |= (R300_INPUT_CNTL_TC0 << tex_count); 538 rs.vap_out_vtx_fmt[1] |= (4 << (3 * tex_count)); 539 stream_loc_notcl[loc++] = 6 + tex_count; 540 541 /* Rasterize it. */ 542 rX00_rs_tex(&rs, tex_count, tex_ptr, SWIZ_XYZW); 543 544 /* Write it to the FS input register. */ 545 rX00_rs_tex_write(&rs, tex_count, fp_offset); 546 547 DBG(r300, DBG_RS, "r300: Rasterized WPOS written to FS.\n"); 548 549 fp_offset++; 550 tex_count++; 551 tex_ptr += 4; 552 } else { 553 if (fs_inputs->wpos != ATTR_UNUSED && tex_count >= 8) { 554 fprintf(stderr, "r300: ERROR: FS input WPOS unassigned, " 555 "not enough hardware slots. (it's not a bug, do not " 556 "report it)\n"); 557 } 558 } 559 560 /* Invalidate the rest of the no-TCL (GA) stream locations. */ 561 for (; loc < 16;) { 562 stream_loc_notcl[loc++] = -1; 563 } 564 565 /* Rasterize at least one color, or bad things happen. */ 566 if (col_count == 0 && tex_count == 0) { 567 rX00_rs_col(&rs, 0, 0, SWIZ_0001); 568 col_count++; 569 570 DBG(r300, DBG_RS, "r300: Rasterized color 0 to prevent lockups.\n"); 571 } 572 573 DBG(r300, DBG_RS, "r300: --- Rasterizer status ---: colors: %i, " 574 "generics: %i.\n", col_count, tex_count); 575 576 rs.count = MIN2(tex_ptr, 32) | (col_count << R300_IC_COUNT_SHIFT) | 577 R300_HIRES_EN; 578 579 count = MAX3(col_count, tex_count, 1); 580 rs.inst_count = count - 1; 581 582 /* set the GB enable flags */ 583 if (r300->sprite_coord_enable) 584 stuffing_enable |= R300_GB_POINT_STUFF_ENABLE; 585 586 rs.gb_enable = stuffing_enable; 587 588 /* Now, after all that, see if we actually need to update the state. */ 589 if (memcmp(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block))) { 590 memcpy(r300->rs_block_state.state, &rs, sizeof(struct r300_rs_block)); 591 r300->rs_block_state.size = 13 + count*2; 592 } 593} 594 595static void rgba_to_bgra(float color[4]) 596{ 597 float x = color[0]; 598 color[0] = color[2]; 599 color[2] = x; 600} 601 602static uint32_t r300_get_border_color(enum pipe_format format, 603 const float border[4], 604 boolean is_r500) 605{ 606 const struct util_format_description *desc; 607 float border_swizzled[4] = {0}; 608 union util_color uc = {0}; 609 610 desc = util_format_description(format); 611 612 /* Do depth formats first. */ 613 if (util_format_is_depth_or_stencil(format)) { 614 switch (format) { 615 case PIPE_FORMAT_Z16_UNORM: 616 return util_pack_z(PIPE_FORMAT_Z16_UNORM, border[0]); 617 case PIPE_FORMAT_X8Z24_UNORM: 618 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 619 if (is_r500) { 620 return util_pack_z(PIPE_FORMAT_X8Z24_UNORM, border[0]); 621 } else { 622 return util_pack_z(PIPE_FORMAT_Z16_UNORM, border[0]) << 16; 623 } 624 default: 625 assert(0); 626 return 0; 627 } 628 } 629 630 /* Apply inverse swizzle of the format. */ 631 util_format_unswizzle_4f(border_swizzled, border, desc->swizzle); 632 633 /* Compressed formats. */ 634 if (util_format_is_compressed(format)) { 635 switch (format) { 636 case PIPE_FORMAT_RGTC1_SNORM: 637 case PIPE_FORMAT_LATC1_SNORM: 638 border_swizzled[0] = border_swizzled[0] < 0 ? 639 border_swizzled[0]*0.5+1 : 640 border_swizzled[0]*0.5; 641 /* Pass through. */ 642 643 case PIPE_FORMAT_RGTC1_UNORM: 644 case PIPE_FORMAT_LATC1_UNORM: 645 /* Add 1/32 to round the border color instead of truncating. */ 646 /* The Y component is used for the border color. */ 647 border_swizzled[1] = border_swizzled[0] + 1.0f/32; 648 util_pack_color(border_swizzled, PIPE_FORMAT_B4G4R4A4_UNORM, &uc); 649 return uc.ui; 650 case PIPE_FORMAT_RGTC2_SNORM: 651 case PIPE_FORMAT_LATC2_SNORM: 652 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc); 653 return uc.ui; 654 case PIPE_FORMAT_RGTC2_UNORM: 655 case PIPE_FORMAT_LATC2_UNORM: 656 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc); 657 return uc.ui; 658 case PIPE_FORMAT_DXT1_SRGB: 659 case PIPE_FORMAT_DXT1_SRGBA: 660 case PIPE_FORMAT_DXT3_SRGBA: 661 case PIPE_FORMAT_DXT5_SRGBA: 662 util_pack_color(border_swizzled, PIPE_FORMAT_B8G8R8A8_SRGB, &uc); 663 return uc.ui; 664 default: 665 util_pack_color(border_swizzled, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 666 return uc.ui; 667 } 668 } 669 670 switch (desc->channel[0].size) { 671 case 2: 672 rgba_to_bgra(border_swizzled); 673 util_pack_color(border_swizzled, PIPE_FORMAT_B2G3R3_UNORM, &uc); 674 break; 675 676 case 4: 677 rgba_to_bgra(border_swizzled); 678 util_pack_color(border_swizzled, PIPE_FORMAT_B4G4R4A4_UNORM, &uc); 679 break; 680 681 case 5: 682 rgba_to_bgra(border_swizzled); 683 if (desc->channel[1].size == 5) { 684 util_pack_color(border_swizzled, PIPE_FORMAT_B5G5R5A1_UNORM, &uc); 685 } else if (desc->channel[1].size == 6) { 686 util_pack_color(border_swizzled, PIPE_FORMAT_B5G6R5_UNORM, &uc); 687 } else { 688 assert(0); 689 } 690 break; 691 692 default: 693 case 8: 694 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) { 695 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc); 696 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 697 if (desc->nr_channels == 2) { 698 border_swizzled[3] = border_swizzled[1]; 699 util_pack_color(border_swizzled, PIPE_FORMAT_L8A8_SRGB, &uc); 700 } else { 701 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SRGB, &uc); 702 } 703 } else { 704 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc); 705 } 706 break; 707 708 case 10: 709 util_pack_color(border_swizzled, PIPE_FORMAT_R10G10B10A2_UNORM, &uc); 710 break; 711 712 case 16: 713 if (desc->nr_channels <= 2) { 714 if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) { 715 util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_FLOAT, &uc); 716 } else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) { 717 util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_SNORM, &uc); 718 } else { 719 util_pack_color(border_swizzled, PIPE_FORMAT_R16G16_UNORM, &uc); 720 } 721 } else { 722 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) { 723 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_SNORM, &uc); 724 } else { 725 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc); 726 } 727 } 728 break; 729 730 case 32: 731 if (desc->nr_channels == 1) { 732 util_pack_color(border_swizzled, PIPE_FORMAT_R32_FLOAT, &uc); 733 } else { 734 util_pack_color(border_swizzled, PIPE_FORMAT_R8G8B8A8_UNORM, &uc); 735 } 736 break; 737 } 738 739 return uc.ui; 740} 741 742static void r300_merge_textures_and_samplers(struct r300_context* r300) 743{ 744 struct r300_textures_state *state = 745 (struct r300_textures_state*)r300->textures_state.state; 746 struct r300_texture_sampler_state *texstate; 747 struct r300_sampler_state *sampler; 748 struct r300_sampler_view *view; 749 struct r300_resource *tex; 750 unsigned base_level, min_level, level_count, i, j, size; 751 unsigned count = MIN2(state->sampler_view_count, 752 state->sampler_state_count); 753 boolean has_us_format = r300->screen->caps.has_us_format; 754 755 /* The KIL opcode fix, see below. */ 756 if (!count && !r300->screen->caps.is_r500) 757 count = 1; 758 759 state->tx_enable = 0; 760 state->count = 0; 761 size = 2; 762 763 for (i = 0; i < count; i++) { 764 if (state->sampler_views[i] && state->sampler_states[i]) { 765 state->tx_enable |= 1 << i; 766 767 view = state->sampler_views[i]; 768 tex = r300_resource(view->base.texture); 769 sampler = state->sampler_states[i]; 770 771 texstate = &state->regs[i]; 772 texstate->format = view->format; 773 texstate->filter0 = sampler->filter0; 774 texstate->filter1 = sampler->filter1; 775 776 /* Set the border color. */ 777 texstate->border_color = 778 r300_get_border_color(view->base.format, 779 sampler->state.border_color.f, 780 r300->screen->caps.is_r500); 781 782 /* determine min/max levels */ 783 base_level = view->base.u.tex.first_level; 784 min_level = sampler->min_lod; 785 level_count = MIN3(sampler->max_lod, 786 tex->b.b.last_level - base_level, 787 view->base.u.tex.last_level - base_level); 788 789 if (base_level + min_level) { 790 unsigned offset; 791 792 if (tex->tex.is_npot) { 793 /* Even though we do not implement mipmapping for NPOT 794 * textures, we should at least honor the minimum level 795 * which is allowed to be displayed. We do this by setting up 796 * an i-th mipmap level as the zero level. */ 797 base_level += min_level; 798 } 799 offset = tex->tex.offset_in_bytes[base_level]; 800 801 r300_texture_setup_format_state(r300->screen, tex, 802 view->base.format, 803 base_level, 804 view->width0_override, 805 view->height0_override, 806 &texstate->format); 807 texstate->format.tile_config |= offset & 0xffffffe0; 808 assert((offset & 0x1f) == 0); 809 } 810 811 /* Assign a texture cache region. */ 812 texstate->format.format1 |= view->texcache_region; 813 814 /* Depth textures are kinda special. */ 815 if (util_format_is_depth_or_stencil(view->base.format)) { 816 unsigned char depth_swizzle[4]; 817 818 if (!r300->screen->caps.is_r500 && 819 util_format_get_blocksizebits(view->base.format) == 32) { 820 /* X24x8 is sampled as Y16X16 on r3xx-r4xx. 821 * The depth here is at the Y component. */ 822 for (j = 0; j < 4; j++) 823 depth_swizzle[j] = UTIL_FORMAT_SWIZZLE_Y; 824 } else { 825 for (j = 0; j < 4; j++) 826 depth_swizzle[j] = UTIL_FORMAT_SWIZZLE_X; 827 } 828 829 /* If compare mode is disabled, sampler view swizzles 830 * are stored in the format. 831 * Otherwise, the swizzles must be applied after the compare 832 * mode in the fragment shader. */ 833 if (sampler->state.compare_mode == PIPE_TEX_COMPARE_NONE) { 834 texstate->format.format1 |= 835 r300_get_swizzle_combined(depth_swizzle, 836 view->swizzle, FALSE); 837 } else { 838 texstate->format.format1 |= 839 r300_get_swizzle_combined(depth_swizzle, 0, FALSE); 840 } 841 } 842 843 if (r300->screen->caps.dxtc_swizzle && 844 util_format_is_compressed(view->base.format)) { 845 texstate->filter1 |= R400_DXTC_SWIZZLE_ENABLE; 846 } 847 848 /* to emulate 1D textures through 2D ones correctly */ 849 if (tex->b.b.target == PIPE_TEXTURE_1D) { 850 texstate->filter0 &= ~R300_TX_WRAP_T_MASK; 851 texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE); 852 } 853 854 /* The hardware doesn't like CLAMP and CLAMP_TO_BORDER 855 * for the 3rd coordinate if the texture isn't 3D. */ 856 if (tex->b.b.target != PIPE_TEXTURE_3D) { 857 texstate->filter0 &= ~R300_TX_WRAP_R_MASK; 858 } 859 860 if (tex->tex.is_npot) { 861 /* NPOT textures don't support mip filter, unfortunately. 862 * This prevents incorrect rendering. */ 863 texstate->filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK; 864 865 /* Mask out the mirrored flag. */ 866 if (texstate->filter0 & R300_TX_WRAP_S(R300_TX_MIRRORED)) { 867 texstate->filter0 &= ~R300_TX_WRAP_S(R300_TX_MIRRORED); 868 } 869 if (texstate->filter0 & R300_TX_WRAP_T(R300_TX_MIRRORED)) { 870 texstate->filter0 &= ~R300_TX_WRAP_T(R300_TX_MIRRORED); 871 } 872 873 /* Change repeat to clamp-to-edge. 874 * (the repeat bit has a value of 0, no masking needed). */ 875 if ((texstate->filter0 & R300_TX_WRAP_S_MASK) == 876 R300_TX_WRAP_S(R300_TX_REPEAT)) { 877 texstate->filter0 |= R300_TX_WRAP_S(R300_TX_CLAMP_TO_EDGE); 878 } 879 if ((texstate->filter0 & R300_TX_WRAP_T_MASK) == 880 R300_TX_WRAP_T(R300_TX_REPEAT)) { 881 texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE); 882 } 883 } else { 884 /* the MAX_MIP level is the largest (finest) one */ 885 texstate->format.format0 |= R300_TX_NUM_LEVELS(level_count); 886 texstate->filter0 |= R300_TX_MAX_MIP_LEVEL(min_level); 887 } 888 889 /* Float textures only support nearest and mip-nearest filtering. */ 890 if (util_format_is_float(view->base.format)) { 891 /* No MAG linear filtering. */ 892 if ((texstate->filter0 & R300_TX_MAG_FILTER_MASK) == 893 R300_TX_MAG_FILTER_LINEAR) { 894 texstate->filter0 &= ~R300_TX_MAG_FILTER_MASK; 895 texstate->filter0 |= R300_TX_MAG_FILTER_NEAREST; 896 } 897 /* No MIN linear filtering. */ 898 if ((texstate->filter0 & R300_TX_MIN_FILTER_MASK) == 899 R300_TX_MIN_FILTER_LINEAR) { 900 texstate->filter0 &= ~R300_TX_MIN_FILTER_MASK; 901 texstate->filter0 |= R300_TX_MIN_FILTER_NEAREST; 902 } 903 /* No mipmap linear filtering. */ 904 if ((texstate->filter0 & R300_TX_MIN_FILTER_MIP_MASK) == 905 R300_TX_MIN_FILTER_MIP_LINEAR) { 906 texstate->filter0 &= ~R300_TX_MIN_FILTER_MIP_MASK; 907 texstate->filter0 |= R300_TX_MIN_FILTER_MIP_NEAREST; 908 } 909 /* No anisotropic filtering. */ 910 texstate->filter0 &= ~R300_TX_MAX_ANISO_MASK; 911 texstate->filter1 &= ~R500_TX_MAX_ANISO_MASK; 912 texstate->filter1 &= ~R500_TX_ANISO_HIGH_QUALITY; 913 } 914 915 texstate->filter0 |= i << 28; 916 917 size += 16 + (has_us_format ? 2 : 0); 918 state->count = i+1; 919 } else { 920 /* For the KIL opcode to work on r3xx-r4xx, the texture unit 921 * assigned to this opcode (it's always the first one) must be 922 * enabled. Otherwise the opcode doesn't work. 923 * 924 * In order to not depend on the fragment shader, we just make 925 * the first unit enabled all the time. */ 926 if (i == 0 && !r300->screen->caps.is_r500) { 927 pipe_sampler_view_reference( 928 (struct pipe_sampler_view**)&state->sampler_views[i], 929 &r300->texkill_sampler->base); 930 931 state->tx_enable |= 1 << i; 932 933 texstate = &state->regs[i]; 934 935 /* Just set some valid state. */ 936 texstate->format = r300->texkill_sampler->format; 937 texstate->filter0 = 938 r300_translate_tex_filters(PIPE_TEX_FILTER_NEAREST, 939 PIPE_TEX_FILTER_NEAREST, 940 PIPE_TEX_FILTER_NEAREST, 941 FALSE); 942 texstate->filter1 = 0; 943 texstate->border_color = 0; 944 945 texstate->filter0 |= i << 28; 946 size += 16 + (has_us_format ? 2 : 0); 947 state->count = i+1; 948 } 949 } 950 } 951 952 r300->textures_state.size = size; 953 954 /* Pick a fragment shader based on either the texture compare state 955 * or the uses_pitch flag or some other external state. */ 956 if (count && 957 r300->fs_status == FRAGMENT_SHADER_VALID) { 958 r300->fs_status = FRAGMENT_SHADER_MAYBE_DIRTY; 959 } 960} 961 962static void r300_decompress_depth_textures(struct r300_context *r300) 963{ 964 struct r300_textures_state *state = 965 (struct r300_textures_state*)r300->textures_state.state; 966 struct pipe_resource *tex; 967 unsigned count = MIN2(state->sampler_view_count, 968 state->sampler_state_count); 969 unsigned i; 970 971 if (!r300->locked_zbuffer) { 972 return; 973 } 974 975 for (i = 0; i < count; i++) { 976 if (state->sampler_views[i] && state->sampler_states[i]) { 977 tex = state->sampler_views[i]->base.texture; 978 979 if (tex == r300->locked_zbuffer->texture) { 980 r300_decompress_zmask_locked(r300); 981 return; 982 } 983 } 984 } 985} 986 987static void r300_validate_fragment_shader(struct r300_context *r300) 988{ 989 struct pipe_framebuffer_state *fb = r300->fb_state.state; 990 991 if (r300->fs.state && r300->fs_status != FRAGMENT_SHADER_VALID) { 992 /* Pick the fragment shader based on external states. 993 * Then mark the state dirty if the fragment shader is either dirty 994 * or the function r300_pick_fragment_shader changed the shader. */ 995 if (r300_pick_fragment_shader(r300) || 996 r300->fs_status == FRAGMENT_SHADER_DIRTY) { 997 /* Mark the state atom as dirty. */ 998 r300_mark_fs_code_dirty(r300); 999 1000 /* Does Multiwrite need to be changed? */ 1001 if (fb->nr_cbufs > 1) { 1002 boolean new_multiwrite = 1003 r300_fragment_shader_writes_all(r300_fs(r300)); 1004 1005 if (r300->fb_multiwrite != new_multiwrite) { 1006 r300->fb_multiwrite = new_multiwrite; 1007 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE); 1008 } 1009 } 1010 } 1011 r300->fs_status = FRAGMENT_SHADER_VALID; 1012 } 1013} 1014 1015void r300_update_derived_state(struct r300_context* r300) 1016{ 1017 if (r300->textures_state.dirty) { 1018 r300_decompress_depth_textures(r300); 1019 r300_merge_textures_and_samplers(r300); 1020 } 1021 1022 r300_validate_fragment_shader(r300); 1023 1024 if (r300->rs_block_state.dirty) { 1025 r300_update_rs_block(r300); 1026 1027 if (r300->draw) { 1028 memset(&r300->vertex_info, 0, sizeof(struct vertex_info)); 1029 r300_draw_emit_all_attribs(r300); 1030 draw_compute_vertex_size(&r300->vertex_info); 1031 r300_swtcl_vertex_psc(r300); 1032 } 1033 } 1034 1035 r300_update_hyperz_state(r300); 1036} 1037