1//===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14
15#include "SIInstrInfo.h"
16#include "AMDGPUTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/MC/MCInstrDesc.h"
20
21#include <stdio.h>
22
23using namespace llvm;
24
25SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
26  : AMDGPUInstrInfo(tm),
27    RI(tm, *this),
28    TM(tm)
29    { }
30
31const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const
32{
33  return RI;
34}
35
36void
37SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
38                           MachineBasicBlock::iterator MI, DebugLoc DL,
39                           unsigned DestReg, unsigned SrcReg,
40                           bool KillSrc) const
41{
42
43  // If we are trying to copy to or from SCC, there is a bug somewhere else in
44  // the backend.  While it may be theoretically possible to do this, it should
45  // never be necessary.
46  assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
47
48  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
49   .addReg(SrcReg, getKillRegState(KillSrc));
50}
51
52MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
53                                           int64_t Imm) const
54{
55  MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
56  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
57  MachineInstrBuilder(MI).addImm(Imm);
58
59  return MI;
60
61}
62
63bool SIInstrInfo::isMov(unsigned Opcode) const
64{
65  switch(Opcode) {
66  default: return false;
67  case AMDGPU::S_MOV_B32:
68  case AMDGPU::S_MOV_B64:
69  case AMDGPU::V_MOV_B32_e32:
70  case AMDGPU::V_MOV_B32_e64:
71  case AMDGPU::V_MOV_IMM_F32:
72  case AMDGPU::V_MOV_IMM_I32:
73  case AMDGPU::S_MOV_IMM_I32:
74    return true;
75  }
76}
77