1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===// 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// The LLVM Compiler Infrastructure 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// This file is distributed under the University of Illinois Open Source 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// License. See LICENSE.TXT for details. 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org//===----------------------------------------------------------------------===// 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// SI Implementation of TargetInstrInfo. 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org// 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org//===----------------------------------------------------------------------===// 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "SIInstrInfo.h" 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "AMDGPUTargetMachine.h" 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "llvm/CodeGen/MachineInstrBuilder.h" 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "llvm/CodeGen/MachineRegisterInfo.h" 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "llvm/MC/MCInstrDesc.h" 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include <stdio.h> 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgusing namespace llvm; 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 25f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgSIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm) 26f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org : AMDGPUInstrInfo(tm), 27f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org RI(tm, *this), 28f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org TM(tm) 29f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org { } 30f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 31f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgconst SIRegisterInfo &SIInstrInfo::getRegisterInfo() const 32f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 33f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return RI; 34f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 35f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 36f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid 37f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgSIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 38f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org MachineBasicBlock::iterator MI, DebugLoc DL, 39f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned DestReg, unsigned SrcReg, 40f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org bool KillSrc) const 41f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 42f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 43f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org // If we are trying to copy to or from SCC, there is a bug somewhere else in 44f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org // the backend. While it may be theoretically possible to do this, it should 45f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org // never be necessary. 46f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); 47f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 48f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) 49f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org .addReg(SrcReg, getKillRegState(KillSrc)); 50f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 51f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 52f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgMachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, 53f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int64_t Imm) const 54f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 55f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); 56f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); 57f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org MachineInstrBuilder(MI).addImm(Imm); 58f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 59f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return MI; 60f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 61f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 62f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 63f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgbool SIInstrInfo::isMov(unsigned Opcode) const 64f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 65f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org switch(Opcode) { 66f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org default: return false; 67f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::S_MOV_B32: 68f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::S_MOV_B64: 69f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::V_MOV_B32_e32: 70f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::V_MOV_B32_e64: 71f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::V_MOV_IMM_F32: 72f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::V_MOV_IMM_I32: 73f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case AMDGPU::S_MOV_IMM_I32: 74f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return true; 75f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 76f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 77