1//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14
15#ifndef SIINSTRINFO_H
16#define SIINSTRINFO_H
17
18#include "AMDGPUInstrInfo.h"
19#include "SIRegisterInfo.h"
20
21namespace llvm {
22
23class SIInstrInfo : public AMDGPUInstrInfo {
24private:
25  const SIRegisterInfo RI;
26  AMDGPUTargetMachine &TM;
27
28public:
29  explicit SIInstrInfo(AMDGPUTargetMachine &tm);
30
31  const SIRegisterInfo &getRegisterInfo() const;
32
33  virtual void copyPhysReg(MachineBasicBlock &MBB,
34                           MachineBasicBlock::iterator MI, DebugLoc DL,
35                           unsigned DestReg, unsigned SrcReg,
36                           bool KillSrc) const;
37
38  /// getEncodingType - Returns the encoding type of this instruction.
39  unsigned getEncodingType(const MachineInstr &MI) const;
40
41  /// getEncodingBytes - Returns the size of this instructions encoding in
42  /// number of bytes.
43  unsigned getEncodingBytes(const MachineInstr &MI) const;
44
45  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
46                                        int64_t Imm) const;
47
48  virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
49  virtual bool isMov(unsigned Opcode) const;
50
51  };
52
53} // End namespace llvm
54
55namespace SIInstrFlags {
56  enum Flags {
57    // First 4 bits are the instruction encoding
58    NEED_WAIT = 1 << 4
59  };
60}
61
62#endif //SIINSTRINFO_H
63