1/*
2 * Copyright © 2009 Corbin Simpson
3 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 */
27/*
28 * Authors:
29 *      Corbin Simpson <MostAwesomeDude@gmail.com>
30 *      Joakim Sindholt <opensource@zhasha.com>
31 *      Marek Olšák <maraeo@gmail.com>
32 */
33
34#include "radeon_drm_bo.h"
35#include "radeon_drm_cs.h"
36#include "radeon_drm_public.h"
37
38#include "pipebuffer/pb_bufmgr.h"
39#include "util/u_memory.h"
40
41#include <xf86drm.h>
42#include <stdio.h>
43
44/*
45 * this are copy from radeon_drm, once an updated libdrm is released
46 * we should bump configure.ac requirement for it and remove the following
47 * field
48 */
49#ifndef RADEON_INFO_TILING_CONFIG
50#define RADEON_INFO_TILING_CONFIG 6
51#endif
52
53#ifndef RADEON_INFO_WANT_HYPERZ
54#define RADEON_INFO_WANT_HYPERZ 7
55#endif
56
57#ifndef RADEON_INFO_WANT_CMASK
58#define RADEON_INFO_WANT_CMASK 8
59#endif
60
61#ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
62#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
63#endif
64
65#ifndef RADEON_INFO_NUM_BACKENDS
66#define RADEON_INFO_NUM_BACKENDS 0xa
67#endif
68
69#ifndef RADEON_INFO_NUM_TILE_PIPES
70#define RADEON_INFO_NUM_TILE_PIPES 0xb
71#endif
72
73#ifndef RADEON_INFO_BACKEND_MAP
74#define RADEON_INFO_BACKEND_MAP 0xd
75#endif
76
77#ifndef RADEON_INFO_VA_START
78/* virtual address start, va < start are reserved by the kernel */
79#define RADEON_INFO_VA_START        0x0e
80/* maximum size of ib using the virtual memory cs */
81#define RADEON_INFO_IB_VM_MAX_SIZE  0x0f
82#endif
83
84#ifndef RADEON_INFO_MAX_PIPES
85#define RADEON_INFO_MAX_PIPES 0x10
86#endif
87
88#ifndef RADEON_INFO_TIMESTAMP
89#define RADEON_INFO_TIMESTAMP 0x11
90#endif
91
92
93/* Enable/disable feature access for one command stream.
94 * If enable == TRUE, return TRUE on success.
95 * Otherwise, return FALSE.
96 *
97 * We basically do the same thing kernel does, because we have to deal
98 * with multiple contexts (here command streams) backed by one winsys. */
99static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
100                                    struct radeon_drm_cs **owner,
101                                    pipe_mutex *mutex,
102                                    unsigned request, boolean enable)
103{
104    struct drm_radeon_info info;
105    unsigned value = enable ? 1 : 0;
106
107    memset(&info, 0, sizeof(info));
108
109    pipe_mutex_lock(*mutex);
110
111    /* Early exit if we are sure the request will fail. */
112    if (enable) {
113        if (*owner) {
114            pipe_mutex_unlock(*mutex);
115            return FALSE;
116        }
117    } else {
118        if (*owner != applier) {
119            pipe_mutex_unlock(*mutex);
120            return FALSE;
121        }
122    }
123
124    /* Pass through the request to the kernel. */
125    info.value = (unsigned long)&value;
126    info.request = request;
127    if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
128                            &info, sizeof(info)) != 0) {
129        pipe_mutex_unlock(*mutex);
130        return FALSE;
131    }
132
133    /* Update the rights in the winsys. */
134    if (enable) {
135        if (value) {
136            *owner = applier;
137            fprintf(stderr, "radeon: Acquired Hyper-Z.\n");
138            pipe_mutex_unlock(*mutex);
139            return TRUE;
140        }
141    } else {
142        *owner = NULL;
143        fprintf(stderr, "radeon: Released Hyper-Z.\n");
144    }
145
146    pipe_mutex_unlock(*mutex);
147    return FALSE;
148}
149
150static boolean radeon_get_drm_value(int fd, unsigned request,
151                                    const char *errname, uint32_t *out)
152{
153    struct drm_radeon_info info;
154    int retval;
155
156    memset(&info, 0, sizeof(info));
157
158    info.value = (unsigned long)out;
159    info.request = request;
160
161    retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
162    if (retval) {
163        if (errname) {
164            fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
165                    errname, retval);
166        }
167        return FALSE;
168    }
169    return TRUE;
170}
171
172/* Helper function to do the ioctls needed for setup and init. */
173static boolean do_winsys_init(struct radeon_drm_winsys *ws)
174{
175    struct drm_radeon_gem_info gem_info;
176    int retval;
177    drmVersionPtr version;
178
179    memset(&gem_info, 0, sizeof(gem_info));
180
181    /* We do things in a specific order here.
182     *
183     * DRM version first. We need to be sure we're running on a KMS chipset.
184     * This is also for some features.
185     *
186     * Then, the PCI ID. This is essential and should return usable numbers
187     * for all Radeons. If this fails, we probably got handed an FD for some
188     * non-Radeon card.
189     *
190     * The GEM info is actually bogus on the kernel side, as well as our side
191     * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
192     * we don't actually use the info for anything yet.
193     *
194     * The GB and Z pipe requests should always succeed, but they might not
195     * return sensical values for all chipsets, but that's alright because
196     * the pipe drivers already know that.
197     */
198
199    /* Get DRM version. */
200    version = drmGetVersion(ws->fd);
201    if (version->version_major != 2 ||
202        version->version_minor < 3) {
203        fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
204                "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
205                __FUNCTION__,
206                version->version_major,
207                version->version_minor,
208                version->version_patchlevel);
209        drmFreeVersion(version);
210        return FALSE;
211    }
212
213    ws->info.drm_major = version->version_major;
214    ws->info.drm_minor = version->version_minor;
215    ws->info.drm_patchlevel = version->version_patchlevel;
216    drmFreeVersion(version);
217
218    /* Get PCI ID. */
219    if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
220                              &ws->info.pci_id))
221        return FALSE;
222
223    /* Check PCI ID. */
224    switch (ws->info.pci_id) {
225#define CHIPSET(pci_id, name, family) case pci_id:
226#include "pci_ids/r300_pci_ids.h"
227#undef CHIPSET
228        ws->gen = R300;
229        break;
230
231#define CHIPSET(pci_id, name, family) case pci_id:
232#include "pci_ids/r600_pci_ids.h"
233#undef CHIPSET
234        ws->gen = R600;
235        break;
236
237#define CHIPSET(pci_id, name, family) case pci_id:
238#include "pci_ids/radeonsi_pci_ids.h"
239#undef CHIPSET
240        ws->gen = SI;
241        break;
242
243    default:
244        fprintf(stderr, "radeon: Invalid PCI ID.\n");
245        return FALSE;
246    }
247
248    /* Get GEM info. */
249    retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
250            &gem_info, sizeof(gem_info));
251    if (retval) {
252        fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
253                retval);
254        return FALSE;
255    }
256    ws->info.gart_size = gem_info.gart_size;
257    ws->info.vram_size = gem_info.vram_size;
258
259    ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
260
261    /* Generation-specific queries. */
262    if (ws->gen == R300) {
263        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
264                                  "GB pipe count",
265                                  &ws->info.r300_num_gb_pipes))
266            return FALSE;
267
268        if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
269                                  "Z pipe count",
270                                  &ws->info.r300_num_z_pipes))
271            return FALSE;
272    }
273    else if (ws->gen >= R600) {
274        if (ws->info.drm_minor >= 9 &&
275            !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
276                                  "num backends",
277                                  &ws->info.r600_num_backends))
278            return FALSE;
279
280        /* get the GPU counter frequency, failure is not fatal */
281        radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
282                             &ws->info.r600_clock_crystal_freq);
283
284        radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
285                             &ws->info.r600_tiling_config);
286
287        if (ws->info.drm_minor >= 11) {
288            radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
289                                 &ws->info.r600_num_tile_pipes);
290
291            if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
292                                      &ws->info.r600_backend_map))
293                ws->info.r600_backend_map_valid = TRUE;
294        }
295
296        ws->info.r600_virtual_address = FALSE;
297        if (ws->info.drm_minor >= 13) {
298            ws->info.r600_virtual_address = TRUE;
299            if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
300                                      &ws->info.r600_va_start))
301                ws->info.r600_virtual_address = FALSE;
302            if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
303                                      &ws->info.r600_ib_vm_max_size))
304                ws->info.r600_virtual_address = FALSE;
305        }
306        /* Remove this line once the virtual address space feature is fixed. */
307        if (ws->gen == R600 && !debug_get_bool_option("RADEON_VA", FALSE))
308            ws->info.r600_virtual_address = FALSE;
309    }
310
311    /* Get max pipes, this is only needed for compute shaders.  All evergreen+
312     * chips have at least 2 pipes, so we use 2 as a default. */
313    ws->info.r600_max_pipes = 2;
314    radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
315                         &ws->info.r600_max_pipes);
316
317    return TRUE;
318}
319
320static void radeon_winsys_destroy(struct radeon_winsys *rws)
321{
322    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
323
324    pipe_mutex_destroy(ws->hyperz_owner_mutex);
325    pipe_mutex_destroy(ws->cmask_owner_mutex);
326
327    ws->cman->destroy(ws->cman);
328    ws->kman->destroy(ws->kman);
329    if (ws->gen >= R600) {
330        radeon_surface_manager_free(ws->surf_man);
331    }
332    FREE(rws);
333}
334
335static void radeon_query_info(struct radeon_winsys *rws,
336                              struct radeon_info *info)
337{
338    *info = ((struct radeon_drm_winsys *)rws)->info;
339}
340
341static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
342                                         enum radeon_feature_id fid,
343                                         boolean enable)
344{
345    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
346
347    switch (fid) {
348    case RADEON_FID_R300_HYPERZ_ACCESS:
349        if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
350            return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
351                                        &cs->ws->hyperz_owner_mutex,
352                                        RADEON_INFO_WANT_HYPERZ, enable);
353        } else {
354            return FALSE;
355        }
356
357    case RADEON_FID_R300_CMASK_ACCESS:
358        if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
359            return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
360                                        &cs->ws->cmask_owner_mutex,
361                                        RADEON_INFO_WANT_CMASK, enable);
362        } else {
363            return FALSE;
364        }
365    }
366    return FALSE;
367}
368
369static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
370                                          struct radeon_surface *surf)
371{
372    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
373
374    return radeon_surface_init(ws->surf_man, surf);
375}
376
377static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
378                                          struct radeon_surface *surf)
379{
380    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
381
382    return radeon_surface_best(ws->surf_man, surf);
383}
384
385static uint64_t radeon_query_timestamp(struct radeon_winsys *rws)
386{
387    struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
388    uint64_t ts = 0;
389
390    if (ws->info.drm_minor < 20 ||
391        ws->gen < R600) {
392        assert(0);
393        return 0;
394    }
395
396    radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
397                         (uint32_t*)&ts);
398    return ts;
399}
400
401struct radeon_winsys *radeon_drm_winsys_create(int fd)
402{
403    struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
404    if (!ws) {
405        return NULL;
406    }
407
408    ws->fd = fd;
409
410    if (!do_winsys_init(ws))
411        goto fail;
412
413    /* Create managers. */
414    ws->kman = radeon_bomgr_create(ws);
415    if (!ws->kman)
416        goto fail;
417    ws->cman = pb_cache_manager_create(ws->kman, 1000000);
418    if (!ws->cman)
419        goto fail;
420
421    if (ws->gen >= R600) {
422        ws->surf_man = radeon_surface_manager_new(fd);
423        if (!ws->surf_man)
424            goto fail;
425    }
426
427    /* Set functions. */
428    ws->base.destroy = radeon_winsys_destroy;
429    ws->base.query_info = radeon_query_info;
430    ws->base.cs_request_feature = radeon_cs_request_feature;
431    ws->base.surface_init = radeon_drm_winsys_surface_init;
432    ws->base.surface_best = radeon_drm_winsys_surface_best;
433    ws->base.query_timestamp = radeon_query_timestamp;
434
435    radeon_bomgr_init_functions(ws);
436    radeon_drm_cs_init_functions(ws);
437
438    pipe_mutex_init(ws->hyperz_owner_mutex);
439    pipe_mutex_init(ws->cmask_owner_mutex);
440
441    return &ws->base;
442
443fail:
444    if (ws->cman)
445        ws->cman->destroy(ws->cman);
446    if (ws->kman)
447        ws->kman->destroy(ws->kman);
448    if (ws->surf_man)
449        radeon_surface_manager_free(ws->surf_man);
450    FREE(ws);
451    return NULL;
452}
453