1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32#include "brw_context.h"
33#include "brw_state.h"
34#include "brw_defines.h"
35
36static void
37brw_upload_clip_unit(struct brw_context *brw)
38{
39   struct intel_context *intel = &brw->intel;
40   struct gl_context *ctx = &intel->ctx;
41   struct brw_clip_unit_state *clip;
42
43   clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
44			  sizeof(*clip), 32, &brw->clip.state_offset);
45   memset(clip, 0, sizeof(*clip));
46
47   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_CLIP_PROG */
48   clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
49				 16 - 1);
50   clip->thread0.kernel_start_pointer =
51      brw_program_reloc(brw,
52			brw->clip.state_offset +
53			offsetof(struct brw_clip_unit_state, thread0),
54			brw->clip.prog_offset +
55			(clip->thread0.grf_reg_count << 1)) >> 6;
56
57   clip->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
58   clip->thread1.single_program_flow = 1;
59
60   clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
61   clip->thread3.const_urb_entry_read_length =
62      brw->clip.prog_data->curb_read_length;
63
64   /* BRW_NEW_CURBE_OFFSETS */
65   clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
66   clip->thread3.dispatch_grf_start_reg = 1;
67   clip->thread3.urb_entry_read_offset = 0;
68
69   /* BRW_NEW_URB_FENCE */
70   clip->thread4.nr_urb_entries = brw->urb.nr_clip_entries;
71   clip->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
72   /* If we have enough clip URB entries to run two threads, do so.
73    */
74   if (brw->urb.nr_clip_entries >= 10) {
75      /* Half of the URB entries go to each thread, and it has to be an
76       * even number.
77       */
78      assert(brw->urb.nr_clip_entries % 2 == 0);
79
80      /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
81       * only 2 threads can output VUEs at a time.
82       */
83      if (intel->gen == 5)
84         clip->thread4.max_threads = 16 - 1;
85      else
86         clip->thread4.max_threads = 2 - 1;
87   } else {
88      assert(brw->urb.nr_clip_entries >= 5);
89      clip->thread4.max_threads = 1 - 1;
90   }
91
92   if (unlikely(INTEL_DEBUG & DEBUG_STATS))
93      clip->thread4.stats_enable = 1;
94
95   clip->clip5.userclip_enable_flags = 0x7f;
96   clip->clip5.userclip_must_clip = 1;
97   clip->clip5.guard_band_enable = 0;
98   /* _NEW_TRANSFORM */
99   if (!ctx->Transform.DepthClamp)
100      clip->clip5.viewport_z_clip_enable = 1;
101   clip->clip5.viewport_xy_clip_enable = 1;
102   clip->clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
103   clip->clip5.api_mode = BRW_CLIP_API_OGL;
104   clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
105
106   if (intel->is_g4x)
107      clip->clip5.negative_w_clip_test = 1;
108
109   clip->clip6.clipper_viewport_state_ptr = 0;
110   clip->viewport_xmin = -1;
111   clip->viewport_xmax = 1;
112   clip->viewport_ymin = -1;
113   clip->viewport_ymax = 1;
114
115   brw->state.dirty.cache |= CACHE_NEW_CLIP_UNIT;
116}
117
118const struct brw_tracked_state brw_clip_unit = {
119   .dirty = {
120      .mesa  = _NEW_TRANSFORM,
121      .brw   = (BRW_NEW_BATCH |
122		BRW_NEW_PROGRAM_CACHE |
123		BRW_NEW_CURBE_OFFSETS |
124		BRW_NEW_URB_FENCE),
125      .cache = CACHE_NEW_CLIP_PROG
126   },
127   .emit = brw_upload_clip_unit,
128};
129