1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28  * Authors:
29  *   Keith Whitwell <keith@tungstengraphics.com>
30  */
31
32
33
34#include "main/mtypes.h"
35#include "main/macros.h"
36#include "main/fbobject.h"
37#include "brw_context.h"
38#include "brw_state.h"
39#include "brw_defines.h"
40#include "brw_sf.h"
41
42static void upload_sf_vp(struct brw_context *brw)
43{
44   struct intel_context *intel = &brw->intel;
45   struct gl_context *ctx = &intel->ctx;
46   const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
47   struct brw_sf_viewport *sfv;
48   GLfloat y_scale, y_bias;
49   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
50   const GLfloat *v = ctx->Viewport._WindowMap.m;
51
52   sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
53			 sizeof(*sfv), 32, &brw->sf.vp_offset);
54   memset(sfv, 0, sizeof(*sfv));
55
56   if (render_to_fbo) {
57      y_scale = 1.0;
58      y_bias = 0;
59   }
60   else {
61      y_scale = -1.0;
62      y_bias = ctx->DrawBuffer->Height;
63   }
64
65   /* _NEW_VIEWPORT */
66
67   sfv->viewport.m00 = v[MAT_SX];
68   sfv->viewport.m11 = v[MAT_SY] * y_scale;
69   sfv->viewport.m22 = v[MAT_SZ] * depth_scale;
70   sfv->viewport.m30 = v[MAT_TX];
71   sfv->viewport.m31 = v[MAT_TY] * y_scale + y_bias;
72   sfv->viewport.m32 = v[MAT_TZ] * depth_scale;
73
74   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
75    * for DrawBuffer->_[XY]{min,max}
76    */
77
78   /* The scissor only needs to handle the intersection of drawable
79    * and scissor rect, since there are no longer cliprects for shared
80    * buffers with DRI2.
81    *
82    * Note that the hardware's coordinates are inclusive, while Mesa's min is
83    * inclusive but max is exclusive.
84    */
85
86   if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
87       ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
88      /* If the scissor was out of bounds and got clamped to 0
89       * width/height at the bounds, the subtraction of 1 from
90       * maximums could produce a negative number and thus not clip
91       * anything.  Instead, just provide a min > max scissor inside
92       * the bounds, which produces the expected no rendering.
93       */
94      sfv->scissor.xmin = 1;
95      sfv->scissor.xmax = 0;
96      sfv->scissor.ymin = 1;
97      sfv->scissor.ymax = 0;
98   } else if (render_to_fbo) {
99      /* texmemory: Y=0=bottom */
100      sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
101      sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
102      sfv->scissor.ymin = ctx->DrawBuffer->_Ymin;
103      sfv->scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
104   }
105   else {
106      /* memory: Y=0=top */
107      sfv->scissor.xmin = ctx->DrawBuffer->_Xmin;
108      sfv->scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
109      sfv->scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
110      sfv->scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
111   }
112
113   brw->state.dirty.cache |= CACHE_NEW_SF_VP;
114}
115
116const struct brw_tracked_state brw_sf_vp = {
117   .dirty = {
118      .mesa  = (_NEW_VIEWPORT |
119		_NEW_SCISSOR |
120		_NEW_BUFFERS),
121      .brw   = BRW_NEW_BATCH,
122      .cache = 0
123   },
124   .emit = upload_sf_vp
125};
126
127/**
128 * Compute the offset within the URB (expressed in 256-bit register
129 * increments) that should be used to read the VUE in th efragment shader.
130 */
131int
132brw_sf_compute_urb_entry_read_offset(struct intel_context *intel)
133{
134   if (intel->gen == 5)
135      return 3;
136   else
137      return 1;
138}
139
140static void upload_sf_unit( struct brw_context *brw )
141{
142   struct intel_context *intel = &brw->intel;
143   struct gl_context *ctx = &intel->ctx;
144   struct brw_sf_unit_state *sf;
145   drm_intel_bo *bo = intel->batch.bo;
146   int chipset_max_threads;
147   bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
148
149   sf = brw_state_batch(brw, AUB_TRACE_SF_STATE,
150			sizeof(*sf), 64, &brw->sf.state_offset);
151
152   memset(sf, 0, sizeof(*sf));
153
154   /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_SF_PROG */
155   sf->thread0.grf_reg_count = ALIGN(brw->sf.prog_data->total_grf, 16) / 16 - 1;
156   sf->thread0.kernel_start_pointer =
157      brw_program_reloc(brw,
158			brw->sf.state_offset +
159			offsetof(struct brw_sf_unit_state, thread0),
160			brw->sf.prog_offset +
161			(sf->thread0.grf_reg_count << 1)) >> 6;
162
163   sf->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
164
165   sf->thread3.dispatch_grf_start_reg = 3;
166
167   sf->thread3.urb_entry_read_offset =
168      brw_sf_compute_urb_entry_read_offset(intel);
169
170   /* CACHE_NEW_SF_PROG */
171   sf->thread3.urb_entry_read_length = brw->sf.prog_data->urb_read_length;
172
173   /* BRW_NEW_URB_FENCE */
174   sf->thread4.nr_urb_entries = brw->urb.nr_sf_entries;
175   sf->thread4.urb_entry_allocation_size = brw->urb.sfsize - 1;
176
177   /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
178    * 48 (Ironlake) threads.
179    */
180   if (intel->gen == 5)
181      chipset_max_threads = 48;
182   else
183      chipset_max_threads = 24;
184
185   /* BRW_NEW_URB_FENCE */
186   sf->thread4.max_threads = MIN2(chipset_max_threads,
187				  brw->urb.nr_sf_entries) - 1;
188
189   if (unlikely(INTEL_DEBUG & DEBUG_STATS))
190      sf->thread4.stats_enable = 1;
191
192   /* CACHE_NEW_SF_VP */
193   sf->sf5.sf_viewport_state_offset = (intel->batch.bo->offset +
194				       brw->sf.vp_offset) >> 5; /* reloc */
195
196   sf->sf5.viewport_transform = 1;
197
198   /* _NEW_SCISSOR */
199   if (ctx->Scissor.Enabled)
200      sf->sf6.scissor = 1;
201
202   /* _NEW_POLYGON */
203   if (ctx->Polygon.FrontFace == GL_CCW)
204      sf->sf5.front_winding = BRW_FRONTWINDING_CCW;
205   else
206      sf->sf5.front_winding = BRW_FRONTWINDING_CW;
207
208   /* _NEW_BUFFERS
209    * The viewport is inverted for rendering to a FBO, and that inverts
210    * polygon front/back orientation.
211    */
212   sf->sf5.front_winding ^= render_to_fbo;
213
214   /* _NEW_POLYGON */
215   switch (ctx->Polygon.CullFlag ? ctx->Polygon.CullFaceMode : GL_NONE) {
216   case GL_FRONT:
217      sf->sf6.cull_mode = BRW_CULLMODE_FRONT;
218      break;
219   case GL_BACK:
220      sf->sf6.cull_mode = BRW_CULLMODE_BACK;
221      break;
222   case GL_FRONT_AND_BACK:
223      sf->sf6.cull_mode = BRW_CULLMODE_BOTH;
224      break;
225   case GL_NONE:
226      sf->sf6.cull_mode = BRW_CULLMODE_NONE;
227      break;
228   default:
229      assert(0);
230      break;
231   }
232
233   /* _NEW_LINE */
234   /* XXX use ctx->Const.Min/MaxLineWidth here */
235   sf->sf6.line_width = CLAMP(ctx->Line.Width, 1.0, 5.0) * (1<<1);
236
237   sf->sf6.line_endcap_aa_region_width = 1;
238   if (ctx->Line.SmoothFlag)
239      sf->sf6.aa_enable = 1;
240   else if (sf->sf6.line_width <= 0x2)
241       sf->sf6.line_width = 0;
242
243   /* _NEW_BUFFERS */
244   if (!render_to_fbo) {
245      /* Rendering to an OpenGL window */
246      sf->sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
247   }
248   else {
249      /* If rendering to an FBO, the pixel coordinate system is
250       * inverted with respect to the normal OpenGL coordinate
251       * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
252       * But this value is listed as "Reserved, but not seen as useful"
253       * in Intel documentation (page 212, "Point Rasterization Rule",
254       * section 7.4 "SF Pipeline State Summary", of document
255       * "Intel® 965 Express Chipset Family and Intel® G35 Express
256       * Chipset Graphics Controller Programmer's Reference Manual,
257       * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
258       * available at
259       *     http://intellinuxgraphics.org/documentation.html
260       * at the time of this writing).
261       *
262       * It does work on at least some devices, if not all;
263       * if devices that don't support it can be identified,
264       * the likely failure case is that points are rasterized
265       * incorrectly, which is no worse than occurs without
266       * the value, so we're using it here.
267       */
268      sf->sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
269   }
270   /* XXX clamp max depends on AA vs. non-AA */
271
272   /* _NEW_POINT */
273   sf->sf7.sprite_point = ctx->Point.PointSprite;
274   sf->sf7.point_size = CLAMP(rint(CLAMP(ctx->Point.Size,
275					 ctx->Point.MinSize,
276					 ctx->Point.MaxSize)), 1, 255) * (1<<3);
277   /* _NEW_PROGRAM | _NEW_POINT */
278   sf->sf7.use_point_size_state = !(ctx->VertexProgram.PointSizeEnabled ||
279				    ctx->Point._Attenuated);
280   sf->sf7.aa_line_distance_mode = 0;
281
282   /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
283    * _NEW_LIGHT
284    */
285   if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
286      sf->sf7.trifan_pv = 2;
287      sf->sf7.linestrip_pv = 1;
288      sf->sf7.tristrip_pv = 2;
289   } else {
290      sf->sf7.trifan_pv = 1;
291      sf->sf7.linestrip_pv = 0;
292      sf->sf7.tristrip_pv = 0;
293   }
294   sf->sf7.line_last_pixel_enable = 0;
295
296   /* Set bias for OpenGL rasterization rules:
297    */
298   sf->sf6.dest_org_vbias = 0x8;
299   sf->sf6.dest_org_hbias = 0x8;
300
301   /* STATE_PREFETCH command description describes this state as being
302    * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
303    */
304
305   /* Emit SF viewport relocation */
306   drm_intel_bo_emit_reloc(bo, (brw->sf.state_offset +
307				offsetof(struct brw_sf_unit_state, sf5)),
308			   intel->batch.bo, (brw->sf.vp_offset |
309					     sf->sf5.front_winding |
310					     (sf->sf5.viewport_transform << 1)),
311			   I915_GEM_DOMAIN_INSTRUCTION, 0);
312
313   brw->state.dirty.cache |= CACHE_NEW_SF_UNIT;
314}
315
316const struct brw_tracked_state brw_sf_unit = {
317   .dirty = {
318      .mesa  = (_NEW_POLYGON |
319		_NEW_PROGRAM |
320		_NEW_LIGHT |
321		_NEW_LINE |
322		_NEW_POINT |
323		_NEW_SCISSOR |
324		_NEW_BUFFERS),
325      .brw   = (BRW_NEW_BATCH |
326		BRW_NEW_PROGRAM_CACHE |
327		BRW_NEW_URB_FENCE),
328      .cache = (CACHE_NEW_SF_VP |
329		CACHE_NEW_SF_PROG)
330   },
331   .emit = upload_sf_unit,
332};
333